sbus.c revision 1.80 1 1.80 thorpej /* $NetBSD: sbus.c,v 1.80 2020/11/22 03:55:33 thorpej Exp $ */
2 1.20 pk
3 1.20 pk /*-
4 1.20 pk * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 1.20 pk * All rights reserved.
6 1.20 pk *
7 1.20 pk * This code is derived from software contributed to The NetBSD Foundation
8 1.20 pk * by Paul Kranenburg.
9 1.20 pk *
10 1.20 pk * Redistribution and use in source and binary forms, with or without
11 1.20 pk * modification, are permitted provided that the following conditions
12 1.20 pk * are met:
13 1.20 pk * 1. Redistributions of source code must retain the above copyright
14 1.20 pk * notice, this list of conditions and the following disclaimer.
15 1.20 pk * 2. Redistributions in binary form must reproduce the above copyright
16 1.20 pk * notice, this list of conditions and the following disclaimer in the
17 1.20 pk * documentation and/or other materials provided with the distribution.
18 1.20 pk *
19 1.20 pk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.20 pk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.20 pk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.20 pk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.20 pk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.20 pk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.20 pk * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.20 pk * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.20 pk * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.20 pk * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.20 pk * POSSIBILITY OF SUCH DAMAGE.
30 1.20 pk */
31 1.4 deraadt
32 1.1 deraadt /*
33 1.1 deraadt * Copyright (c) 1992, 1993
34 1.1 deraadt * The Regents of the University of California. All rights reserved.
35 1.1 deraadt *
36 1.1 deraadt * This software was developed by the Computer Systems Engineering group
37 1.1 deraadt * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
38 1.1 deraadt * contributed to Berkeley.
39 1.1 deraadt *
40 1.1 deraadt * All advertising materials mentioning features or use of this software
41 1.1 deraadt * must display the following acknowledgement:
42 1.1 deraadt * This product includes software developed by the University of
43 1.1 deraadt * California, Lawrence Berkeley Laboratory.
44 1.1 deraadt *
45 1.1 deraadt * Redistribution and use in source and binary forms, with or without
46 1.1 deraadt * modification, are permitted provided that the following conditions
47 1.1 deraadt * are met:
48 1.1 deraadt * 1. Redistributions of source code must retain the above copyright
49 1.1 deraadt * notice, this list of conditions and the following disclaimer.
50 1.1 deraadt * 2. Redistributions in binary form must reproduce the above copyright
51 1.1 deraadt * notice, this list of conditions and the following disclaimer in the
52 1.1 deraadt * documentation and/or other materials provided with the distribution.
53 1.58 agc * 3. Neither the name of the University nor the names of its contributors
54 1.1 deraadt * may be used to endorse or promote products derived from this software
55 1.1 deraadt * without specific prior written permission.
56 1.1 deraadt *
57 1.1 deraadt * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
58 1.1 deraadt * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
59 1.1 deraadt * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
60 1.1 deraadt * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
61 1.1 deraadt * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
62 1.1 deraadt * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
63 1.1 deraadt * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
64 1.1 deraadt * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
65 1.1 deraadt * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
66 1.1 deraadt * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 1.1 deraadt * SUCH DAMAGE.
68 1.1 deraadt *
69 1.1 deraadt * @(#)sbus.c 8.1 (Berkeley) 6/11/93
70 1.1 deraadt */
71 1.1 deraadt
72 1.1 deraadt /*
73 1.1 deraadt * Sbus stuff.
74 1.1 deraadt */
75 1.57 lukem
76 1.57 lukem #include <sys/cdefs.h>
77 1.80 thorpej __KERNEL_RCSID(0, "$NetBSD: sbus.c,v 1.80 2020/11/22 03:55:33 thorpej Exp $");
78 1.1 deraadt
79 1.1 deraadt #include <sys/param.h>
80 1.16 pk #include <sys/malloc.h>
81 1.80 thorpej #include <sys/kmem.h>
82 1.32 pk #include <sys/kernel.h>
83 1.7 christos #include <sys/systm.h>
84 1.1 deraadt #include <sys/device.h>
85 1.37 mrg
86 1.37 mrg #include <uvm/uvm_extern.h>
87 1.1 deraadt
88 1.47 thorpej #include <machine/autoconf.h>
89 1.75 dyoung #include <sys/bus.h>
90 1.19 pk #include <sparc/dev/sbusreg.h>
91 1.25 pk #include <dev/sbus/sbusvar.h>
92 1.25 pk #include <dev/sbus/xboxvar.h>
93 1.19 pk
94 1.19 pk #include <sparc/sparc/iommuvar.h>
95 1.1 deraadt
96 1.65 uwe void sbusreset(int);
97 1.8 thorpej
98 1.65 uwe static int sbus_get_intr(struct sbus_softc *, int,
99 1.65 uwe struct openprom_intr **, int *);
100 1.65 uwe static void *sbus_intr_establish(
101 1.23 pk bus_space_tag_t,
102 1.65 uwe int, /* Sbus interrupt level */
103 1.65 uwe int, /* `device class' priority */
104 1.65 uwe int (*)(void *), /* handler */
105 1.65 uwe void *, /* handler arg */
106 1.65 uwe void (*)(void)); /* fast handler */
107 1.19 pk
108 1.19 pk
109 1.1 deraadt /* autoconfiguration driver */
110 1.69 macallan int sbus_match_mainbus(device_t, struct cfdata *, void *);
111 1.69 macallan int sbus_match_iommu(device_t, struct cfdata *, void *);
112 1.69 macallan int sbus_match_xbox(device_t, struct cfdata *, void *);
113 1.69 macallan void sbus_attach_mainbus(device_t, device_t, void *);
114 1.69 macallan void sbus_attach_iommu(device_t, device_t, void *);
115 1.69 macallan void sbus_attach_xbox(device_t, device_t, void *);
116 1.8 thorpej
117 1.78 jdc #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D)
118 1.65 uwe static int sbus_error(void);
119 1.77 matt extern int (*sbuserr_handler)(void);
120 1.78 jdc #endif
121 1.32 pk
122 1.69 macallan CFATTACH_DECL_NEW(sbus_mainbus, sizeof(struct sbus_softc),
123 1.52 thorpej sbus_match_mainbus, sbus_attach_mainbus, NULL, NULL);
124 1.51 thorpej
125 1.69 macallan CFATTACH_DECL_NEW(sbus_iommu, sizeof(struct sbus_softc),
126 1.52 thorpej sbus_match_iommu, sbus_attach_iommu, NULL, NULL);
127 1.51 thorpej
128 1.69 macallan CFATTACH_DECL_NEW(sbus_xbox, sizeof(struct sbus_softc),
129 1.52 thorpej sbus_match_xbox, sbus_attach_xbox, NULL, NULL);
130 1.7 christos
131 1.18 thorpej extern struct cfdriver sbus_cd;
132 1.1 deraadt
133 1.63 chs static int sbus_mainbus_attached;
134 1.63 chs
135 1.32 pk /* The "primary" Sbus */
136 1.32 pk struct sbus_softc *sbus_sc;
137 1.32 pk
138 1.19 pk /* If the PROM does not provide the `ranges' property, we make up our own */
139 1.46 thorpej struct openprom_range sbus_translations[] = {
140 1.19 pk /* Assume a maximum of 4 Sbus slots, all mapped to on-board io space */
141 1.19 pk { 0, 0, PMAP_OBIO, SBUS_ADDR(0,0), 1 << 25 },
142 1.19 pk { 1, 0, PMAP_OBIO, SBUS_ADDR(1,0), 1 << 25 },
143 1.19 pk { 2, 0, PMAP_OBIO, SBUS_ADDR(2,0), 1 << 25 },
144 1.19 pk { 3, 0, PMAP_OBIO, SBUS_ADDR(3,0), 1 << 25 }
145 1.19 pk };
146 1.19 pk
147 1.19 pk /*
148 1.19 pk * Child devices receive the Sbus interrupt level in their attach
149 1.19 pk * arguments. We translate these to CPU IPLs using the following
150 1.19 pk * tables. Note: obio bus interrupt levels are identical to the
151 1.19 pk * processor IPL.
152 1.19 pk *
153 1.19 pk * The second set of tables is used when the Sbus interrupt level
154 1.19 pk * cannot be had from the PROM as an `interrupt' property. We then
155 1.19 pk * fall back on the `intr' property which contains the CPU IPL.
156 1.19 pk */
157 1.19 pk
158 1.19 pk /* Translate Sbus interrupt level to processor IPL */
159 1.19 pk static int intr_sbus2ipl_4c[] = {
160 1.19 pk 0, 1, 2, 3, 5, 7, 8, 9
161 1.19 pk };
162 1.19 pk static int intr_sbus2ipl_4m[] = {
163 1.19 pk 0, 2, 3, 5, 7, 9, 11, 13
164 1.19 pk };
165 1.19 pk
166 1.20 pk /*
167 1.20 pk * This value is or'ed into the attach args' interrupt level cookie
168 1.20 pk * if the interrupt level comes from an `intr' property, i.e. it is
169 1.20 pk * not an Sbus interrupt level.
170 1.20 pk */
171 1.19 pk #define SBUS_INTR_COMPAT 0x80000000
172 1.19 pk
173 1.19 pk
174 1.1 deraadt /*
175 1.1 deraadt * Print the location of some sbus-attached device (called just
176 1.1 deraadt * before attaching that device). If `sbus' is not NULL, the
177 1.1 deraadt * device was found but not configured; print the sbus as well.
178 1.1 deraadt * Return UNCONF (config_find ignores this if the device was configured).
179 1.1 deraadt */
180 1.1 deraadt int
181 1.65 uwe sbus_print(void *args, const char *busname)
182 1.1 deraadt {
183 1.19 pk struct sbus_attach_args *sa = args;
184 1.26 pk int i;
185 1.1 deraadt
186 1.19 pk if (busname)
187 1.56 thorpej aprint_normal("%s at %s", sa->sa_name, busname);
188 1.56 thorpej aprint_normal(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset);
189 1.26 pk for (i = 0; i < sa->sa_nintr; i++) {
190 1.65 uwe uint32_t level = sa->sa_intr[i].oi_pri;
191 1.19 pk struct sbus_softc *sc =
192 1.19 pk (struct sbus_softc *) sa->sa_bustag->cookie;
193 1.19 pk
194 1.56 thorpej aprint_normal(" level %d", level & ~SBUS_INTR_COMPAT);
195 1.19 pk if ((level & SBUS_INTR_COMPAT) == 0) {
196 1.19 pk int ipl = sc->sc_intr2ipl[level];
197 1.19 pk if (ipl != level)
198 1.56 thorpej aprint_normal(" (ipl %d)", ipl);
199 1.19 pk }
200 1.19 pk }
201 1.1 deraadt return (UNCONF);
202 1.1 deraadt }
203 1.1 deraadt
204 1.3 deraadt int
205 1.69 macallan sbus_match_mainbus(device_t parent, struct cfdata *cf, void *aux)
206 1.19 pk {
207 1.19 pk struct mainbus_attach_args *ma = aux;
208 1.19 pk
209 1.63 chs if (CPU_ISSUN4 || sbus_mainbus_attached)
210 1.19 pk return (0);
211 1.19 pk
212 1.49 thorpej return (strcmp(cf->cf_name, ma->ma_name) == 0);
213 1.19 pk }
214 1.19 pk
215 1.19 pk int
216 1.69 macallan sbus_match_iommu(device_t parent, struct cfdata *cf, void *aux)
217 1.3 deraadt {
218 1.19 pk struct iommu_attach_args *ia = aux;
219 1.3 deraadt
220 1.9 pk if (CPU_ISSUN4)
221 1.3 deraadt return (0);
222 1.9 pk
223 1.49 thorpej return (strcmp(cf->cf_name, ia->iom_name) == 0);
224 1.3 deraadt }
225 1.3 deraadt
226 1.24 pk int
227 1.69 macallan sbus_match_xbox(device_t parent, struct cfdata *cf, void *aux)
228 1.24 pk {
229 1.24 pk struct xbox_attach_args *xa = aux;
230 1.24 pk
231 1.24 pk if (CPU_ISSUN4)
232 1.24 pk return (0);
233 1.24 pk
234 1.49 thorpej return (strcmp(cf->cf_name, xa->xa_name) == 0);
235 1.24 pk }
236 1.24 pk
237 1.1 deraadt /*
238 1.1 deraadt * Attach an Sbus.
239 1.1 deraadt */
240 1.1 deraadt void
241 1.69 macallan sbus_attach_mainbus(device_t parent, device_t self, void *aux)
242 1.1 deraadt {
243 1.69 macallan struct sbus_softc *sc = device_private(self);
244 1.19 pk struct mainbus_attach_args *ma = aux;
245 1.19 pk int node = ma->ma_node;
246 1.1 deraadt
247 1.63 chs sbus_mainbus_attached = 1;
248 1.1 deraadt
249 1.69 macallan sc->sc_dev = self;
250 1.19 pk sc->sc_bustag = ma->ma_bustag;
251 1.19 pk sc->sc_dmatag = ma->ma_dmatag;
252 1.19 pk
253 1.33 pk #if 0 /* sbus at mainbus (sun4c): `reg' prop is not control space */
254 1.32 pk if (ma->ma_size == 0)
255 1.69 macallan printf("%s: no Sbus registers", device_xname(self));
256 1.32 pk
257 1.45 pk if (bus_space_map(ma->ma_bustag,
258 1.45 pk ma->ma_paddr,
259 1.45 pk ma->ma_size,
260 1.32 pk BUS_SPACE_MAP_LINEAR,
261 1.45 pk &sc->sc_bh) != 0) {
262 1.69 macallan panic("%s: can't map sbusbusreg", device_xname(self));
263 1.32 pk }
264 1.33 pk #endif
265 1.32 pk
266 1.19 pk /* Setup interrupt translation tables */
267 1.19 pk sc->sc_intr2ipl = CPU_ISSUN4C
268 1.19 pk ? intr_sbus2ipl_4c
269 1.19 pk : intr_sbus2ipl_4m;
270 1.19 pk
271 1.19 pk /*
272 1.19 pk * Record clock frequency for synchronous SCSI.
273 1.19 pk * IS THIS THE CORRECT DEFAULT??
274 1.19 pk */
275 1.60 pk sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000);
276 1.19 pk printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
277 1.19 pk
278 1.32 pk sbus_sc = sc;
279 1.36 pk sbus_attach_common(sc, "sbus", node, NULL);
280 1.19 pk }
281 1.19 pk
282 1.32 pk
283 1.19 pk void
284 1.69 macallan sbus_attach_iommu(device_t parent, device_t self, void *aux)
285 1.19 pk {
286 1.69 macallan struct sbus_softc *sc = device_private(self);
287 1.19 pk struct iommu_attach_args *ia = aux;
288 1.19 pk int node = ia->iom_node;
289 1.19 pk
290 1.69 macallan sc->sc_dev = self;
291 1.19 pk sc->sc_bustag = ia->iom_bustag;
292 1.19 pk sc->sc_dmatag = ia->iom_dmatag;
293 1.19 pk
294 1.32 pk if (ia->iom_nreg == 0)
295 1.69 macallan panic("%s: no Sbus registers", device_xname(self));
296 1.32 pk
297 1.45 pk if (bus_space_map(ia->iom_bustag,
298 1.46 thorpej BUS_ADDR(ia->iom_reg[0].oa_space,
299 1.46 thorpej ia->iom_reg[0].oa_base),
300 1.46 thorpej (bus_size_t)ia->iom_reg[0].oa_size,
301 1.32 pk BUS_SPACE_MAP_LINEAR,
302 1.45 pk &sc->sc_bh) != 0) {
303 1.69 macallan panic("%s: can't map sbusbusreg", device_xname(self));
304 1.32 pk }
305 1.32 pk
306 1.19 pk /* Setup interrupt translation tables */
307 1.19 pk sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m;
308 1.19 pk
309 1.1 deraadt /*
310 1.1 deraadt * Record clock frequency for synchronous SCSI.
311 1.1 deraadt * IS THIS THE CORRECT DEFAULT??
312 1.1 deraadt */
313 1.60 pk sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000);
314 1.13 christos printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
315 1.10 abrown
316 1.32 pk sbus_sc = sc;
317 1.78 jdc #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D)
318 1.32 pk sbuserr_handler = sbus_error;
319 1.78 jdc #endif
320 1.36 pk sbus_attach_common(sc, "sbus", node, NULL);
321 1.24 pk }
322 1.24 pk
323 1.24 pk void
324 1.69 macallan sbus_attach_xbox(device_t parent, device_t self, void *aux)
325 1.24 pk {
326 1.69 macallan struct sbus_softc *sc = device_private(self);
327 1.24 pk struct xbox_attach_args *xa = aux;
328 1.24 pk int node = xa->xa_node;
329 1.24 pk
330 1.24 pk sc->sc_bustag = xa->xa_bustag;
331 1.24 pk sc->sc_dmatag = xa->xa_dmatag;
332 1.24 pk
333 1.24 pk /* Setup interrupt translation tables */
334 1.24 pk sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m;
335 1.24 pk
336 1.24 pk /*
337 1.24 pk * Record clock frequency for synchronous SCSI.
338 1.24 pk * IS THIS THE CORRECT DEFAULT??
339 1.24 pk */
340 1.60 pk sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000);
341 1.24 pk printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
342 1.24 pk
343 1.36 pk sbus_attach_common(sc, "sbus", node, NULL);
344 1.19 pk }
345 1.19 pk
346 1.19 pk void
347 1.65 uwe sbus_attach_common(struct sbus_softc *sc, const char *busname, int busnode,
348 1.65 uwe const char * const *specials)
349 1.19 pk {
350 1.19 pk int node0, node, error;
351 1.19 pk const char *sp;
352 1.19 pk const char *const *ssp;
353 1.19 pk bus_space_tag_t sbt;
354 1.19 pk struct sbus_attach_args sa;
355 1.19 pk
356 1.62 pk if ((sbt = bus_space_tag_alloc(sc->sc_bustag, sc)) == NULL) {
357 1.69 macallan printf("%s: attach: out of memory\n",
358 1.69 macallan device_xname(sc->sc_dev));
359 1.62 pk return;
360 1.62 pk }
361 1.62 pk sbt->sparc_intr_establish = sbus_intr_establish;
362 1.19 pk
363 1.10 abrown /*
364 1.10 abrown * Get the SBus burst transfer size if burst transfers are supported
365 1.10 abrown */
366 1.60 pk sc->sc_burst = prom_getpropint(busnode, "burst-sizes", 0);
367 1.35 pk
368 1.35 pk
369 1.35 pk if (CPU_ISSUN4M) {
370 1.35 pk /*
371 1.35 pk * Some models (e.g. SS20) erroneously report 64-bit
372 1.35 pk * burst capability. We mask it out here for all SUN4Ms,
373 1.35 pk * since probably no member of that class supports
374 1.35 pk * 64-bit Sbus bursts.
375 1.35 pk */
376 1.35 pk sc->sc_burst &= ~SBUS_BURST_64;
377 1.35 pk }
378 1.1 deraadt
379 1.19 pk /*
380 1.19 pk * Collect address translations from the OBP.
381 1.19 pk */
382 1.60 pk error = prom_getprop(busnode, "ranges", sizeof(struct rom_range),
383 1.59 mrg &sbt->nranges, &sbt->ranges);
384 1.19 pk switch (error) {
385 1.19 pk case 0:
386 1.19 pk break;
387 1.19 pk case ENOENT:
388 1.19 pk /* Fall back to our own `range' construction */
389 1.48 thorpej sbt->ranges = sbus_translations;
390 1.48 thorpej sbt->nranges =
391 1.19 pk sizeof(sbus_translations)/sizeof(sbus_translations[0]);
392 1.19 pk break;
393 1.19 pk default:
394 1.69 macallan panic("%s: error getting ranges property",
395 1.69 macallan device_xname(sc->sc_dev));
396 1.16 pk }
397 1.9 pk
398 1.1 deraadt /*
399 1.1 deraadt * Loop through ROM children, fixing any relative addresses
400 1.1 deraadt * and then configuring each device.
401 1.19 pk * `specials' is an array of device names that are treated
402 1.19 pk * specially:
403 1.1 deraadt */
404 1.19 pk node0 = firstchild(busnode);
405 1.19 pk for (ssp = specials ; ssp != NULL && *(sp = *ssp) != 0; ssp++) {
406 1.19 pk if ((node = findnode(node0, sp)) == 0) {
407 1.19 pk panic("could not find %s amongst %s devices",
408 1.19 pk sp, busname);
409 1.19 pk }
410 1.19 pk
411 1.19 pk if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag,
412 1.36 pk node, &sa) != 0) {
413 1.19 pk panic("sbus_attach: %s: incomplete", sp);
414 1.19 pk }
415 1.69 macallan (void) config_found(sc->sc_dev, (void *)&sa, sbus_print);
416 1.26 pk sbus_destroy_attach_args(&sa);
417 1.19 pk }
418 1.19 pk
419 1.19 pk for (node = node0; node; node = nextsibling(node)) {
420 1.60 pk char *name = prom_getpropstring(node, "name");
421 1.19 pk for (ssp = specials, sp = NULL;
422 1.19 pk ssp != NULL && (sp = *ssp) != NULL;
423 1.19 pk ssp++)
424 1.19 pk if (strcmp(name, sp) == 0)
425 1.19 pk break;
426 1.19 pk
427 1.19 pk if (sp != NULL)
428 1.19 pk /* Already configured as an "early" device */
429 1.19 pk continue;
430 1.19 pk
431 1.19 pk if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag,
432 1.36 pk node, &sa) != 0) {
433 1.19 pk printf("sbus_attach: %s: incomplete\n", name);
434 1.1 deraadt continue;
435 1.19 pk }
436 1.69 macallan (void) config_found(sc->sc_dev, (void *)&sa, sbus_print);
437 1.26 pk sbus_destroy_attach_args(&sa);
438 1.19 pk }
439 1.19 pk }
440 1.9 pk
441 1.19 pk int
442 1.65 uwe sbus_setup_attach_args(struct sbus_softc *sc,
443 1.65 uwe bus_space_tag_t bustag, bus_dma_tag_t dmatag, int node,
444 1.65 uwe struct sbus_attach_args *sa)
445 1.19 pk {
446 1.32 pk int n, error;
447 1.19 pk
448 1.72 cegger memset(sa, 0, sizeof(struct sbus_attach_args));
449 1.60 pk error = prom_getprop(node, "name", 1, &n, &sa->sa_name);
450 1.26 pk if (error != 0)
451 1.26 pk return (error);
452 1.76 mrg KASSERT(sa->sa_name[n-1] == '\0');
453 1.26 pk
454 1.19 pk sa->sa_bustag = bustag;
455 1.19 pk sa->sa_dmatag = dmatag;
456 1.19 pk sa->sa_node = node;
457 1.39 eeh sa->sa_frequency = sc->sc_clockfreq;
458 1.19 pk
459 1.60 pk error = prom_getprop(node, "reg", sizeof(struct openprom_addr),
460 1.59 mrg &sa->sa_nreg, &sa->sa_reg);
461 1.26 pk if (error != 0) {
462 1.26 pk char buf[32];
463 1.26 pk if (error != ENOENT ||
464 1.26 pk !node_has_property(node, "device_type") ||
465 1.60 pk strcmp(prom_getpropstringA(node, "device_type", buf, sizeof buf),
466 1.26 pk "hierarchical") != 0)
467 1.26 pk return (error);
468 1.26 pk }
469 1.26 pk for (n = 0; n < sa->sa_nreg; n++) {
470 1.26 pk /* Convert to relative addressing, if necessary */
471 1.65 uwe uint32_t base = sa->sa_reg[n].oa_base;
472 1.26 pk if (SBUS_ABS(base)) {
473 1.46 thorpej sa->sa_reg[n].oa_space = SBUS_ABS_TO_SLOT(base);
474 1.46 thorpej sa->sa_reg[n].oa_base = SBUS_ABS_TO_OFFSET(base);
475 1.26 pk }
476 1.9 pk }
477 1.19 pk
478 1.26 pk if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr)) != 0)
479 1.19 pk return (error);
480 1.19 pk
481 1.65 uwe error = prom_getprop(node, "address", sizeof(uint32_t),
482 1.59 mrg &sa->sa_npromvaddrs, &sa->sa_promvaddrs);
483 1.26 pk if (error != 0 && error != ENOENT)
484 1.19 pk return (error);
485 1.19 pk
486 1.19 pk return (0);
487 1.9 pk }
488 1.9 pk
489 1.26 pk void
490 1.65 uwe sbus_destroy_attach_args(struct sbus_attach_args *sa)
491 1.26 pk {
492 1.65 uwe
493 1.26 pk if (sa->sa_name != NULL)
494 1.26 pk free(sa->sa_name, M_DEVBUF);
495 1.26 pk
496 1.26 pk if (sa->sa_nreg != 0)
497 1.26 pk free(sa->sa_reg, M_DEVBUF);
498 1.26 pk
499 1.26 pk if (sa->sa_intr)
500 1.26 pk free(sa->sa_intr, M_DEVBUF);
501 1.26 pk
502 1.26 pk if (sa->sa_promvaddrs)
503 1.26 pk free(sa->sa_promvaddrs, M_DEVBUF);
504 1.26 pk
505 1.72 cegger memset(sa, 0, sizeof(struct sbus_attach_args));/*DEBUG*/
506 1.26 pk }
507 1.26 pk
508 1.40 eeh bus_addr_t
509 1.65 uwe sbus_bus_addr(bus_space_tag_t t, u_int btype, u_int offset)
510 1.40 eeh {
511 1.40 eeh
512 1.44 uwe /* XXX: sbus_bus_addr should be g/c'ed */
513 1.44 uwe return (BUS_ADDR(btype, offset));
514 1.1 deraadt }
515 1.1 deraadt
516 1.19 pk
517 1.1 deraadt /*
518 1.19 pk * Get interrupt attributes for an Sbus device.
519 1.19 pk */
520 1.65 uwe static int
521 1.65 uwe sbus_get_intr(struct sbus_softc *sc, int node,
522 1.65 uwe struct openprom_intr **ipp, int *np)
523 1.19 pk {
524 1.26 pk int error, n;
525 1.65 uwe uint32_t *ipl = NULL;
526 1.19 pk
527 1.19 pk /*
528 1.19 pk * The `interrupts' property contains the Sbus interrupt level.
529 1.19 pk */
530 1.60 pk if (prom_getprop(node, "interrupts", sizeof(int), np,
531 1.59 mrg &ipl) == 0) {
532 1.46 thorpej /* Change format to an `struct openprom_intr' array */
533 1.46 thorpej struct openprom_intr *ip;
534 1.46 thorpej ip = malloc(*np * sizeof(struct openprom_intr), M_DEVBUF,
535 1.79 chs M_WAITOK);
536 1.26 pk for (n = 0; n < *np; n++) {
537 1.46 thorpej ip[n].oi_pri = ipl[n];
538 1.46 thorpej ip[n].oi_vec = 0;
539 1.26 pk }
540 1.19 pk free(ipl, M_DEVBUF);
541 1.26 pk *ipp = ip;
542 1.19 pk return (0);
543 1.19 pk }
544 1.19 pk
545 1.19 pk /*
546 1.19 pk * Fall back on `intr' property.
547 1.19 pk */
548 1.26 pk *ipp = NULL;
549 1.60 pk error = prom_getprop(node, "intr", sizeof(struct openprom_intr),
550 1.59 mrg np, ipp);
551 1.26 pk switch (error) {
552 1.19 pk case 0:
553 1.26 pk for (n = *np; n-- > 0;) {
554 1.46 thorpej (*ipp)[n].oi_pri &= 0xf;
555 1.46 thorpej (*ipp)[n].oi_pri |= SBUS_INTR_COMPAT;
556 1.26 pk }
557 1.26 pk break;
558 1.19 pk case ENOENT:
559 1.26 pk error = 0;
560 1.26 pk break;
561 1.19 pk }
562 1.19 pk
563 1.26 pk return (error);
564 1.19 pk }
565 1.19 pk
566 1.19 pk
567 1.19 pk /*
568 1.19 pk * Install an interrupt handler for an Sbus device.
569 1.19 pk */
570 1.65 uwe static void *
571 1.65 uwe sbus_intr_establish(bus_space_tag_t t, int pri, int level,
572 1.65 uwe int (*handler)(void *), void *arg,
573 1.65 uwe void (*fastvec)(void))
574 1.19 pk {
575 1.22 pk struct sbus_softc *sc = t->cookie;
576 1.19 pk struct intrhand *ih;
577 1.38 pk int pil;
578 1.19 pk
579 1.80 thorpej ih = kmem_alloc(sizeof(struct intrhand), KM_SLEEP);
580 1.19 pk
581 1.38 pk /*
582 1.38 pk * Translate Sbus interrupt priority to CPU interrupt level
583 1.38 pk */
584 1.54 pk if ((pri & SBUS_INTR_COMPAT) != 0)
585 1.38 pk pil = pri & ~SBUS_INTR_COMPAT;
586 1.19 pk else
587 1.38 pk pil = sc->sc_intr2ipl[pri];
588 1.19 pk
589 1.19 pk ih->ih_fun = handler;
590 1.19 pk ih->ih_arg = arg;
591 1.74 mrg intr_establish(pil, level, ih, fastvec, false);
592 1.19 pk return (ih);
593 1.19 pk }
594 1.19 pk
595 1.78 jdc #if (defined(SUN4M) && !defined(MSIIEP)) || defined(SUN4D)
596 1.65 uwe static int
597 1.65 uwe sbus_error(void)
598 1.32 pk {
599 1.32 pk struct sbus_softc *sc = sbus_sc;
600 1.32 pk bus_space_handle_t bh = sc->sc_bh;
601 1.65 uwe uint32_t afsr, afva;
602 1.32 pk char bits[64];
603 1.32 pk static int straytime, nstray;
604 1.32 pk int timesince;
605 1.32 pk
606 1.32 pk afsr = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFSR_REG);
607 1.32 pk afva = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFAR_REG);
608 1.71 christos snprintb(bits, sizeof(bits), SBUS_AFSR_BITS, afsr);
609 1.71 christos printf("sbus error:\n\tAFSR %s\n", bits);
610 1.32 pk printf("\taddress: 0x%x%x\n", afsr & SBUS_AFSR_PAH, afva);
611 1.32 pk
612 1.32 pk /* For now, do the same dance as on stray interrupts */
613 1.67 kardel timesince = time_uptime - straytime;
614 1.32 pk if (timesince <= 10) {
615 1.32 pk if (++nstray > 9)
616 1.32 pk panic("too many SBus errors");
617 1.32 pk } else {
618 1.67 kardel straytime = time_uptime;
619 1.32 pk nstray = 1;
620 1.32 pk }
621 1.32 pk
622 1.32 pk /* Unlock registers and clear interrupt */
623 1.32 pk bus_space_write_4(sc->sc_bustag, bh, SBUS_AFSR_REG, afsr);
624 1.32 pk
625 1.32 pk return (0);
626 1.19 pk }
627 1.78 jdc #endif
628