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sbus.c revision 1.67
      1 /*	$NetBSD: sbus.c,v 1.67 2006/06/07 22:38:49 kardel Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Paul Kranenburg.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 /*
     40  * Copyright (c) 1992, 1993
     41  *	The Regents of the University of California.  All rights reserved.
     42  *
     43  * This software was developed by the Computer Systems Engineering group
     44  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
     45  * contributed to Berkeley.
     46  *
     47  * All advertising materials mentioning features or use of this software
     48  * must display the following acknowledgement:
     49  *	This product includes software developed by the University of
     50  *	California, Lawrence Berkeley Laboratory.
     51  *
     52  * Redistribution and use in source and binary forms, with or without
     53  * modification, are permitted provided that the following conditions
     54  * are met:
     55  * 1. Redistributions of source code must retain the above copyright
     56  *    notice, this list of conditions and the following disclaimer.
     57  * 2. Redistributions in binary form must reproduce the above copyright
     58  *    notice, this list of conditions and the following disclaimer in the
     59  *    documentation and/or other materials provided with the distribution.
     60  * 3. Neither the name of the University nor the names of its contributors
     61  *    may be used to endorse or promote products derived from this software
     62  *    without specific prior written permission.
     63  *
     64  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     65  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     66  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     67  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     68  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     69  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     70  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     71  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     72  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     73  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     74  * SUCH DAMAGE.
     75  *
     76  *	@(#)sbus.c	8.1 (Berkeley) 6/11/93
     77  */
     78 
     79 /*
     80  * Sbus stuff.
     81  */
     82 
     83 #include <sys/cdefs.h>
     84 __KERNEL_RCSID(0, "$NetBSD: sbus.c,v 1.67 2006/06/07 22:38:49 kardel Exp $");
     85 
     86 #include <sys/param.h>
     87 #include <sys/malloc.h>
     88 #include <sys/kernel.h>
     89 #include <sys/systm.h>
     90 #include <sys/device.h>
     91 
     92 #include <uvm/uvm_extern.h>
     93 
     94 #include <machine/autoconf.h>
     95 #include <machine/bus.h>
     96 #include <sparc/dev/sbusreg.h>
     97 #include <dev/sbus/sbusvar.h>
     98 #include <dev/sbus/xboxvar.h>
     99 
    100 #include <sparc/sparc/iommuvar.h>
    101 
    102 void sbusreset(int);
    103 
    104 static int sbus_get_intr(struct sbus_softc *, int,
    105 			 struct openprom_intr **, int *);
    106 static void *sbus_intr_establish(
    107 		bus_space_tag_t,
    108 		int,			/* Sbus interrupt level */
    109 		int,			/* `device class' priority */
    110 		int (*)(void *),	/* handler */
    111 		void *,			/* handler arg */
    112 		void (*)(void));	/* fast handler */
    113 
    114 
    115 /* autoconfiguration driver */
    116 int	sbus_match_mainbus(struct device *, struct cfdata *, void *);
    117 int	sbus_match_iommu(struct device *, struct cfdata *, void *);
    118 int	sbus_match_xbox(struct device *, struct cfdata *, void *);
    119 void	sbus_attach_mainbus(struct device *, struct device *, void *);
    120 void	sbus_attach_iommu(struct device *, struct device *, void *);
    121 void	sbus_attach_xbox(struct device *, struct device *, void *);
    122 
    123 static	int sbus_error(void);
    124 int	(*sbuserr_handler)(void);
    125 
    126 CFATTACH_DECL(sbus_mainbus, sizeof(struct sbus_softc),
    127     sbus_match_mainbus, sbus_attach_mainbus, NULL, NULL);
    128 
    129 CFATTACH_DECL(sbus_iommu, sizeof(struct sbus_softc),
    130     sbus_match_iommu, sbus_attach_iommu, NULL, NULL);
    131 
    132 CFATTACH_DECL(sbus_xbox, sizeof(struct sbus_softc),
    133     sbus_match_xbox, sbus_attach_xbox, NULL, NULL);
    134 
    135 extern struct cfdriver sbus_cd;
    136 
    137 static int sbus_mainbus_attached;
    138 
    139 /* The "primary" Sbus */
    140 struct sbus_softc *sbus_sc;
    141 
    142 /* If the PROM does not provide the `ranges' property, we make up our own */
    143 struct openprom_range sbus_translations[] = {
    144 	/* Assume a maximum of 4 Sbus slots, all mapped to on-board io space */
    145 	{ 0, 0, PMAP_OBIO, SBUS_ADDR(0,0), 1 << 25 },
    146 	{ 1, 0, PMAP_OBIO, SBUS_ADDR(1,0), 1 << 25 },
    147 	{ 2, 0, PMAP_OBIO, SBUS_ADDR(2,0), 1 << 25 },
    148 	{ 3, 0, PMAP_OBIO, SBUS_ADDR(3,0), 1 << 25 }
    149 };
    150 
    151 /*
    152  * Child devices receive the Sbus interrupt level in their attach
    153  * arguments. We translate these to CPU IPLs using the following
    154  * tables. Note: obio bus interrupt levels are identical to the
    155  * processor IPL.
    156  *
    157  * The second set of tables is used when the Sbus interrupt level
    158  * cannot be had from the PROM as an `interrupt' property. We then
    159  * fall back on the `intr' property which contains the CPU IPL.
    160  */
    161 
    162 /* Translate Sbus interrupt level to processor IPL */
    163 static int intr_sbus2ipl_4c[] = {
    164 	0, 1, 2, 3, 5, 7, 8, 9
    165 };
    166 static int intr_sbus2ipl_4m[] = {
    167 	0, 2, 3, 5, 7, 9, 11, 13
    168 };
    169 
    170 /*
    171  * This value is or'ed into the attach args' interrupt level cookie
    172  * if the interrupt level comes from an `intr' property, i.e. it is
    173  * not an Sbus interrupt level.
    174  */
    175 #define SBUS_INTR_COMPAT	0x80000000
    176 
    177 
    178 /*
    179  * Print the location of some sbus-attached device (called just
    180  * before attaching that device).  If `sbus' is not NULL, the
    181  * device was found but not configured; print the sbus as well.
    182  * Return UNCONF (config_find ignores this if the device was configured).
    183  */
    184 int
    185 sbus_print(void *args, const char *busname)
    186 {
    187 	struct sbus_attach_args *sa = args;
    188 	int i;
    189 
    190 	if (busname)
    191 		aprint_normal("%s at %s", sa->sa_name, busname);
    192 	aprint_normal(" slot %d offset 0x%x", sa->sa_slot, sa->sa_offset);
    193 	for (i = 0; i < sa->sa_nintr; i++) {
    194 		uint32_t level = sa->sa_intr[i].oi_pri;
    195 		struct sbus_softc *sc =
    196 			(struct sbus_softc *) sa->sa_bustag->cookie;
    197 
    198 		aprint_normal(" level %d", level & ~SBUS_INTR_COMPAT);
    199 		if ((level & SBUS_INTR_COMPAT) == 0) {
    200 			int ipl = sc->sc_intr2ipl[level];
    201 			if (ipl != level)
    202 				aprint_normal(" (ipl %d)", ipl);
    203 		}
    204 	}
    205 	return (UNCONF);
    206 }
    207 
    208 int
    209 sbus_match_mainbus(struct device *parent, struct cfdata *cf, void *aux)
    210 {
    211 	struct mainbus_attach_args *ma = aux;
    212 
    213 	if (CPU_ISSUN4 || sbus_mainbus_attached)
    214 		return (0);
    215 
    216 	return (strcmp(cf->cf_name, ma->ma_name) == 0);
    217 }
    218 
    219 int
    220 sbus_match_iommu(struct device *parent, struct cfdata *cf, void *aux)
    221 {
    222 	struct iommu_attach_args *ia = aux;
    223 
    224 	if (CPU_ISSUN4)
    225 		return (0);
    226 
    227 	return (strcmp(cf->cf_name, ia->iom_name) == 0);
    228 }
    229 
    230 int
    231 sbus_match_xbox(struct device *parent, struct cfdata *cf, void *aux)
    232 {
    233 	struct xbox_attach_args *xa = aux;
    234 
    235 	if (CPU_ISSUN4)
    236 		return (0);
    237 
    238 	return (strcmp(cf->cf_name, xa->xa_name) == 0);
    239 }
    240 
    241 /*
    242  * Attach an Sbus.
    243  */
    244 void
    245 sbus_attach_mainbus(struct device *parent, struct device *self, void *aux)
    246 {
    247 	struct sbus_softc *sc = (struct sbus_softc *)self;
    248 	struct mainbus_attach_args *ma = aux;
    249 	int node = ma->ma_node;
    250 
    251 	sbus_mainbus_attached = 1;
    252 
    253 	sc->sc_bustag = ma->ma_bustag;
    254 	sc->sc_dmatag = ma->ma_dmatag;
    255 
    256 #if 0	/* sbus at mainbus (sun4c): `reg' prop is not control space */
    257 	if (ma->ma_size == 0)
    258 		printf("%s: no Sbus registers", self->dv_xname);
    259 
    260 	if (bus_space_map(ma->ma_bustag,
    261 			  ma->ma_paddr,
    262 			  ma->ma_size,
    263 			  BUS_SPACE_MAP_LINEAR,
    264 			  &sc->sc_bh) != 0) {
    265 		panic("%s: can't map sbusbusreg", self->dv_xname);
    266 	}
    267 #endif
    268 
    269 	/* Setup interrupt translation tables */
    270 	sc->sc_intr2ipl = CPU_ISSUN4C
    271 				? intr_sbus2ipl_4c
    272 				: intr_sbus2ipl_4m;
    273 
    274 	/*
    275 	 * Record clock frequency for synchronous SCSI.
    276 	 * IS THIS THE CORRECT DEFAULT??
    277 	 */
    278 	sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000);
    279 	printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
    280 
    281 	sbus_sc = sc;
    282 	sbus_attach_common(sc, "sbus", node, NULL);
    283 }
    284 
    285 
    286 void
    287 sbus_attach_iommu(struct device *parent, struct device *self, void *aux)
    288 {
    289 	struct sbus_softc *sc = (struct sbus_softc *)self;
    290 	struct iommu_attach_args *ia = aux;
    291 	int node = ia->iom_node;
    292 
    293 	sc->sc_bustag = ia->iom_bustag;
    294 	sc->sc_dmatag = ia->iom_dmatag;
    295 
    296 	if (ia->iom_nreg == 0)
    297 		panic("%s: no Sbus registers", self->dv_xname);
    298 
    299 	if (bus_space_map(ia->iom_bustag,
    300 			  BUS_ADDR(ia->iom_reg[0].oa_space,
    301 				   ia->iom_reg[0].oa_base),
    302 			  (bus_size_t)ia->iom_reg[0].oa_size,
    303 			  BUS_SPACE_MAP_LINEAR,
    304 			  &sc->sc_bh) != 0) {
    305 		panic("%s: can't map sbusbusreg", self->dv_xname);
    306 	}
    307 
    308 	/* Setup interrupt translation tables */
    309 	sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m;
    310 
    311 	/*
    312 	 * Record clock frequency for synchronous SCSI.
    313 	 * IS THIS THE CORRECT DEFAULT??
    314 	 */
    315 	sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000);
    316 	printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
    317 
    318 	sbus_sc = sc;
    319 	sbuserr_handler = sbus_error;
    320 	sbus_attach_common(sc, "sbus", node, NULL);
    321 }
    322 
    323 void
    324 sbus_attach_xbox(struct device *parent, struct device *self, void *aux)
    325 {
    326 	struct sbus_softc *sc = (struct sbus_softc *)self;
    327 	struct xbox_attach_args *xa = aux;
    328 	int node = xa->xa_node;
    329 
    330 	sc->sc_bustag = xa->xa_bustag;
    331 	sc->sc_dmatag = xa->xa_dmatag;
    332 
    333 	/* Setup interrupt translation tables */
    334 	sc->sc_intr2ipl = CPU_ISSUN4C ? intr_sbus2ipl_4c : intr_sbus2ipl_4m;
    335 
    336 	/*
    337 	 * Record clock frequency for synchronous SCSI.
    338 	 * IS THIS THE CORRECT DEFAULT??
    339 	 */
    340 	sc->sc_clockfreq = prom_getpropint(node, "clock-frequency", 25*1000*1000);
    341 	printf(": clock = %s MHz\n", clockfreq(sc->sc_clockfreq));
    342 
    343 	sbus_attach_common(sc, "sbus", node, NULL);
    344 }
    345 
    346 void
    347 sbus_attach_common(struct sbus_softc *sc, const char *busname, int busnode,
    348 		   const char * const *specials)
    349 {
    350 	int node0, node, error;
    351 	const char *sp;
    352 	const char *const *ssp;
    353 	bus_space_tag_t sbt;
    354 	struct sbus_attach_args sa;
    355 
    356 	if ((sbt = bus_space_tag_alloc(sc->sc_bustag, sc)) == NULL) {
    357 		printf("%s: attach: out of memory\n", sc->sc_dev.dv_xname);
    358 		return;
    359 	}
    360 	sbt->sparc_intr_establish = sbus_intr_establish;
    361 
    362 	/*
    363 	 * Get the SBus burst transfer size if burst transfers are supported
    364 	 */
    365 	sc->sc_burst = prom_getpropint(busnode, "burst-sizes", 0);
    366 
    367 
    368 	if (CPU_ISSUN4M) {
    369 		/*
    370 		 * Some models (e.g. SS20) erroneously report 64-bit
    371 		 * burst capability. We mask it out here for all SUN4Ms,
    372 		 * since probably no member of that class supports
    373 		 * 64-bit Sbus bursts.
    374 		 */
    375 		sc->sc_burst &= ~SBUS_BURST_64;
    376 	}
    377 
    378 	/*
    379 	 * Collect address translations from the OBP.
    380 	 */
    381 	error = prom_getprop(busnode, "ranges", sizeof(struct rom_range),
    382 			&sbt->nranges, &sbt->ranges);
    383 	switch (error) {
    384 	case 0:
    385 		break;
    386 	case ENOENT:
    387 		/* Fall back to our own `range' construction */
    388 		sbt->ranges = sbus_translations;
    389 		sbt->nranges =
    390 			sizeof(sbus_translations)/sizeof(sbus_translations[0]);
    391 		break;
    392 	default:
    393 		panic("%s: error getting ranges property", sc->sc_dev.dv_xname);
    394 	}
    395 
    396 	/*
    397 	 * Loop through ROM children, fixing any relative addresses
    398 	 * and then configuring each device.
    399 	 * `specials' is an array of device names that are treated
    400 	 * specially:
    401 	 */
    402 	node0 = firstchild(busnode);
    403 	for (ssp = specials ; ssp != NULL && *(sp = *ssp) != 0; ssp++) {
    404 		if ((node = findnode(node0, sp)) == 0) {
    405 			panic("could not find %s amongst %s devices",
    406 				sp, busname);
    407 		}
    408 
    409 		if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag,
    410 					   node, &sa) != 0) {
    411 			panic("sbus_attach: %s: incomplete", sp);
    412 		}
    413 		(void) config_found(&sc->sc_dev, (void *)&sa, sbus_print);
    414 		sbus_destroy_attach_args(&sa);
    415 	}
    416 
    417 	for (node = node0; node; node = nextsibling(node)) {
    418 		char *name = prom_getpropstring(node, "name");
    419 		for (ssp = specials, sp = NULL;
    420 		     ssp != NULL && (sp = *ssp) != NULL;
    421 		     ssp++)
    422 			if (strcmp(name, sp) == 0)
    423 				break;
    424 
    425 		if (sp != NULL)
    426 			/* Already configured as an "early" device */
    427 			continue;
    428 
    429 		if (sbus_setup_attach_args(sc, sbt, sc->sc_dmatag,
    430 					   node, &sa) != 0) {
    431 			printf("sbus_attach: %s: incomplete\n", name);
    432 			continue;
    433 		}
    434 		(void) config_found(&sc->sc_dev, (void *)&sa, sbus_print);
    435 		sbus_destroy_attach_args(&sa);
    436 	}
    437 }
    438 
    439 int
    440 sbus_setup_attach_args(struct sbus_softc *sc,
    441 		       bus_space_tag_t bustag, bus_dma_tag_t dmatag, int node,
    442 		       struct sbus_attach_args *sa)
    443 {
    444 	int n, error;
    445 
    446 	bzero(sa, sizeof(struct sbus_attach_args));
    447 	error = prom_getprop(node, "name", 1, &n, &sa->sa_name);
    448 	if (error != 0)
    449 		return (error);
    450 	sa->sa_name[n] = '\0';
    451 
    452 	sa->sa_bustag = bustag;
    453 	sa->sa_dmatag = dmatag;
    454 	sa->sa_node = node;
    455 	sa->sa_frequency = sc->sc_clockfreq;
    456 
    457 	error = prom_getprop(node, "reg", sizeof(struct openprom_addr),
    458 			&sa->sa_nreg, &sa->sa_reg);
    459 	if (error != 0) {
    460 		char buf[32];
    461 		if (error != ENOENT ||
    462 		    !node_has_property(node, "device_type") ||
    463 		    strcmp(prom_getpropstringA(node, "device_type", buf, sizeof buf),
    464 			   "hierarchical") != 0)
    465 			return (error);
    466 	}
    467 	for (n = 0; n < sa->sa_nreg; n++) {
    468 		/* Convert to relative addressing, if necessary */
    469 		uint32_t base = sa->sa_reg[n].oa_base;
    470 		if (SBUS_ABS(base)) {
    471 			sa->sa_reg[n].oa_space = SBUS_ABS_TO_SLOT(base);
    472 			sa->sa_reg[n].oa_base = SBUS_ABS_TO_OFFSET(base);
    473 		}
    474 	}
    475 
    476 	if ((error = sbus_get_intr(sc, node, &sa->sa_intr, &sa->sa_nintr)) != 0)
    477 		return (error);
    478 
    479 	error = prom_getprop(node, "address", sizeof(uint32_t),
    480 			 &sa->sa_npromvaddrs, &sa->sa_promvaddrs);
    481 	if (error != 0 && error != ENOENT)
    482 		return (error);
    483 
    484 	return (0);
    485 }
    486 
    487 void
    488 sbus_destroy_attach_args(struct sbus_attach_args *sa)
    489 {
    490 
    491 	if (sa->sa_name != NULL)
    492 		free(sa->sa_name, M_DEVBUF);
    493 
    494 	if (sa->sa_nreg != 0)
    495 		free(sa->sa_reg, M_DEVBUF);
    496 
    497 	if (sa->sa_intr)
    498 		free(sa->sa_intr, M_DEVBUF);
    499 
    500 	if (sa->sa_promvaddrs)
    501 		free(sa->sa_promvaddrs, M_DEVBUF);
    502 
    503 	bzero(sa, sizeof(struct sbus_attach_args));/*DEBUG*/
    504 }
    505 
    506 bus_addr_t
    507 sbus_bus_addr(bus_space_tag_t t, u_int btype, u_int offset)
    508 {
    509 
    510 	/* XXX: sbus_bus_addr should be g/c'ed */
    511 	return (BUS_ADDR(btype, offset));
    512 }
    513 
    514 
    515 /*
    516  * Each attached device calls sbus_establish after it initializes
    517  * its sbusdev portion.
    518  */
    519 void
    520 sbus_establish(struct sbusdev *sd, struct device *dev)
    521 {
    522 	register struct sbus_softc *sc;
    523 	register struct device *curdev;
    524 
    525 	/*
    526 	 * We have to look for the sbus by name, since it is not necessarily
    527 	 * our immediate parent (i.e. sun4m /iommu/sbus/espdma/esp)
    528 	 * We don't just use the device structure of the above-attached
    529 	 * sbus, since we might (in the future) support multiple sbus's.
    530 	 */
    531 	for (curdev = device_parent(dev); ; curdev = device_parent(curdev)) {
    532 		if (!curdev || !curdev->dv_xname)
    533 			panic("sbus_establish: can't find sbus parent for %s",
    534 			      sd->sd_dev->dv_xname
    535 					? sd->sd_dev->dv_xname
    536 					: "<unknown>" );
    537 
    538 		if (strncmp(curdev->dv_xname, "sbus", 4) == 0)
    539 			break;
    540 	}
    541 	sc = (struct sbus_softc *) curdev;
    542 
    543 	sd->sd_dev = dev;
    544 	sd->sd_bchain = sc->sc_sbdev;
    545 	sc->sc_sbdev = sd;
    546 }
    547 
    548 /*
    549  * Reset the given sbus. (???)
    550  */
    551 void
    552 sbusreset(int sbus)
    553 {
    554 	register struct sbusdev *sd;
    555 	struct sbus_softc *sc = sbus_cd.cd_devs[sbus];
    556 	struct device *dev;
    557 
    558 	printf("reset %s:", sc->sc_dev.dv_xname);
    559 	for (sd = sc->sc_sbdev; sd != NULL; sd = sd->sd_bchain) {
    560 		if (sd->sd_reset) {
    561 			dev = sd->sd_dev;
    562 			(*sd->sd_reset)(dev);
    563 			printf(" %s", dev->dv_xname);
    564 		}
    565 	}
    566 }
    567 
    568 
    569 /*
    570  * Get interrupt attributes for an Sbus device.
    571  */
    572 static int
    573 sbus_get_intr(struct sbus_softc *sc, int node,
    574 	      struct openprom_intr **ipp, int *np)
    575 {
    576 	int error, n;
    577 	uint32_t *ipl = NULL;
    578 
    579 	/*
    580 	 * The `interrupts' property contains the Sbus interrupt level.
    581 	 */
    582 	if (prom_getprop(node, "interrupts", sizeof(int), np,
    583 			 &ipl) == 0) {
    584 		/* Change format to an `struct openprom_intr' array */
    585 		struct openprom_intr *ip;
    586 		ip = malloc(*np * sizeof(struct openprom_intr), M_DEVBUF,
    587 		    M_NOWAIT);
    588 		if (ip == NULL) {
    589 			free(ipl, M_DEVBUF);
    590 			return (ENOMEM);
    591 		}
    592 		for (n = 0; n < *np; n++) {
    593 			ip[n].oi_pri = ipl[n];
    594 			ip[n].oi_vec = 0;
    595 		}
    596 		free(ipl, M_DEVBUF);
    597 		*ipp = ip;
    598 		return (0);
    599 	}
    600 
    601 	/*
    602 	 * Fall back on `intr' property.
    603 	 */
    604 	*ipp = NULL;
    605 	error = prom_getprop(node, "intr", sizeof(struct openprom_intr),
    606 			np, ipp);
    607 	switch (error) {
    608 	case 0:
    609 		for (n = *np; n-- > 0;) {
    610 			(*ipp)[n].oi_pri &= 0xf;
    611 			(*ipp)[n].oi_pri |= SBUS_INTR_COMPAT;
    612 		}
    613 		break;
    614 	case ENOENT:
    615 		error = 0;
    616 		break;
    617 	}
    618 
    619 	return (error);
    620 }
    621 
    622 
    623 /*
    624  * Install an interrupt handler for an Sbus device.
    625  */
    626 static void *
    627 sbus_intr_establish(bus_space_tag_t t, int pri, int level,
    628 		    int (*handler)(void *), void *arg,
    629 		    void (*fastvec)(void))
    630 {
    631 	struct sbus_softc *sc = t->cookie;
    632 	struct intrhand *ih;
    633 	int pil;
    634 
    635 	ih = (struct intrhand *)
    636 		malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT);
    637 	if (ih == NULL)
    638 		return (NULL);
    639 
    640 	/*
    641 	 * Translate Sbus interrupt priority to CPU interrupt level
    642 	 */
    643 	if ((pri & SBUS_INTR_COMPAT) != 0)
    644 		pil = pri & ~SBUS_INTR_COMPAT;
    645 	else
    646 		pil = sc->sc_intr2ipl[pri];
    647 
    648 	ih->ih_fun = handler;
    649 	ih->ih_arg = arg;
    650 	intr_establish(pil, level, ih, fastvec);
    651 	return (ih);
    652 }
    653 
    654 static int
    655 sbus_error(void)
    656 {
    657 	struct sbus_softc *sc = sbus_sc;
    658 	bus_space_handle_t bh = sc->sc_bh;
    659 	uint32_t afsr, afva;
    660 	char bits[64];
    661 static	int straytime, nstray;
    662 	int timesince;
    663 
    664 	afsr = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFSR_REG);
    665 	afva = bus_space_read_4(sc->sc_bustag, bh, SBUS_AFAR_REG);
    666 	printf("sbus error:\n\tAFSR %s\n",
    667 		bitmask_snprintf(afsr, SBUS_AFSR_BITS, bits, sizeof(bits)));
    668 	printf("\taddress: 0x%x%x\n", afsr & SBUS_AFSR_PAH, afva);
    669 
    670 	/* For now, do the same dance as on stray interrupts */
    671 	timesince = time_uptime - straytime;
    672 	if (timesince <= 10) {
    673 		if (++nstray > 9)
    674 			panic("too many SBus errors");
    675 	} else {
    676 		straytime = time_uptime;
    677 		nstray = 1;
    678 	}
    679 
    680 	/* Unlock registers and clear interrupt */
    681 	bus_space_write_4(sc->sc_bustag, bh, SBUS_AFSR_REG, afsr);
    682 
    683 	return (0);
    684 }
    685