sw.c revision 1.3.2.2
1 1.3.2.2 pk /* $NetBSD: sw.c,v 1.3.2.2 2000/07/22 21:14:19 pk Exp $ */ 2 1.3.2.2 pk 3 1.3.2.2 pk /*- 4 1.3.2.2 pk * Copyright (c) 1996 The NetBSD Foundation, Inc. 5 1.3.2.2 pk * All rights reserved. 6 1.3.2.2 pk * 7 1.3.2.2 pk * This code is derived from software contributed to The NetBSD Foundation 8 1.3.2.2 pk * by Adam Glass, David Jones, Gordon W. Ross, and Jason R. Thorpe. 9 1.3.2.2 pk * 10 1.3.2.2 pk * Redistribution and use in source and binary forms, with or without 11 1.3.2.2 pk * modification, are permitted provided that the following conditions 12 1.3.2.2 pk * are met: 13 1.3.2.2 pk * 1. Redistributions of source code must retain the above copyright 14 1.3.2.2 pk * notice, this list of conditions and the following disclaimer. 15 1.3.2.2 pk * 2. Redistributions in binary form must reproduce the above copyright 16 1.3.2.2 pk * notice, this list of conditions and the following disclaimer in the 17 1.3.2.2 pk * documentation and/or other materials provided with the distribution. 18 1.3.2.2 pk * 3. All advertising materials mentioning features or use of this software 19 1.3.2.2 pk * must display the following acknowledgement: 20 1.3.2.2 pk * This product includes software developed by the NetBSD 21 1.3.2.2 pk * Foundation, Inc. and its contributors. 22 1.3.2.2 pk * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.3.2.2 pk * contributors may be used to endorse or promote products derived 24 1.3.2.2 pk * from this software without specific prior written permission. 25 1.3.2.2 pk * 26 1.3.2.2 pk * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.3.2.2 pk * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.3.2.2 pk * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.3.2.2 pk * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.3.2.2 pk * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.3.2.2 pk * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.3.2.2 pk * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.3.2.2 pk * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.3.2.2 pk * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.3.2.2 pk * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.3.2.2 pk * POSSIBILITY OF SUCH DAMAGE. 37 1.3.2.2 pk */ 38 1.3.2.2 pk 39 1.3.2.2 pk /* 40 1.3.2.2 pk * This file contains only the machine-dependent parts of the 41 1.3.2.2 pk * Sun4 SCSI driver. (Autoconfig stuff and DMA functions.) 42 1.3.2.2 pk * The machine-independent parts are in ncr5380sbc.c 43 1.3.2.2 pk * 44 1.3.2.2 pk * Supported hardware includes: 45 1.3.2.2 pk * Sun "SCSI Weird" on OBIO (sw: Sun 4/100-series) 46 1.3.2.2 pk * Sun SCSI-3 on VME (si: Sun 4/200-series, others) 47 1.3.2.2 pk * 48 1.3.2.2 pk * The VME variant has a bit to enable or disable the DMA engine, 49 1.3.2.2 pk * but that bit also gates the interrupt line from the NCR5380! 50 1.3.2.2 pk * Therefore, in order to get any interrupt from the 5380, (i.e. 51 1.3.2.2 pk * for reselect) one must clear the DMA engine transfer count and 52 1.3.2.2 pk * then enable DMA. This has the further complication that you 53 1.3.2.2 pk * CAN NOT touch the NCR5380 while the DMA enable bit is set, so 54 1.3.2.2 pk * we have to turn DMA back off before we even look at the 5380. 55 1.3.2.2 pk * 56 1.3.2.2 pk * What wonderfully whacky hardware this is! 57 1.3.2.2 pk * 58 1.3.2.2 pk * David Jones wrote the initial version of this module for NetBSD/sun3, 59 1.3.2.2 pk * which included support for the VME adapter only. (no reselection). 60 1.3.2.2 pk * 61 1.3.2.2 pk * Gordon Ross added support for the Sun 3 OBIO adapter, and re-worked 62 1.3.2.2 pk * both the VME and OBIO code to support disconnect/reselect. 63 1.3.2.2 pk * (Required figuring out the hardware "features" noted above.) 64 1.3.2.2 pk * 65 1.3.2.2 pk * The autoconfiguration boilerplate came from Adam Glass. 66 1.3.2.2 pk * 67 1.3.2.2 pk * Jason R. Thorpe ported the autoconfiguration and VME portions to 68 1.3.2.2 pk * NetBSD/sparc, and added initial support for the 4/100 "SCSI Weird", 69 1.3.2.2 pk * a wacky OBIO variant of the VME SCSI-3. Many thanks to Chuck Cranor 70 1.3.2.2 pk * for lots of helpful tips and suggestions. Thanks also to Paul Kranenburg 71 1.3.2.2 pk * and Chris Torek for bits of insight needed along the way. Thanks to 72 1.3.2.2 pk * David Gilbert and Andrew Gillham who risked filesystem life-and-limb 73 1.3.2.2 pk * for the sake of testing. Andrew Gillham helped work out the bugs 74 1.3.2.2 pk * the 4/100 DMA code. 75 1.3.2.2 pk */ 76 1.3.2.2 pk 77 1.3.2.2 pk /* 78 1.3.2.2 pk * NOTE: support for the 4/100 "SCSI Weird" is not complete! DMA 79 1.3.2.2 pk * works, but interrupts (and, thus, reselection) don't. I don't know 80 1.3.2.2 pk * why, and I don't have a machine to test this on further. 81 1.3.2.2 pk * 82 1.3.2.2 pk * DMA, DMA completion interrupts, and reselection work fine on my 83 1.3.2.2 pk * 4/260 with modern SCSI-II disks attached. I've had reports of 84 1.3.2.2 pk * reselection failing on Sun Shoebox-type configurations where 85 1.3.2.2 pk * there are multiple non-SCSI devices behind Emulex or Adaptec 86 1.3.2.2 pk * bridges. These devices pre-date the SCSI-I spec, and might not 87 1.3.2.2 pk * bahve the way the 5380 code expects. For this reason, only 88 1.3.2.2 pk * DMA is enabled by default in this driver. 89 1.3.2.2 pk * 90 1.3.2.2 pk * Jason R. Thorpe <thorpej (at) NetBSD.ORG> 91 1.3.2.2 pk * December 8, 1995 92 1.3.2.2 pk */ 93 1.3.2.2 pk 94 1.3.2.2 pk #include "opt_ddb.h" 95 1.3.2.2 pk 96 1.3.2.2 pk #include <sys/types.h> 97 1.3.2.2 pk #include <sys/param.h> 98 1.3.2.2 pk #include <sys/systm.h> 99 1.3.2.2 pk #include <sys/kernel.h> 100 1.3.2.2 pk #include <sys/malloc.h> 101 1.3.2.2 pk #include <sys/errno.h> 102 1.3.2.2 pk #include <sys/device.h> 103 1.3.2.2 pk #include <sys/buf.h> 104 1.3.2.2 pk 105 1.3.2.2 pk #include <machine/bus.h> 106 1.3.2.2 pk #include <machine/intr.h> 107 1.3.2.2 pk #include <machine/autoconf.h> 108 1.3.2.2 pk 109 1.3.2.2 pk #include <dev/scsipi/scsi_all.h> 110 1.3.2.2 pk #include <dev/scsipi/scsipi_all.h> 111 1.3.2.2 pk #include <dev/scsipi/scsipi_debug.h> 112 1.3.2.2 pk #include <dev/scsipi/scsiconf.h> 113 1.3.2.2 pk 114 1.3.2.2 pk #ifndef DDB 115 1.3.2.2 pk #define Debugger() 116 1.3.2.2 pk #endif 117 1.3.2.2 pk 118 1.3.2.2 pk #ifndef DEBUG 119 1.3.2.2 pk #define DEBUG XXX 120 1.3.2.2 pk #endif 121 1.3.2.2 pk 122 1.3.2.2 pk #define COUNT_SW_LEFTOVERS XXX /* See sw DMA completion code */ 123 1.3.2.2 pk 124 1.3.2.2 pk #include <dev/ic/ncr5380reg.h> 125 1.3.2.2 pk #include <dev/ic/ncr5380var.h> 126 1.3.2.2 pk 127 1.3.2.2 pk #include <sparc/dev/swreg.h> 128 1.3.2.2 pk 129 1.3.2.2 pk /* 130 1.3.2.2 pk * Transfers smaller than this are done using PIO 131 1.3.2.2 pk * (on assumption they're not worth DMA overhead) 132 1.3.2.2 pk */ 133 1.3.2.2 pk #define MIN_DMA_LEN 128 134 1.3.2.2 pk 135 1.3.2.2 pk /* 136 1.3.2.2 pk * Transfers lager than 65535 bytes need to be split-up. 137 1.3.2.2 pk * (Some of the FIFO logic has only 16 bits counters.) 138 1.3.2.2 pk * Make the size an integer multiple of the page size 139 1.3.2.2 pk * to avoid buf/cluster remap problems. (paranoid?) 140 1.3.2.2 pk */ 141 1.3.2.2 pk #define MAX_DMA_LEN 0xE000 142 1.3.2.2 pk 143 1.3.2.2 pk #ifdef DEBUG 144 1.3.2.2 pk int sw_debug = 0; 145 1.3.2.2 pk static int sw_link_flags = 0 /* | SDEV_DB2 */ ; 146 1.3.2.2 pk #endif 147 1.3.2.2 pk 148 1.3.2.2 pk /* 149 1.3.2.2 pk * This structure is used to keep track of mapped DMA requests. 150 1.3.2.2 pk */ 151 1.3.2.2 pk struct sw_dma_handle { 152 1.3.2.2 pk int dh_flags; 153 1.3.2.2 pk #define SIDH_BUSY 0x01 /* This DH is in use */ 154 1.3.2.2 pk #define SIDH_OUT 0x02 /* DMA does data out (write) */ 155 1.3.2.2 pk u_char *dh_addr; /* KVA of start of buffer */ 156 1.3.2.2 pk int dh_maplen; /* Original data length */ 157 1.3.2.2 pk long dh_startingpa; /* PA of buffer; for "sw" */ 158 1.3.2.2 pk bus_dmamap_t dh_dmamap; 159 1.3.2.2 pk #define dh_dvma dh_dmamap->dm_segs[0].ds_addr /* VA of buffer in DVMA space */ 160 1.3.2.2 pk }; 161 1.3.2.2 pk 162 1.3.2.2 pk /* 163 1.3.2.2 pk * The first structure member has to be the ncr5380_softc 164 1.3.2.2 pk * so we can just cast to go back and fourth between them. 165 1.3.2.2 pk */ 166 1.3.2.2 pk struct sw_softc { 167 1.3.2.2 pk struct ncr5380_softc ncr_sc; 168 1.3.2.2 pk bus_space_tag_t sc_bustag; /* bus tags */ 169 1.3.2.2 pk bus_dma_tag_t sc_dmatag; 170 1.3.2.2 pk 171 1.3.2.2 pk struct sw_dma_handle *sc_dma; 172 1.3.2.2 pk int sc_xlen; /* length of current DMA segment. */ 173 1.3.2.2 pk int sc_options; /* options for this instance. */ 174 1.3.2.2 pk }; 175 1.3.2.2 pk 176 1.3.2.2 pk /* 177 1.3.2.2 pk * Options. By default, DMA is enabled and DMA completion interrupts 178 1.3.2.2 pk * and reselect are disabled. You may enable additional features 179 1.3.2.2 pk * the `flags' directive in your kernel's configuration file. 180 1.3.2.2 pk * 181 1.3.2.2 pk * Alternatively, you can patch your kernel with DDB or some other 182 1.3.2.2 pk * mechanism. The sc_options member of the softc is OR'd with 183 1.3.2.2 pk * the value in sw_options. 184 1.3.2.2 pk * 185 1.3.2.2 pk * On the "sw", interrupts (and thus) reselection don't work, so they're 186 1.3.2.2 pk * disabled by default. DMA is still a little dangerous, too. 187 1.3.2.2 pk * 188 1.3.2.2 pk * Note, there's a separate sw_options to make life easier. 189 1.3.2.2 pk */ 190 1.3.2.2 pk #define SW_ENABLE_DMA 0x01 /* Use DMA (maybe polled) */ 191 1.3.2.2 pk #define SW_DMA_INTR 0x02 /* DMA completion interrupts */ 192 1.3.2.2 pk #define SW_DO_RESELECT 0x04 /* Allow disconnect/reselect */ 193 1.3.2.2 pk #define SW_OPTIONS_MASK (SW_ENABLE_DMA|SW_DMA_INTR|SW_DO_RESELECT) 194 1.3.2.2 pk #define SW_OPTIONS_BITS "\10\3RESELECT\2DMA_INTR\1DMA" 195 1.3.2.2 pk int sw_options = SW_ENABLE_DMA; 196 1.3.2.2 pk 197 1.3.2.2 pk static int sw_match __P((struct device *, struct cfdata *, void *)); 198 1.3.2.2 pk static void sw_attach __P((struct device *, struct device *, void *)); 199 1.3.2.2 pk static int sw_intr __P((void *)); 200 1.3.2.2 pk static void sw_reset_adapter __P((struct ncr5380_softc *)); 201 1.3.2.2 pk static void sw_minphys __P((struct buf *)); 202 1.3.2.2 pk 203 1.3.2.2 pk void sw_dma_alloc __P((struct ncr5380_softc *)); 204 1.3.2.2 pk void sw_dma_free __P((struct ncr5380_softc *)); 205 1.3.2.2 pk void sw_dma_poll __P((struct ncr5380_softc *)); 206 1.3.2.2 pk 207 1.3.2.2 pk void sw_dma_setup __P((struct ncr5380_softc *)); 208 1.3.2.2 pk void sw_dma_start __P((struct ncr5380_softc *)); 209 1.3.2.2 pk void sw_dma_eop __P((struct ncr5380_softc *)); 210 1.3.2.2 pk void sw_dma_stop __P((struct ncr5380_softc *)); 211 1.3.2.2 pk 212 1.3.2.2 pk void sw_intr_on __P((struct ncr5380_softc *)); 213 1.3.2.2 pk void sw_intr_off __P((struct ncr5380_softc *)); 214 1.3.2.2 pk 215 1.3.2.2 pk /* Shorthand bus space access */ 216 1.3.2.2 pk #define SWREG_READ(sc, index) \ 217 1.3.2.2 pk bus_space_read_4((sc)->sc_regt, (sc)->sc_regh, index) 218 1.3.2.2 pk #define SWREG_WRITE(sc, index, v) \ 219 1.3.2.2 pk bus_space_write_4((sc)->sc_regt, (sc)->sc_regh, index, v) 220 1.3.2.2 pk 221 1.3.2.2 pk 222 1.3.2.2 pk /* The Sun "SCSI Weird" 4/100 obio controller. */ 223 1.3.2.2 pk struct cfattach sw_ca = { 224 1.3.2.2 pk sizeof(struct sw_softc), sw_match, sw_attach 225 1.3.2.2 pk }; 226 1.3.2.2 pk 227 1.3.2.2 pk static int 228 1.3.2.2 pk sw_match(parent, cf, aux) 229 1.3.2.2 pk struct device *parent; 230 1.3.2.2 pk struct cfdata *cf; 231 1.3.2.2 pk void *aux; 232 1.3.2.2 pk { 233 1.3.2.2 pk union obio_attach_args *uoba = aux; 234 1.3.2.2 pk struct obio4_attach_args *oba; 235 1.3.2.2 pk 236 1.3.2.2 pk /* Nothing but a Sun 4/100 is going to have these devices. */ 237 1.3.2.2 pk if (cpuinfo.cpu_type != CPUTYP_4_100) 238 1.3.2.2 pk return (0); 239 1.3.2.2 pk 240 1.3.2.2 pk if (uoba->uoba_isobio4 == 0) 241 1.3.2.2 pk return (0); 242 1.3.2.2 pk 243 1.3.2.2 pk /* Make sure there is something there... */ 244 1.3.2.2 pk oba = &uoba->uoba_oba4; 245 1.3.2.2 pk return (bus_space_probe(oba->oba_bustag, 0, oba->oba_paddr, 246 1.3.2.2 pk 1, /* probe size */ 247 1.3.2.2 pk 1, /* offset */ 248 1.3.2.2 pk 0, /* flags */ 249 1.3.2.2 pk NULL, NULL)); 250 1.3.2.2 pk } 251 1.3.2.2 pk 252 1.3.2.2 pk static void 253 1.3.2.2 pk sw_attach(parent, self, aux) 254 1.3.2.2 pk struct device *parent, *self; 255 1.3.2.2 pk void *aux; 256 1.3.2.2 pk { 257 1.3.2.2 pk struct sw_softc *sc = (struct sw_softc *) self; 258 1.3.2.2 pk struct ncr5380_softc *ncr_sc = &sc->ncr_sc; 259 1.3.2.2 pk union obio_attach_args *uoba = aux; 260 1.3.2.2 pk struct obio4_attach_args *oba = &uoba->uoba_oba4; 261 1.3.2.2 pk bus_space_handle_t bh; 262 1.3.2.2 pk char bits[64]; 263 1.3.2.2 pk int i; 264 1.3.2.2 pk 265 1.3.2.2 pk sc->sc_dmatag = oba->oba_dmatag; 266 1.3.2.2 pk 267 1.3.2.2 pk /* Map the controller registers. */ 268 1.3.2.2 pk if (obio_bus_map(oba->oba_bustag, oba->oba_paddr, 269 1.3.2.2 pk 0, 270 1.3.2.2 pk SWREG_BANK_SZ, 271 1.3.2.2 pk BUS_SPACE_MAP_LINEAR, 272 1.3.2.2 pk 0, &bh) != 0) { 273 1.3.2.2 pk printf("%s: cannot map registers\n", self->dv_xname); 274 1.3.2.2 pk return; 275 1.3.2.2 pk } 276 1.3.2.2 pk 277 1.3.2.2 pk ncr_sc->sc_regt = oba->oba_bustag; 278 1.3.2.2 pk ncr_sc->sc_regh = bh; 279 1.3.2.2 pk 280 1.3.2.2 pk sc->sc_options = sw_options; 281 1.3.2.2 pk 282 1.3.2.2 pk ncr_sc->sc_dma_setup = sw_dma_setup; 283 1.3.2.2 pk ncr_sc->sc_dma_start = sw_dma_start; 284 1.3.2.2 pk ncr_sc->sc_dma_eop = sw_dma_stop; 285 1.3.2.2 pk ncr_sc->sc_dma_stop = sw_dma_stop; 286 1.3.2.2 pk ncr_sc->sc_intr_on = sw_intr_on; 287 1.3.2.2 pk ncr_sc->sc_intr_off = sw_intr_off; 288 1.3.2.2 pk 289 1.3.2.2 pk /* 290 1.3.2.2 pk * Establish interrupt channel. 291 1.3.2.2 pk * Default interrupt priority always is 3. At least, that's 292 1.3.2.2 pk * what my board seems to be at. --thorpej 293 1.3.2.2 pk */ 294 1.3.2.2 pk if (oba->oba_pri == -1) 295 1.3.2.2 pk oba->oba_pri = 3; 296 1.3.2.2 pk 297 1.3.2.2 pk (void)bus_intr_establish(oba->oba_bustag, oba->oba_pri, IPL_BIO, 0, 298 1.3.2.2 pk sw_intr, sc); 299 1.3.2.2 pk 300 1.3.2.2 pk printf(" pri %d\n", oba->oba_pri); 301 1.3.2.2 pk 302 1.3.2.2 pk 303 1.3.2.2 pk /* 304 1.3.2.2 pk * Pull in the options flags. Allow the user to completely 305 1.3.2.2 pk * override the default values. 306 1.3.2.2 pk */ 307 1.3.2.2 pk if ((ncr_sc->sc_dev.dv_cfdata->cf_flags & SW_OPTIONS_MASK) != 0) 308 1.3.2.2 pk sc->sc_options = 309 1.3.2.2 pk (ncr_sc->sc_dev.dv_cfdata->cf_flags & SW_OPTIONS_MASK); 310 1.3.2.2 pk 311 1.3.2.2 pk /* 312 1.3.2.2 pk * Initialize fields used by the MI code 313 1.3.2.2 pk */ 314 1.3.2.2 pk 315 1.3.2.2 pk /* NCR5380 register bank offsets */ 316 1.3.2.2 pk ncr_sc->sci_r0 = 0; 317 1.3.2.2 pk ncr_sc->sci_r1 = 1; 318 1.3.2.2 pk ncr_sc->sci_r2 = 2; 319 1.3.2.2 pk ncr_sc->sci_r3 = 3; 320 1.3.2.2 pk ncr_sc->sci_r4 = 4; 321 1.3.2.2 pk ncr_sc->sci_r5 = 5; 322 1.3.2.2 pk ncr_sc->sci_r6 = 6; 323 1.3.2.2 pk ncr_sc->sci_r7 = 7; 324 1.3.2.2 pk 325 1.3.2.2 pk ncr_sc->sc_rev = NCR_VARIANT_NCR5380; 326 1.3.2.2 pk 327 1.3.2.2 pk /* 328 1.3.2.2 pk * MD function pointers used by the MI code. 329 1.3.2.2 pk */ 330 1.3.2.2 pk ncr_sc->sc_pio_out = ncr5380_pio_out; 331 1.3.2.2 pk ncr_sc->sc_pio_in = ncr5380_pio_in; 332 1.3.2.2 pk ncr_sc->sc_dma_alloc = sw_dma_alloc; 333 1.3.2.2 pk ncr_sc->sc_dma_free = sw_dma_free; 334 1.3.2.2 pk ncr_sc->sc_dma_poll = sw_dma_poll; 335 1.3.2.2 pk 336 1.3.2.2 pk ncr_sc->sc_flags = 0; 337 1.3.2.2 pk if ((sc->sc_options & SW_DO_RESELECT) == 0) 338 1.3.2.2 pk ncr_sc->sc_no_disconnect = 0xFF; 339 1.3.2.2 pk if ((sc->sc_options & SW_DMA_INTR) == 0) 340 1.3.2.2 pk ncr_sc->sc_flags |= NCR5380_FORCE_POLLING; 341 1.3.2.2 pk ncr_sc->sc_min_dma_len = MIN_DMA_LEN; 342 1.3.2.2 pk 343 1.3.2.2 pk 344 1.3.2.2 pk /* 345 1.3.2.2 pk * Allocate DMA handles. 346 1.3.2.2 pk */ 347 1.3.2.2 pk i = SCI_OPENINGS * sizeof(struct sw_dma_handle); 348 1.3.2.2 pk sc->sc_dma = (struct sw_dma_handle *)malloc(i, M_DEVBUF, M_NOWAIT); 349 1.3.2.2 pk if (sc->sc_dma == NULL) 350 1.3.2.2 pk panic("sw: dma handle malloc failed\n"); 351 1.3.2.2 pk 352 1.3.2.2 pk for (i = 0; i < SCI_OPENINGS; i++) { 353 1.3.2.2 pk sc->sc_dma[i].dh_flags = 0; 354 1.3.2.2 pk 355 1.3.2.2 pk /* Allocate a DMA handle */ 356 1.3.2.2 pk if (bus_dmamap_create( 357 1.3.2.2 pk sc->sc_dmatag, /* tag */ 358 1.3.2.2 pk MAXPHYS, /* size */ 359 1.3.2.2 pk 1, /* nsegments */ 360 1.3.2.2 pk MAXPHYS, /* maxsegsz */ 361 1.3.2.2 pk 0, /* boundary */ 362 1.3.2.2 pk BUS_DMA_NOWAIT, 363 1.3.2.2 pk &sc->sc_dma[i].dh_dmamap) != 0) { 364 1.3.2.2 pk 365 1.3.2.2 pk printf("%s: DMA buffer map create error\n", 366 1.3.2.2 pk ncr_sc->sc_dev.dv_xname); 367 1.3.2.2 pk return; 368 1.3.2.2 pk } 369 1.3.2.2 pk } 370 1.3.2.2 pk 371 1.3.2.2 pk if (sc->sc_options) { 372 1.3.2.2 pk printf("%s: options=%s\n", ncr_sc->sc_dev.dv_xname, 373 1.3.2.2 pk bitmask_snprintf(sc->sc_options, SW_OPTIONS_BITS, 374 1.3.2.2 pk bits, sizeof(bits))); 375 1.3.2.2 pk } 376 1.3.2.2 pk #ifdef DEBUG 377 1.3.2.2 pk ncr_sc->sc_link.flags |= sw_link_flags; 378 1.3.2.2 pk #endif 379 1.3.2.2 pk 380 1.3.2.2 pk ncr_sc->sc_link.scsipi_scsi.adapter_target = 7; 381 1.3.2.2 pk ncr_sc->sc_adapter.scsipi_minphys = sw_minphys; 382 1.3.2.2 pk 383 1.3.2.2 pk /* Initialize sw board */ 384 1.3.2.2 pk sw_reset_adapter(ncr_sc); 385 1.3.2.2 pk 386 1.3.2.2 pk /* Attach the ncr5380 chip driver */ 387 1.3.2.2 pk ncr5380_attach(ncr_sc); 388 1.3.2.2 pk } 389 1.3.2.2 pk 390 1.3.2.2 pk static void 391 1.3.2.2 pk sw_minphys(struct buf *bp) 392 1.3.2.2 pk { 393 1.3.2.2 pk if (bp->b_bcount > MAX_DMA_LEN) { 394 1.3.2.2 pk #ifdef DEBUG 395 1.3.2.2 pk if (sw_debug) { 396 1.3.2.2 pk printf("sw_minphys len = 0x%x.\n", MAX_DMA_LEN); 397 1.3.2.2 pk Debugger(); 398 1.3.2.2 pk } 399 1.3.2.2 pk #endif 400 1.3.2.2 pk bp->b_bcount = MAX_DMA_LEN; 401 1.3.2.2 pk } 402 1.3.2.2 pk return (minphys(bp)); 403 1.3.2.2 pk } 404 1.3.2.2 pk 405 1.3.2.2 pk #define CSR_WANT (SW_CSR_SBC_IP | SW_CSR_DMA_IP | \ 406 1.3.2.2 pk SW_CSR_DMA_CONFLICT | SW_CSR_DMA_BUS_ERR ) 407 1.3.2.2 pk 408 1.3.2.2 pk static int 409 1.3.2.2 pk sw_intr(void *arg) 410 1.3.2.2 pk { 411 1.3.2.2 pk struct sw_softc *sc = arg; 412 1.3.2.2 pk struct ncr5380_softc *ncr_sc = (struct ncr5380_softc *)arg; 413 1.3.2.2 pk int dma_error, claimed; 414 1.3.2.2 pk u_short csr; 415 1.3.2.2 pk 416 1.3.2.2 pk claimed = 0; 417 1.3.2.2 pk dma_error = 0; 418 1.3.2.2 pk 419 1.3.2.2 pk /* SBC interrupt? DMA interrupt? */ 420 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 421 1.3.2.2 pk 422 1.3.2.2 pk NCR_TRACE("sw_intr: csr=0x%x\n", csr); 423 1.3.2.2 pk 424 1.3.2.2 pk if (csr & SW_CSR_DMA_CONFLICT) { 425 1.3.2.2 pk dma_error |= SW_CSR_DMA_CONFLICT; 426 1.3.2.2 pk printf("sw_intr: DMA conflict\n"); 427 1.3.2.2 pk } 428 1.3.2.2 pk if (csr & SW_CSR_DMA_BUS_ERR) { 429 1.3.2.2 pk dma_error |= SW_CSR_DMA_BUS_ERR; 430 1.3.2.2 pk printf("sw_intr: DMA bus error\n"); 431 1.3.2.2 pk } 432 1.3.2.2 pk if (dma_error) { 433 1.3.2.2 pk if (sc->ncr_sc.sc_state & NCR_DOINGDMA) 434 1.3.2.2 pk sc->ncr_sc.sc_state |= NCR_ABORTING; 435 1.3.2.2 pk /* Make sure we will call the main isr. */ 436 1.3.2.2 pk csr |= SW_CSR_DMA_IP; 437 1.3.2.2 pk } 438 1.3.2.2 pk 439 1.3.2.2 pk if (csr & (SW_CSR_SBC_IP | SW_CSR_DMA_IP)) { 440 1.3.2.2 pk claimed = ncr5380_intr(&sc->ncr_sc); 441 1.3.2.2 pk #ifdef DEBUG 442 1.3.2.2 pk if (!claimed) { 443 1.3.2.2 pk printf("sw_intr: spurious from SBC\n"); 444 1.3.2.2 pk if (sw_debug & 4) { 445 1.3.2.2 pk Debugger(); /* XXX */ 446 1.3.2.2 pk } 447 1.3.2.2 pk } 448 1.3.2.2 pk #endif 449 1.3.2.2 pk } 450 1.3.2.2 pk 451 1.3.2.2 pk return (claimed); 452 1.3.2.2 pk } 453 1.3.2.2 pk 454 1.3.2.2 pk 455 1.3.2.2 pk static void 456 1.3.2.2 pk sw_reset_adapter(struct ncr5380_softc *ncr_sc) 457 1.3.2.2 pk { 458 1.3.2.2 pk 459 1.3.2.2 pk #ifdef DEBUG 460 1.3.2.2 pk if (sw_debug) { 461 1.3.2.2 pk printf("sw_reset_adapter\n"); 462 1.3.2.2 pk } 463 1.3.2.2 pk #endif 464 1.3.2.2 pk 465 1.3.2.2 pk /* 466 1.3.2.2 pk * The reset bits in the CSR are active low. 467 1.3.2.2 pk */ 468 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, 0); 469 1.3.2.2 pk delay(10); 470 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, SW_CSR_SCSI_RES); 471 1.3.2.2 pk 472 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, 0); 473 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, 0); 474 1.3.2.2 pk delay(10); 475 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, SW_CSR_SCSI_RES | SW_CSR_INTR_EN); 476 1.3.2.2 pk 477 1.3.2.2 pk SCI_CLR_INTR(ncr_sc); 478 1.3.2.2 pk } 479 1.3.2.2 pk 480 1.3.2.2 pk 481 1.3.2.2 pk /***************************************************************** 482 1.3.2.2 pk * Common functions for DMA 483 1.3.2.2 pk ****************************************************************/ 484 1.3.2.2 pk 485 1.3.2.2 pk /* 486 1.3.2.2 pk * Allocate a DMA handle and put it in sc->sc_dma. Prepare 487 1.3.2.2 pk * for DMA transfer. On the Sun4, this means mapping the buffer 488 1.3.2.2 pk * into DVMA space. 489 1.3.2.2 pk */ 490 1.3.2.2 pk void 491 1.3.2.2 pk sw_dma_alloc(ncr_sc) 492 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 493 1.3.2.2 pk { 494 1.3.2.2 pk struct sw_softc *sc = (struct sw_softc *)ncr_sc; 495 1.3.2.2 pk struct sci_req *sr = ncr_sc->sc_current; 496 1.3.2.2 pk struct scsipi_xfer *xs = sr->sr_xs; 497 1.3.2.2 pk struct sw_dma_handle *dh; 498 1.3.2.2 pk int i, xlen; 499 1.3.2.2 pk u_long addr; 500 1.3.2.2 pk 501 1.3.2.2 pk #ifdef DIAGNOSTIC 502 1.3.2.2 pk if (sr->sr_dma_hand != NULL) 503 1.3.2.2 pk panic("sw_dma_alloc: already have DMA handle"); 504 1.3.2.2 pk #endif 505 1.3.2.2 pk 506 1.3.2.2 pk #if 1 /* XXX - Temporary */ 507 1.3.2.2 pk /* XXX - In case we think DMA is completely broken... */ 508 1.3.2.2 pk if ((sc->sc_options & SW_ENABLE_DMA) == 0) 509 1.3.2.2 pk return; 510 1.3.2.2 pk #endif 511 1.3.2.2 pk 512 1.3.2.2 pk addr = (u_long) ncr_sc->sc_dataptr; 513 1.3.2.2 pk xlen = ncr_sc->sc_datalen; 514 1.3.2.2 pk 515 1.3.2.2 pk /* If the DMA start addr is misaligned then do PIO */ 516 1.3.2.2 pk if ((addr & 1) || (xlen & 1)) { 517 1.3.2.2 pk printf("sw_dma_alloc: misaligned.\n"); 518 1.3.2.2 pk return; 519 1.3.2.2 pk } 520 1.3.2.2 pk 521 1.3.2.2 pk /* Make sure our caller checked sc_min_dma_len. */ 522 1.3.2.2 pk if (xlen < MIN_DMA_LEN) 523 1.3.2.2 pk panic("sw_dma_alloc: xlen=0x%x\n", xlen); 524 1.3.2.2 pk 525 1.3.2.2 pk /* Find free DMA handle. Guaranteed to find one since we have 526 1.3.2.2 pk as many DMA handles as the driver has processes. */ 527 1.3.2.2 pk for (i = 0; i < SCI_OPENINGS; i++) { 528 1.3.2.2 pk if ((sc->sc_dma[i].dh_flags & SIDH_BUSY) == 0) 529 1.3.2.2 pk goto found; 530 1.3.2.2 pk } 531 1.3.2.2 pk panic("sw: no free DMA handles."); 532 1.3.2.2 pk 533 1.3.2.2 pk found: 534 1.3.2.2 pk dh = &sc->sc_dma[i]; 535 1.3.2.2 pk dh->dh_flags = SIDH_BUSY; 536 1.3.2.2 pk dh->dh_addr = (u_char *)addr; 537 1.3.2.2 pk dh->dh_maplen = xlen; 538 1.3.2.2 pk 539 1.3.2.2 pk /* Copy the "write" flag for convenience. */ 540 1.3.2.2 pk if ((xs->xs_control & XS_CTL_DATA_OUT) != 0) 541 1.3.2.2 pk dh->dh_flags |= SIDH_OUT; 542 1.3.2.2 pk 543 1.3.2.2 pk /* 544 1.3.2.2 pk * Double-map the buffer into DVMA space. If we can't re-map 545 1.3.2.2 pk * the buffer, we print a warning and fall back to PIO mode. 546 1.3.2.2 pk * 547 1.3.2.2 pk * NOTE: it is not safe to sleep here! 548 1.3.2.2 pk */ 549 1.3.2.2 pk if (bus_dmamap_load(sc->sc_dmatag, dh->dh_dmamap, 550 1.3.2.2 pk (caddr_t)addr, xlen, NULL, BUS_DMA_NOWAIT) != 0) { 551 1.3.2.2 pk /* Can't remap segment */ 552 1.3.2.2 pk printf("sw_dma_alloc: can't remap 0x%lx/0x%x, doing PIO\n", 553 1.3.2.2 pk addr, dh->dh_maplen); 554 1.3.2.2 pk dh->dh_flags = 0; 555 1.3.2.2 pk return; 556 1.3.2.2 pk } 557 1.3.2.2 pk bus_dmamap_sync(sc->sc_dmatag, dh->dh_dmamap, addr, xlen, 558 1.3.2.2 pk (dh->dh_flags & SIDH_OUT) 559 1.3.2.2 pk ? BUS_DMASYNC_PREWRITE 560 1.3.2.2 pk : BUS_DMASYNC_PREREAD); 561 1.3.2.2 pk 562 1.3.2.2 pk /* success */ 563 1.3.2.2 pk sr->sr_dma_hand = dh; 564 1.3.2.2 pk 565 1.3.2.2 pk return; 566 1.3.2.2 pk } 567 1.3.2.2 pk 568 1.3.2.2 pk 569 1.3.2.2 pk void 570 1.3.2.2 pk sw_dma_free(ncr_sc) 571 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 572 1.3.2.2 pk { 573 1.3.2.2 pk struct sw_softc *sc = (struct sw_softc *)ncr_sc; 574 1.3.2.2 pk struct sci_req *sr = ncr_sc->sc_current; 575 1.3.2.2 pk struct sw_dma_handle *dh = sr->sr_dma_hand; 576 1.3.2.2 pk 577 1.3.2.2 pk #ifdef DIAGNOSTIC 578 1.3.2.2 pk if (dh == NULL) 579 1.3.2.2 pk panic("sw_dma_free: no DMA handle"); 580 1.3.2.2 pk #endif 581 1.3.2.2 pk 582 1.3.2.2 pk if (ncr_sc->sc_state & NCR_DOINGDMA) 583 1.3.2.2 pk panic("sw_dma_free: free while in progress"); 584 1.3.2.2 pk 585 1.3.2.2 pk if (dh->dh_flags & SIDH_BUSY) { 586 1.3.2.2 pk /* Give back the DVMA space. */ 587 1.3.2.2 pk bus_dmamap_sync(sc->sc_dmatag, dh->dh_dmamap, 588 1.3.2.2 pk dh->dh_dvma, dh->dh_maplen, 589 1.3.2.2 pk (dh->dh_flags & SIDH_OUT) 590 1.3.2.2 pk ? BUS_DMASYNC_POSTWRITE 591 1.3.2.2 pk : BUS_DMASYNC_POSTREAD); 592 1.3.2.2 pk bus_dmamap_unload(sc->sc_dmatag, dh->dh_dmamap); 593 1.3.2.2 pk dh->dh_flags = 0; 594 1.3.2.2 pk } 595 1.3.2.2 pk sr->sr_dma_hand = NULL; 596 1.3.2.2 pk } 597 1.3.2.2 pk 598 1.3.2.2 pk 599 1.3.2.2 pk /* 600 1.3.2.2 pk * Poll (spin-wait) for DMA completion. 601 1.3.2.2 pk * Called right after xx_dma_start(), and 602 1.3.2.2 pk * xx_dma_stop() will be called next. 603 1.3.2.2 pk * Same for either VME or OBIO. 604 1.3.2.2 pk */ 605 1.3.2.2 pk void 606 1.3.2.2 pk sw_dma_poll(ncr_sc) 607 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 608 1.3.2.2 pk { 609 1.3.2.2 pk struct sci_req *sr = ncr_sc->sc_current; 610 1.3.2.2 pk int tmo, csr_mask, csr; 611 1.3.2.2 pk 612 1.3.2.2 pk /* Make sure DMA started successfully. */ 613 1.3.2.2 pk if (ncr_sc->sc_state & NCR_ABORTING) 614 1.3.2.2 pk return; 615 1.3.2.2 pk 616 1.3.2.2 pk csr_mask = SW_CSR_SBC_IP | SW_CSR_DMA_IP | 617 1.3.2.2 pk SW_CSR_DMA_CONFLICT | SW_CSR_DMA_BUS_ERR; 618 1.3.2.2 pk 619 1.3.2.2 pk tmo = 50000; /* X100 = 5 sec. */ 620 1.3.2.2 pk for (;;) { 621 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 622 1.3.2.2 pk if (csr & csr_mask) 623 1.3.2.2 pk break; 624 1.3.2.2 pk if (--tmo <= 0) { 625 1.3.2.2 pk printf("%s: DMA timeout (while polling)\n", 626 1.3.2.2 pk ncr_sc->sc_dev.dv_xname); 627 1.3.2.2 pk /* Indicate timeout as MI code would. */ 628 1.3.2.2 pk sr->sr_flags |= SR_OVERDUE; 629 1.3.2.2 pk break; 630 1.3.2.2 pk } 631 1.3.2.2 pk delay(100); 632 1.3.2.2 pk } 633 1.3.2.2 pk 634 1.3.2.2 pk #ifdef DEBUG 635 1.3.2.2 pk if (sw_debug) { 636 1.3.2.2 pk printf("sw_dma_poll: done, csr=0x%x\n", csr); 637 1.3.2.2 pk } 638 1.3.2.2 pk #endif 639 1.3.2.2 pk } 640 1.3.2.2 pk 641 1.3.2.2 pk 642 1.3.2.2 pk /* 643 1.3.2.2 pk * This is called when the bus is going idle, 644 1.3.2.2 pk * so we want to enable the SBC interrupts. 645 1.3.2.2 pk * That is controlled by the DMA enable! 646 1.3.2.2 pk * Who would have guessed! 647 1.3.2.2 pk * What a NASTY trick! 648 1.3.2.2 pk * 649 1.3.2.2 pk * XXX THIS MIGHT NOT WORK RIGHT! 650 1.3.2.2 pk */ 651 1.3.2.2 pk void 652 1.3.2.2 pk sw_intr_on(ncr_sc) 653 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 654 1.3.2.2 pk { 655 1.3.2.2 pk u_int32_t csr; 656 1.3.2.2 pk 657 1.3.2.2 pk sw_dma_setup(ncr_sc); 658 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 659 1.3.2.2 pk csr |= SW_CSR_DMA_EN; /* XXX - this bit is for vme only?! */ 660 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, csr); 661 1.3.2.2 pk } 662 1.3.2.2 pk 663 1.3.2.2 pk /* 664 1.3.2.2 pk * This is called when the bus is idle and we are 665 1.3.2.2 pk * about to start playing with the SBC chip. 666 1.3.2.2 pk * 667 1.3.2.2 pk * XXX THIS MIGHT NOT WORK RIGHT! 668 1.3.2.2 pk */ 669 1.3.2.2 pk void 670 1.3.2.2 pk sw_intr_off(ncr_sc) 671 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 672 1.3.2.2 pk { 673 1.3.2.2 pk u_int32_t csr; 674 1.3.2.2 pk 675 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 676 1.3.2.2 pk csr &= ~SW_CSR_DMA_EN; 677 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, csr); 678 1.3.2.2 pk } 679 1.3.2.2 pk 680 1.3.2.2 pk 681 1.3.2.2 pk /* 682 1.3.2.2 pk * This function is called during the COMMAND or MSG_IN phase 683 1.3.2.2 pk * that preceeds a DATA_IN or DATA_OUT phase, in case we need 684 1.3.2.2 pk * to setup the DMA engine before the bus enters a DATA phase. 685 1.3.2.2 pk * 686 1.3.2.2 pk * On the OBIO version we just clear the DMA count and address 687 1.3.2.2 pk * here (to make sure it stays idle) and do the real setup 688 1.3.2.2 pk * later, in dma_start. 689 1.3.2.2 pk */ 690 1.3.2.2 pk void 691 1.3.2.2 pk sw_dma_setup(ncr_sc) 692 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 693 1.3.2.2 pk { 694 1.3.2.2 pk u_int32_t csr; 695 1.3.2.2 pk 696 1.3.2.2 pk /* No FIFO to reset on "sw". */ 697 1.3.2.2 pk 698 1.3.2.2 pk /* Set direction (assume recv here) */ 699 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 700 1.3.2.2 pk csr &= ~SW_CSR_SEND; 701 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, csr); 702 1.3.2.2 pk 703 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, 0); 704 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, 0); 705 1.3.2.2 pk } 706 1.3.2.2 pk 707 1.3.2.2 pk 708 1.3.2.2 pk void 709 1.3.2.2 pk sw_dma_start(ncr_sc) 710 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 711 1.3.2.2 pk { 712 1.3.2.2 pk struct sw_softc *sc = (struct sw_softc *)ncr_sc; 713 1.3.2.2 pk struct sci_req *sr = ncr_sc->sc_current; 714 1.3.2.2 pk struct sw_dma_handle *dh = sr->sr_dma_hand; 715 1.3.2.2 pk u_long dva; 716 1.3.2.2 pk int xlen, adj, adjlen; 717 1.3.2.2 pk u_int mode; 718 1.3.2.2 pk u_int32_t csr; 719 1.3.2.2 pk 720 1.3.2.2 pk /* 721 1.3.2.2 pk * Get the DVMA mapping for this segment. 722 1.3.2.2 pk */ 723 1.3.2.2 pk dva = (u_long)(dh->dh_dvma); 724 1.3.2.2 pk if (dva & 1) 725 1.3.2.2 pk panic("sw_dma_start: bad dva=0x%lx", dva); 726 1.3.2.2 pk 727 1.3.2.2 pk xlen = ncr_sc->sc_datalen; 728 1.3.2.2 pk xlen &= ~1; 729 1.3.2.2 pk sc->sc_xlen = xlen; /* XXX: or less... */ 730 1.3.2.2 pk 731 1.3.2.2 pk #ifdef DEBUG 732 1.3.2.2 pk if (sw_debug & 2) { 733 1.3.2.2 pk printf("sw_dma_start: dh=%p, dva=0x%lx, xlen=%d\n", 734 1.3.2.2 pk dh, dva, xlen); 735 1.3.2.2 pk } 736 1.3.2.2 pk #endif 737 1.3.2.2 pk 738 1.3.2.2 pk /* 739 1.3.2.2 pk * Set up the DMA controller. 740 1.3.2.2 pk * Note that (dh->dh_len < sc_datalen) 741 1.3.2.2 pk */ 742 1.3.2.2 pk 743 1.3.2.2 pk /* Set direction (send/recv) */ 744 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 745 1.3.2.2 pk if (dh->dh_flags & SIDH_OUT) { 746 1.3.2.2 pk csr |= SW_CSR_SEND; 747 1.3.2.2 pk } else { 748 1.3.2.2 pk csr &= ~SW_CSR_SEND; 749 1.3.2.2 pk } 750 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, csr); 751 1.3.2.2 pk 752 1.3.2.2 pk /* 753 1.3.2.2 pk * The "sw" needs longword aligned transfers. We 754 1.3.2.2 pk * detect a shortword aligned transfer here, and adjust the 755 1.3.2.2 pk * DMA transfer by 2 bytes. These two bytes are read/written 756 1.3.2.2 pk * in PIO mode just before the DMA is started. 757 1.3.2.2 pk */ 758 1.3.2.2 pk adj = 0; 759 1.3.2.2 pk if (dva & 2) { 760 1.3.2.2 pk adj = 2; 761 1.3.2.2 pk #ifdef DEBUG 762 1.3.2.2 pk if (sw_debug & 2) 763 1.3.2.2 pk printf("sw_dma_start: adjusted up %d bytes\n", adj); 764 1.3.2.2 pk #endif 765 1.3.2.2 pk } 766 1.3.2.2 pk 767 1.3.2.2 pk /* We have to frob the address on the "sw". */ 768 1.3.2.2 pk dh->dh_startingpa = (dva | 0xF00000); 769 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, (u_int)(dh->dh_startingpa + adj)); 770 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, xlen - adj); 771 1.3.2.2 pk 772 1.3.2.2 pk /* 773 1.3.2.2 pk * Acknowledge the phase change. (After DMA setup!) 774 1.3.2.2 pk * Put the SBIC into DMA mode, and start the transfer. 775 1.3.2.2 pk */ 776 1.3.2.2 pk if (dh->dh_flags & SIDH_OUT) { 777 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_OUT); 778 1.3.2.2 pk if (adj) { 779 1.3.2.2 pk adjlen = ncr5380_pio_out(ncr_sc, PHASE_DATA_OUT, 780 1.3.2.2 pk adj, dh->dh_addr); 781 1.3.2.2 pk if (adjlen != adj) 782 1.3.2.2 pk printf("%s: bad outgoing adj, %d != %d\n", 783 1.3.2.2 pk ncr_sc->sc_dev.dv_xname, adjlen, adj); 784 1.3.2.2 pk } 785 1.3.2.2 pk SCI_CLR_INTR(ncr_sc); 786 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_icmd, SCI_ICMD_DATA); 787 1.3.2.2 pk mode = NCR5380_READ(ncr_sc, sci_mode); 788 1.3.2.2 pk mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 789 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_mode, mode); 790 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_dma_send, 0); /* start it */ 791 1.3.2.2 pk } else { 792 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_tcmd, PHASE_DATA_IN); 793 1.3.2.2 pk if (adj) { 794 1.3.2.2 pk adjlen = ncr5380_pio_in(ncr_sc, PHASE_DATA_IN, 795 1.3.2.2 pk adj, dh->dh_addr); 796 1.3.2.2 pk if (adjlen != adj) 797 1.3.2.2 pk printf("%s: bad incoming adj, %d != %d\n", 798 1.3.2.2 pk ncr_sc->sc_dev.dv_xname, adjlen, adj); 799 1.3.2.2 pk } 800 1.3.2.2 pk SCI_CLR_INTR(ncr_sc); 801 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_icmd, 0); 802 1.3.2.2 pk mode = NCR5380_READ(ncr_sc, sci_mode); 803 1.3.2.2 pk mode |= (SCI_MODE_DMA | SCI_MODE_DMA_IE); 804 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_mode, mode); 805 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_irecv, 0); /* start it */ 806 1.3.2.2 pk } 807 1.3.2.2 pk 808 1.3.2.2 pk /* Let'er rip! */ 809 1.3.2.2 pk csr |= SW_CSR_DMA_EN; 810 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, csr); 811 1.3.2.2 pk 812 1.3.2.2 pk ncr_sc->sc_state |= NCR_DOINGDMA; 813 1.3.2.2 pk 814 1.3.2.2 pk #ifdef DEBUG 815 1.3.2.2 pk if (sw_debug & 2) { 816 1.3.2.2 pk printf("sw_dma_start: started, flags=0x%x\n", 817 1.3.2.2 pk ncr_sc->sc_state); 818 1.3.2.2 pk } 819 1.3.2.2 pk #endif 820 1.3.2.2 pk } 821 1.3.2.2 pk 822 1.3.2.2 pk 823 1.3.2.2 pk void 824 1.3.2.2 pk sw_dma_eop(ncr_sc) 825 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 826 1.3.2.2 pk { 827 1.3.2.2 pk 828 1.3.2.2 pk /* Not needed - DMA was stopped prior to examining sci_csr */ 829 1.3.2.2 pk } 830 1.3.2.2 pk 831 1.3.2.2 pk #if (defined(DEBUG) || defined(DIAGNOSTIC)) && !defined(COUNT_SW_LEFTOVERS) 832 1.3.2.2 pk #define COUNT_SW_LEFTOVERS 833 1.3.2.2 pk #endif 834 1.3.2.2 pk #ifdef COUNT_SW_LEFTOVERS 835 1.3.2.2 pk /* 836 1.3.2.2 pk * Let's find out how often these occur. Read these with DDB from time 837 1.3.2.2 pk * to time. 838 1.3.2.2 pk */ 839 1.3.2.2 pk int sw_3_leftover = 0; 840 1.3.2.2 pk int sw_2_leftover = 0; 841 1.3.2.2 pk int sw_1_leftover = 0; 842 1.3.2.2 pk int sw_0_leftover = 0; 843 1.3.2.2 pk #endif 844 1.3.2.2 pk 845 1.3.2.2 pk void 846 1.3.2.2 pk sw_dma_stop(ncr_sc) 847 1.3.2.2 pk struct ncr5380_softc *ncr_sc; 848 1.3.2.2 pk { 849 1.3.2.2 pk struct sci_req *sr = ncr_sc->sc_current; 850 1.3.2.2 pk struct sw_dma_handle *dh = sr->sr_dma_hand; 851 1.3.2.2 pk int ntrans = 0, dva; 852 1.3.2.2 pk u_int mode; 853 1.3.2.2 pk u_int32_t csr; 854 1.3.2.2 pk 855 1.3.2.2 pk if ((ncr_sc->sc_state & NCR_DOINGDMA) == 0) { 856 1.3.2.2 pk #ifdef DEBUG 857 1.3.2.2 pk printf("sw_dma_stop: dma not running\n"); 858 1.3.2.2 pk #endif 859 1.3.2.2 pk return; 860 1.3.2.2 pk } 861 1.3.2.2 pk ncr_sc->sc_state &= ~NCR_DOINGDMA; 862 1.3.2.2 pk 863 1.3.2.2 pk /* First, halt the DMA engine. */ 864 1.3.2.2 pk csr = SWREG_READ(ncr_sc, SWREG_CSR); 865 1.3.2.2 pk csr &= ~SW_CSR_DMA_EN; 866 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_CSR, csr); 867 1.3.2.2 pk 868 1.3.2.2 pk /* 869 1.3.2.2 pk * XXX HARDWARE BUG! 870 1.3.2.2 pk * Apparently, some early 4/100 SCSI controllers had a hardware 871 1.3.2.2 pk * bug that caused the controller to do illegal memory access. 872 1.3.2.2 pk * We see this as SW_CSR_DMA_BUS_ERR (makes sense). To work around 873 1.3.2.2 pk * this, we simply need to clean up after ourselves ... there will 874 1.3.2.2 pk * be as many as 3 bytes left over. Since we clean up "left-over" 875 1.3.2.2 pk * bytes on every read anyway, we just continue to chug along 876 1.3.2.2 pk * if SW_CSR_DMA_BUS_ERR is asserted. (This was probably worked 877 1.3.2.2 pk * around in hardware later with the "left-over byte" indicator 878 1.3.2.2 pk * in the VME controller.) 879 1.3.2.2 pk */ 880 1.3.2.2 pk #if 0 881 1.3.2.2 pk if (csr & (SW_CSR_DMA_CONFLICT | SW_CSR_DMA_BUS_ERR)) { 882 1.3.2.2 pk #else 883 1.3.2.2 pk if (csr & (SW_CSR_DMA_CONFLICT)) { 884 1.3.2.2 pk #endif 885 1.3.2.2 pk printf("sw: DMA error, csr=0x%x, reset\n", csr); 886 1.3.2.2 pk sr->sr_xs->error = XS_DRIVER_STUFFUP; 887 1.3.2.2 pk ncr_sc->sc_state |= NCR_ABORTING; 888 1.3.2.2 pk sw_reset_adapter(ncr_sc); 889 1.3.2.2 pk } 890 1.3.2.2 pk 891 1.3.2.2 pk /* Note that timeout may have set the error flag. */ 892 1.3.2.2 pk if (ncr_sc->sc_state & NCR_ABORTING) 893 1.3.2.2 pk goto out; 894 1.3.2.2 pk 895 1.3.2.2 pk /* 896 1.3.2.2 pk * Now try to figure out how much actually transferred 897 1.3.2.2 pk * 898 1.3.2.2 pk * The "sw" doesn't have a FIFO or a bcr, so we've stored 899 1.3.2.2 pk * the starting PA of the transfer in the DMA handle, 900 1.3.2.2 pk * and subtract it from the ending PA left in the dma_addr 901 1.3.2.2 pk * register. 902 1.3.2.2 pk */ 903 1.3.2.2 pk dva = SWREG_READ(ncr_sc, SWREG_DMA_ADDR); 904 1.3.2.2 pk ntrans = (dva - dh->dh_startingpa); 905 1.3.2.2 pk 906 1.3.2.2 pk #ifdef DEBUG 907 1.3.2.2 pk if (sw_debug & 2) { 908 1.3.2.2 pk printf("sw_dma_stop: ntrans=0x%x\n", ntrans); 909 1.3.2.2 pk } 910 1.3.2.2 pk #endif 911 1.3.2.2 pk 912 1.3.2.2 pk if (ntrans > ncr_sc->sc_datalen) 913 1.3.2.2 pk panic("sw_dma_stop: excess transfer"); 914 1.3.2.2 pk 915 1.3.2.2 pk /* Adjust data pointer */ 916 1.3.2.2 pk ncr_sc->sc_dataptr += ntrans; 917 1.3.2.2 pk ncr_sc->sc_datalen -= ntrans; 918 1.3.2.2 pk 919 1.3.2.2 pk /* 920 1.3.2.2 pk * After a read, we may need to clean-up 921 1.3.2.2 pk * "Left-over bytes" (yuck!) The "sw" doesn't 922 1.3.2.2 pk * have a "left-over" indicator, so we have to so 923 1.3.2.2 pk * this no matter what. Ick. 924 1.3.2.2 pk */ 925 1.3.2.2 pk if ((dh->dh_flags & SIDH_OUT) == 0) { 926 1.3.2.2 pk char *cp = ncr_sc->sc_dataptr; 927 1.3.2.2 pk u_int32_t bpr; 928 1.3.2.2 pk 929 1.3.2.2 pk bpr = SWREG_READ(ncr_sc, SWREG_BPR); 930 1.3.2.2 pk 931 1.3.2.2 pk switch (dva & 3) { 932 1.3.2.2 pk case 3: 933 1.3.2.2 pk cp[0] = (bpr & 0xff000000) >> 24; 934 1.3.2.2 pk cp[1] = (bpr & 0x00ff0000) >> 16; 935 1.3.2.2 pk cp[2] = (bpr & 0x0000ff00) >> 8; 936 1.3.2.2 pk #ifdef COUNT_SW_LEFTOVERS 937 1.3.2.2 pk ++sw_3_leftover; 938 1.3.2.2 pk #endif 939 1.3.2.2 pk break; 940 1.3.2.2 pk 941 1.3.2.2 pk case 2: 942 1.3.2.2 pk cp[0] = (bpr & 0xff000000) >> 24; 943 1.3.2.2 pk cp[1] = (bpr & 0x00ff0000) >> 16; 944 1.3.2.2 pk #ifdef COUNT_SW_LEFTOVERS 945 1.3.2.2 pk ++sw_2_leftover; 946 1.3.2.2 pk #endif 947 1.3.2.2 pk break; 948 1.3.2.2 pk 949 1.3.2.2 pk case 1: 950 1.3.2.2 pk cp[0] = (bpr & 0xff000000) >> 24; 951 1.3.2.2 pk #ifdef COUNT_SW_LEFTOVERS 952 1.3.2.2 pk ++sw_1_leftover; 953 1.3.2.2 pk #endif 954 1.3.2.2 pk break; 955 1.3.2.2 pk 956 1.3.2.2 pk #ifdef COUNT_SW_LEFTOVERS 957 1.3.2.2 pk default: 958 1.3.2.2 pk ++sw_0_leftover; 959 1.3.2.2 pk break; 960 1.3.2.2 pk #endif 961 1.3.2.2 pk } 962 1.3.2.2 pk } 963 1.3.2.2 pk 964 1.3.2.2 pk out: 965 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_ADDR, 0); 966 1.3.2.2 pk SWREG_WRITE(ncr_sc, SWREG_DMA_CNT, 0); 967 1.3.2.2 pk 968 1.3.2.2 pk /* Put SBIC back in PIO mode. */ 969 1.3.2.2 pk mode = NCR5380_READ(ncr_sc, sci_mode); 970 1.3.2.2 pk mode &= ~(SCI_MODE_DMA | SCI_MODE_DMA_IE); 971 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_mode, mode); 972 1.3.2.2 pk NCR5380_WRITE(ncr_sc, sci_icmd, 0); 973 1.3.2.2 pk 974 1.3.2.2 pk #ifdef DEBUG 975 1.3.2.2 pk if (sw_debug & 2) { 976 1.3.2.2 pk printf("sw_dma_stop: ntrans=0x%x\n", ntrans); 977 1.3.2.2 pk } 978 1.3.2.2 pk #endif 979 1.3.2.2 pk } 980
Indexes created Tue Oct 07 21:09:53 GMT 2025