ts102reg.h revision 1.2
1 /* $NetBSD: ts102reg.h,v 1.2 1999/08/11 00:46:06 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 #ifndef _SPARC_DEV_TS102REG_H 39 #define _SPARC_DEV_TS102REG_H 40 41 /* There are two separate register blocks within the TS102. The first 42 * gives access to PCMCIA card specific resources, and the second gives 43 * access to the microcontroller interface 44 */ 45 #define TS102_REG_CARD_A_INT 0x0000 /* Card A Interrupt Register */ 46 #define TS102_REG_CARD_A_STS 0x0004 /* Card A Status Register */ 47 #define TS102_REG_CARD_A_CTL 0x0008 /* Card A Control Register */ 48 #define TS102_REG_CARD_B_INT 0x0010 /* Card B Interrupt Register */ 49 #define TS102_REG_CARD_B_STS 0x0014 /* Card B Status Register */ 50 #define TS102_REG_CARD_B_CTL 0x0018 /* Card B Control Register */ 51 #define TS102_REG_UCTRL_INT 0x0020 /* Microcontroller Interrupt Register */ 52 #define TS102_REG_UCTRL_DATA 0x0024 /* Microcontroller Data Register */ 53 #define TS102_REG_UCTRL_STS 0x0028 /* Microcontroller Status Register */ 54 55 /* TS102 Card Interrupt Register defintions. 56 * 57 * There is one 16-bit interrupt register for each card. Each register 58 * contains interrupt status (read) and clear (write) bits and an 59 * interrupt mask for each of the four interrupt sources. 60 * 61 * The request bit is the logical AND of the status and the mask bit, 62 * and indicated and an interrupt is being requested. The mask bits 63 * allow masking of individual interrupts. An interrupt is enabled when 64 * the mask is set to 1 and is clear by write a 1 to the associated 65 * request bit. 66 * 67 * The card interrupt register also contain the soft reset flag. 68 * Setting this bit to 1 will the SPARCbook 3 to be reset. 69 */ 70 #define TS102_CARD_INT_RQST_IRQ 0x0001 71 #define TS102_CARD_INT_RQST_WP_STATUS_CHANGED 0x0002 72 #define TS102_CARD_INT_RQST_BATTERY_STATUS_CHANGED 0x0004 73 #define TS102_CARD_INT_RQST_CARDDETECT_STATUS_CHANGED 0x0008 74 #define TS102_CARD_INT_STATUS_IRQ 0x0010 75 #define TS102_CARD_INT_STATUS_WP_STATUS_CHANGED 0x0020 76 #define TS102_CARD_INT_STATUS_BATTERY_STATUS_CHANGED 0x0040 77 #define TS102_CARD_INT_STATUS_CARDDETECT_STATUS_CHANGED 0x0080 78 #define TS102_CARD_INT_MASK_IRQ 0x0100 79 #define TS102_CARD_INT_MASK_WP_STATUS 0x0200 80 #define TS102_CARD_INT_MASK_BATTERY_STATUS 0x0400 81 #define TS102_CARD_INT_MASK_CARDDETECT_STATUS 0x0800 82 #define TS102_CARD_INT_SOFT_RESET 0x1000 83 84 /* TS102 Card Status Register definitions. The Card Status Register 85 * contains card status and control bit. 86 */ 87 #define TS102_CARD_STS_PRES 0x0001 /* Card Present (1) */ 88 #define TS102_CARD_STS_IO 0x0002 /* (1) I/O Card, (0) = Mem Card */ 89 #define TS102_CARD_STS_TYPE3 0x0004 /* Type-3 PCMCIA card (disk) */ 90 #define TS102_CARD_STS_VCC 0x0008 /* Vcc (0=5V, 1=3.3V) */ 91 #define TS102_CARD_STS_VPP1_MASK 0x0030 /* Programming Voltage Control2 */ 92 #define TS102_CARD_STS_VPP1_NC 0x0030 /* NC */ 93 #define TS102_CARD_STS_VPP1_VCC 0x0020 /* Vcc (3.3V or 5V) */ 94 #define TS102_CARD_STS_VPP1_VPP 0x0010 /* Vpp (12V) */ 95 #define TS102_CARD_STS_VPP1_0V 0x0000 /* 0V */ 96 #define TS102_CARD_STS_VPP2_MASK 0x00c0 /* Programming Voltage Control1 */ 97 #define TS102_CARD_STS_VPP2_NC 0x00c0 /* NC */ 98 #define TS102_CARD_STS_VPP2_VCC 0x0080 /* Vcc (3.3V or 5V) */ 99 #define TS102_CARD_STS_VPP2_VPP 0x0040 /* Vpp (12V) */ 100 #define TS102_CARD_STS_VPP2_0V 0x0000 /* 0V */ 101 #define TS102_CARD_STS_WP 0x0100 /* Write Protect (1) */ 102 #define TS102_CARD_STS_BVD_MASK 0x0600 /* Battery Voltage Detect */ 103 #define TS102_CARD_STS_BVD_GOOD 0x0600 /* Battery good */ 104 #define TS102_CARD_STS_BVD_LOW_OK 0x0400 /* Battery low, data OK */ 105 #define TS102_CARD_STS_BVD_LOW_SUSPECT1 0x0200 /* Battery low, data suspect */ 106 #define TS102_CARD_STS_BVD_LOW_SUSPECT0 0x0000 /* Battery low, data suspect */ 107 #define TS102_CARD_STS_LVL 0x0800 /* Level (1) / Edge */ 108 #define TS102_CARD_STS_RDY 0x1000 /* Ready (1) / Not Busy */ 109 #define TS102_CARD_STS_VCCEN 0x2000 /* Powered Up (0) */ 110 #define TS102_CARD_STS_RIEN 0x4000 /* Not Supported */ 111 #define TS102_CARD_STS_ACEN 0x8000 /* Access Enabled (1) */ 112 113 /* TS102 Card Control Register definitions 114 */ 115 #define TS102_CARD_CTL_AA_MASK 0x0003 /* Attribute Address A[25:24] */ 116 #define TS102_CARD_CTL_IA_MASK 0x000c /* I/O Address A[25:24] */ 117 #define TS102_CARD_CTL_IA_BITPOS 2 /* */ 118 #define TS102_CARD_CTL_CES_MASK 0x0070 /* CE/address setup time */ 119 #define TS102_CARD_CTL_CES_BITPOS 4 /* n+1 clocks */ 120 #define TS102_CARD_CTL_OWE_MASK 0x0380 /* OE/WE width */ 121 #define TS102_CARD_CTL_OWE_BITPOS 7 /* n+2 clocks */ 122 #define TS102_CARD_CTL_CEH 0x0400 /* Chip enable hold time */ 123 /* (0) - 1 clock */ 124 /* (1) - 2 clocks */ 125 #define TS102_CARD_CTL_SBLE 0x0800 /* SBus little endian */ 126 #define TS102_CARD_CTL_PCMBE 0x1000 /* PCMCIA big endian */ 127 #define TS102_CARD_CTL_RAHD 0x2000 /* Read ahead enable */ 128 #define TS102_CARD_CTL_INCDIS 0x4000 /* Address increment disable */ 129 #define TS102_CARD_CTL_PWRD 0x8000 /* Power down */ 130 131 /* Microcontroller Interrupt Register 132 */ 133 #define TS102_UCTRL_INT_TXE_REQ 0x01 /* transmit FIFO empty */ 134 #define TS102_UCTRL_INT_TXNF_REQ 0x02 /* transmit FIFO not full */ 135 #define TS102_UCTRL_INT_RXNE_REQ 0x04 /* receive FIFO not empty */ 136 #define TS102_UCTRL_INT_RXO_REQ 0x08 /* receive FIFO overflow */ 137 #define TS102_UCTRL_INT_TXE_MSK 0x10 /* transmit FIFO empty */ 138 #define TS102_UCTRL_INT_TXNF_MSK 0x20 /* transmit FIFO not full */ 139 #define TS102_UCTRL_INT_RXNE_MSK 0x40 /* receive FIFO not empty */ 140 #define TS102_UCTRL_INT_RXO_MSK 0x80 /* receive FIFO overflow */ 141 142 /* TS102 Microcontroller Data Register (only 8 bits are significant). 143 */ 144 #define TS102_UCTRL_DATA_MASK 0xff 145 146 /* TS102 Microcontroller Status Register. 147 * read 1 if asserted 148 * write 1 to clear 149 */ 150 #define TS102_UCTRL_STS_TXE_STA 0x01 /* transmit FIFO empty */ 151 #define TS102_UCTRL_STS_TXNF_STA 0x02 /* transmit FIFO not full */ 152 #define TS102_UCTRL_STS_RXNE_STA 0x04 /* receive FIFO not empty */ 153 #define TS102_UCTRL_STS_RXO_STA 0x08 /* receive FIFO overflow */ 154 155 enum ts102_opcode { /* Argument Returned */ 156 TS102_OP_RD_SERIAL_NUM=0x01, /* none ack + 4 bytes */ 157 TS102_OP_RD_ETHER_ADDR=0x02, /* none ack + 6 bytes */ 158 TS102_OP_RD_HW_VERSION=0x03, /* none ack + 2 bytes */ 159 TS102_OP_RD_UCTLR_VERSION=0x04, /* none ack + 2 bytes */ 160 TS102_OP_RD_MAX_TEMP=0x05, /* none ack + 1 bytes */ 161 TS102_OP_RD_MIN_TEMP=0x07, /* none ack + 1 bytes */ 162 TS102_OP_RD_CURRENT_TEMP=0x06, /* none ack + 1 bytes */ 163 TS102_OP_RD_SYSTEM_VARIANT=0x08, /* none ack + 4 bytes */ 164 TS102_OP_RD_POWERON_CYCLES=0x09, /* none ack + 4 bytes */ 165 TS102_OP_RD_POWERON_SECONDS=0x0a, /* none ack + 4 bytes */ 166 TS102_OP_RD_RESET_STATUS=0x0b, /* none ack + 1 bytes */ 167 #define TS102_RESET_STATUS_RESERVED0 0x00 168 #define TS102_RESET_STATUS_POWERON 0x01 169 #define TS102_RESET_STATUS_KEYBOARD 0x02 170 #define TS102_RESET_STATUS_WATCHDOG 0x03 171 #define TS102_RESET_STATUS_TIMEOUT 0x04 172 #define TS102_RESET_STATUS_SOFTWARE 0x05 173 #define TS102_RESET_STATUS_BROWNOUT 0x06 174 #define TS102_RESET_STATUS_RESERVED1 0x07 175 TS102_OP_RD_EVENT_STATUS=0x0c, /* none ack + 2 bytes */ 176 #define TS102_EVENT_STATUS_SHUTDOWN_REQUEST 0x0001 177 #define TS102_EVENT_STATUS_LOW_POWER_WARNING 0x0002 178 #define TS102_EVENT_STATUS_VERY_LOW_POWER_WARNING 0x0004 179 #define TS102_EVENT_STATUS_BATT_CHANGED 0x0008 180 #define TS102_EVENT_STATUS_EXT_KEYBOARD_STATUS_CHANGE 0x0010 181 #define TS102_EVENT_STATUS_EXT_MOUSE_STATUS_CHANGE 0x0020 182 #define TS102_EVENT_STATUS_EXTERNAL_VGA_STATUS_CHANGE 0x0040 183 #define TS102_EVENT_STATUS_LID_STATUS_CHANGE 0x0080 184 #define TS102_EVENT_STATUS_MICROCONTROLLER_ERROR 0x0100 185 #define TS102_EVENT_STATUS_RESERVED 0x0200 186 #define TS102_EVENT_STATUS_EXT_BATT_STATUS_CHANGE 0x0400 187 #define TS102_EVENT_STATUS_EXT_BATT_CHARGING_STATUS_CHANGE 0x0800 188 #define TS102_EVENT_STATUS_EXT_BATT_LOW_POWER 0x1000 189 #define TS102_EVENT_STATUS_DC_STATUS_CHANGE 0x2000 190 #define TS102_EVENT_STATUS_CHARGING_STATUS_CHANGE 0x4000 191 #define TS102_EVENT_STATUS_POWERON_BTN_PRESSED 0x8000 192 TS102_OP_RD_REAL_TIME_CLK=0x0d, /* none ack + 7 bytes */ 193 TS102_OP_RD_EXT_VGA_PORT=0x0e, /* none ack + 1 bytes */ 194 TS102_OP_RD_UCTRL_ROM_CKSUM=0x0f, /* none ack + 2 bytes */ 195 TS102_OP_RD_ERROR_STATUS=0x10, /* none ack + 2 bytes */ 196 #define TS102_ERROR_STATUS_NO_ERROR 0x00 197 #define TS102_ERROR_STATUS_COMMAND_ERROR 0x01 198 #define TS102_ERROR_STATUS_EXECUTION_ERROR 0x02 199 #define TS102_ERROR_STATUS_PHYSICAL_ERROR 0x04 200 TS102_OP_RD_EXT_STATUS=0x11, /* none ack + 2 bytes */ 201 #define TS102_EXT_STATUS_MAIN_POWER_AVAILABLE 0x0001 202 #define TS102_EXT_STATUS_INTERNAL_BATTERY_ATTACHED 0x0002 203 #define TS102_EXT_STATUS_EXTERNAL_BATTERY_ATTACHED 0x0004 204 #define TS102_EXT_STATUS_EXTERNAL_VGA_ATTACHED 0x0008 205 #define TS102_EXT_STATUS_EXTERNAL_KEYBOARD_ATTACHED 0x0010 206 #define TS102_EXT_STATUS_EXTERNAL_MOUSE_ATTACHED 0x0020 207 #define TS102_EXT_STATUS_LID_DOWN 0x0040 208 #define TS102_EXT_STATUS_INTERNAL_BATTERY_CHARGING 0x0080 209 #define TS102_EXT_STATUS_EXTERNAL_BATTERY_CHARGING 0x0100 210 #define TS102_EXT_STATUS_INTERNAL_BATTERY_DISCHARGING 0x0200 211 #define TS102_EXT_STATUS_EXTERNAL_BATTERY_DISCHARGING 0x0400 212 TS102_OP_RD_USER_CONFIG=0x12, /* none ack + 2 bytes */ 213 TS102_OP_RD_UCTRL_VLT=0x13, /* none ack + 1 bytes */ 214 TS102_OP_RD_INT_BATT_VLT=0x14, /* none ack + 1 bytes */ 215 TS102_OP_RD_DC_IN_VLT=0x15, /* none ack + 1 bytes */ 216 TS102_OP_RD_HORZ_PRT_VLT=0x16, /* none ack + 1 bytes */ 217 TS102_OP_RD_VERT_PTR_VLT=0x17, /* none ack + 1 bytes */ 218 TS102_OP_RD_INT_CHANGE_LEVEL=0x18, /* none ack + 1 bytes */ 219 TS102_OP_RD_EXT_CHARGE_LEVEL=0x19, /* none ack + 1 bytes */ 220 TS102_OP_RD_RTC_ALARM=0x1a, /* none ack + 7 bytes */ 221 TS102_OP_RD_EVENT_STATUS_NO_RESET=0x1b, /* none ack + 2 bytes */ 222 TS102_OP_RD_INT_KBD_LAYOUT=0x1c, /* none ack + 2 bytes */ 223 TS102_OP_RD_EXT_KBD_LAYOUT=0x1d, /* none ack + 2 bytes */ 224 TS102_OP_RD_EEPROM_STATUS=0x1e, /* none ack + 2 bytes */ 225 #define TS102_EEPROM_STATUS_FACTORY_AREA_CHECKSUM_FAIL 0x01 226 #define TS102_EEPROM_STATUS_CONSUMER_AREA_CHECKSUM_FAIL 0x02 227 #define TS102_EEPROM_STATUS_USER_AREA_CHECKSUM_FAIL 0x04 228 #define TS102_EEPROM_STATUS_VPD_AREA_CHECKSUM_FAIL 0x08 229 230 /* Read/Write/Modify Commands 231 */ 232 TS102_OP_CTL_LCD=0x20, /* mask ack + 2 bytes */ 233 #define TS102_LCD_CAPS_LOCK 0x0001 234 #define TS102_LCD_SCROLL_LOCK 0x0002 235 #define TS102_LCD_NUMLOCK 0x0004 236 #define TS102_LCD_DISK_ACTIVE 0x0008 237 #define TS102_LCD_LAN_ACTIVE 0x0010 238 #define TS102_LCD_WAN_ACTIVE 0x0020 239 #define TS102_LCD_PCMCIA_ACTIVE 0x0040 240 #define TS102_LCD_DC_OK 0x0080 241 #define TS102_LCD_COMPOSE 0x0100 242 TS102_OP_CTL_BITPORT=0x21, /* mask ack + 1 byte */ 243 #define TS102_BITPORT_TFTPWR 0x01 /* TFT power (low) */ 244 #define TS102_BITPORT_SYNCINVA 0x04 /* ext. monitor sync (low) */ 245 #define TS102_BITPORT_SYNCINVB 0x08 /* ext. monitor sync (low) */ 246 #define TS102_BITPORT_BP_DIS 0x10 /* no bootprom from pcmcia (high) */ 247 /* boot from pcmcia (low */ 248 #define TS102_BITPORT_ENCSYNC 0x20 /* enab composite sync (low) */ 249 TS102_OP_CTL_SPEAKER_VOLUME=0x23, /* mask ack + 1 byte */ 250 TS102_OP_CTL_TFT_BIRGHNESS=0x24, /* mask ack + 1 byte */ 251 TS102_OP_CTL_WATCHDOG=0x25, /* mask ack + 1 byte */ 252 TS102_OP_CTL_FCTRY_EEPROM=0x26, /* mask ack + 1 byte */ 253 TS102_OP_CTL_KDB_TIME_UNTL_RTP=0x28, /* mask ack + 1 byte */ 254 TS102_OP_CTL_KBD_TIME_BTWN_RPTS=0x29, /* mask ack + 1 byte */ 255 TS102_OP_CTL_TIMEZONE=0x2a, /* mask ack + 1 byte */ 256 TS102_OP_CTL_MARK_SPACE_RATIO=0x2b, /* mask ack + 1 byte */ 257 TS102_OP_CTL_DIAGNOSTIC_MODE=0x2e, /* mask ack + 1 byte */ 258 #define TS102_DIAGNOSTIC_MODE_CMD_DIAG_ON_LCD 0x01 259 #define TS102_DIAGNOSTIC_MODE_KDB_MS_9600 0x02 260 TS102_OP_CTL_SCREEN_CONTRAST=0x2f, /* mask ack + 1 byte */ 261 262 /* Commands returning no status 263 */ 264 TS102_OP_CMD_RING_BELL=0x30, /* msb,lsb ack */ 265 TS102_OP_CMD_DIAGNOSTIC_STATUS=0x32, /* msb,lsb ack */ 266 TS102_OP_CMD_CLR_KEY_COMBO_TBL=0x33, /* none ack */ 267 TS102_OP_CMD_SOFTWARE_RESET=0x34, /* none ack */ 268 TS102_OP_CMD_SET_RTC=0x35, /* smhddmy ack */ 269 TS102_OP_CMD_RECAL_PTR=0x36, /* none ack */ 270 TS102_OP_CMD_SET_BELL_FREQ=0x37, /* msb,lsb ack */ 271 TS102_OP_CMD_SET_INT_BATT_RATE=0x39, /* charge-lvl ack */ 272 TS102_OP_CMD_SET_EXT_BATT_RATE=0x3a, /* charge-lvl ack */ 273 TS102_OP_CMD_SET_RTC_ALARM=0x3b, /* smhddmy ack */ 274 275 /* Block transfer commands 276 */ 277 TS102_OP_BLK_RD_EEPROM=0x40, /* len off ack <data> */ 278 TS102_OP_BLK_WR_EEPROM=0x41, /* len off <data> ack */ 279 TS102_OP_BLK_WR_STATUS=0x42, /* len off <data> ack */ 280 TS102_OP_BLK_DEF_SPCL_CHAR=0x43, /* len off <data> ack */ 281 #define TS102_BLK_OFF_DEF_WAN1 0 282 #define TS102_BLK_OFF_DEF_WAN2 1 283 #define TS102_BLK_OFF_DEF_LAN1 2 284 #define TS102_BLK_OFF_DEF_LAN2 3 285 #define TS102_BLK_OFF_DEF_PCMCIA 4 286 #define TS102_BLK_OFF_DEF_DC_GOOD 5 287 #define TS102_BLK_OFF_DEF_BACKSLASH 6 288 289 /* Generic commands 290 */ 291 TS102_OP_GEN_DEF_KEY_COMBO_ENT=0x50, /* seq com-length ack */ 292 TS102_OP_GEN_DEF_STRING_TBL_ENT=0x51, /* str-code len <str> ack */ 293 TS102_OP_GEN_DEF_STS_CTRN_DISP=0x52, /* len <msg> ack */ 294 295 /* Generic commands with optional status 296 */ 297 TS102_OP_GEN_STS_EMU_COMMAND=0x64, /* <command> ack */ 298 TS102_OP_GEN_STS_RD_EMU_REGISTER=0x65, /* reg ack + 1 byte */ 299 TS102_OP_GEN_STS_WR_EMU_REGISTER=0x66, /* reg,val ack */ 300 TS102_OP_GEN_STS_RD_EMU_RAM=0x67, /* addr ack + 1 byte */ 301 TS102_OP_GEN_STS_WR_EMU_RAM=0x68, /* addr,val ack */ 302 TS102_OP_GEN_STS_RD_BQ_REGISTER=0x69, /* reg ack + 1 byte */ 303 TS102_OP_GEN_STS_WR_BQ_REGISTER=0x6a, /* reg,val ack */ 304 305 /* Administration commands 306 */ 307 TS102_OP_ADMIN_SET_USER_PASS=0x70, /* len <pass> ack */ 308 TS102_OP_ADMIN_VRFY_USER_PASS=0x71, /* len <pass> ack + status */ 309 TS102_OP_ADMIN_GET_SYSTEM_PASS=0x72, /* none ack + <7bytekey> */ 310 TS102_OP_ADMIN_VRFY_SYSTEM_PASS=0x73, /* len <pass> ack + status */ 311 TS102_OP_ADMIN_POWER_OFF=0x82, /* len <pass> none */ 312 TS102_OP_ADMIN_POWER_RESTART=0x83, /* msb,xx,lsb none */ 313 }; 314 315 #endif /* _SPARC_DEV_TS102REG_H */ 316
Indexes created Thu Sep 25 16:09:42 GMT 2025