vme_machdep.c revision 1.13
1 /* $NetBSD: vme_machdep.c,v 1.13 1998/08/30 21:26:46 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <sys/proc.h> 46 #include <sys/user.h> 47 #include <sys/syslog.h> 48 49 #include <vm/vm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <sparc/sparc/iommuvar.h> 54 #include <machine/autoconf.h> 55 #include <machine/pmap.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmevar.h> 61 62 #include <sparc/sparc/asm.h> 63 #include <sparc/sparc/vaddrs.h> 64 #include <sparc/sparc/cpuvar.h> 65 #include <sparc/dev/vmereg.h> 66 67 struct vmebus_softc { 68 struct device sc_dev; /* base device */ 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 struct vmebusreg *sc_reg; /* VME control registers */ 72 struct vmebusvec *sc_vec; /* VME interrupt vector */ 73 struct rom_range *sc_range; /* ROM range property */ 74 int sc_nrange; 75 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 76 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 77 int (*sc_vmeintr) __P((void *)); 78 struct bootpath *sc_bp; 79 }; 80 struct vmebus_softc *vmebus_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 #endif 93 94 95 static int sparc_vme_probe __P((void *, bus_space_tag_t, vme_addr_t, 96 size_t, vme_size_t, vme_mod_t, 97 int (*) __P((void *, void *)), void *)); 98 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_mod_t, 99 bus_space_tag_t, bus_space_handle_t *)); 100 static void sparc_vme_unmap __P((void *)); 101 static int sparc_vme_mmap_cookie __P((void *, vme_addr_t, vme_mod_t, 102 bus_space_tag_t, bus_space_handle_t *)); 103 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 104 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, 105 int (*) __P((void *)), void *)); 106 static void sparc_vme_intr_disestablish __P((void *, void *)); 107 108 static int vmebus_translate __P((struct vmebus_softc *, vme_mod_t, 109 vme_addr_t, bus_type_t *, bus_addr_t *)); 110 static void sparc_vme_bus_establish __P((void *, struct device *)); 111 #if defined(SUN4M) 112 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 113 bus_size_t, bus_size_t, int)); 114 115 #endif 116 117 /* 118 * DMA functions. 119 */ 120 #if defined(SUN4) 121 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 122 bus_size_t, struct proc *, int)); 123 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 124 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 125 bus_addr_t, bus_size_t, int)); 126 127 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 128 bus_size_t, bus_size_t, bus_dma_segment_t *, 129 int, int *, int)); 130 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 131 bus_dma_segment_t *, int)); 132 #endif 133 134 #if defined(SUN4M) 135 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 136 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 137 138 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 139 bus_size_t, struct proc *, int)); 140 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 141 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 142 bus_addr_t, bus_size_t, int)); 143 144 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 145 bus_size_t, bus_size_t, bus_dma_segment_t *, 146 int, int *, int)); 147 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 148 bus_dma_segment_t *, int)); 149 #endif 150 151 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 152 int, size_t, caddr_t *, int)); 153 #if 0 154 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 155 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 156 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 157 bus_dma_segment_t *, int, int, int, int)); 158 #endif 159 160 struct cfattach vme_mainbus_ca = { 161 sizeof(struct vmebus_softc), vmematch_mainbus, vmeattach_mainbus 162 }; 163 164 struct cfattach vme_iommu_ca = { 165 sizeof(struct vmebus_softc), vmematch_iommu, vmeattach_iommu 166 }; 167 168 /* If the PROM does not provide the `ranges' property, we make up our own */ 169 struct rom_range vmebus_translations[] = { 170 #define _DS (VMEMOD_D|VMEMOD_S) 171 { VMEMOD_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 172 { VMEMOD_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 173 { VMEMOD_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 174 { VMEMOD_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 175 { VMEMOD_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 176 { VMEMOD_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 177 #undef _DS 178 }; 179 180 /* 181 * DMA on sun4 VME devices use the last MB of virtual space, which 182 * is mapped by hardware onto the first MB of VME space. 183 */ 184 struct extent *vme_dvmamap; 185 186 struct sparc_bus_space_tag sparc_vme_bus_tag = { 187 NULL, /* cookie */ 188 NULL, /* parent bus tag */ 189 NULL, /* bus_map */ 190 NULL, /* bus_unmap */ 191 NULL, /* bus_subregion */ 192 NULL /* barrier */ 193 }; 194 195 struct vme_chipset_tag sparc_vme_chipset_tag = { 196 NULL, 197 sparc_vme_probe, 198 sparc_vme_map, 199 sparc_vme_unmap, 200 sparc_vme_mmap_cookie, 201 sparc_vme_intr_map, 202 sparc_vme_intr_establish, 203 sparc_vme_intr_disestablish, 204 sparc_vme_bus_establish 205 }; 206 207 208 #if defined(SUN4) 209 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 210 NULL, /* cookie */ 211 _bus_dmamap_create, 212 _bus_dmamap_destroy, 213 sparc_vme4_dmamap_load, 214 _bus_dmamap_load_mbuf, 215 _bus_dmamap_load_uio, 216 _bus_dmamap_load_raw, 217 sparc_vme4_dmamap_unload, 218 sparc_vme4_dmamap_sync, 219 220 sparc_vme4_dmamem_alloc, 221 sparc_vme4_dmamem_free, 222 sparc_vme_dmamem_map, 223 _bus_dmamem_unmap, 224 _bus_dmamem_mmap 225 }; 226 #endif 227 228 #if defined(SUN4M) 229 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 230 NULL, /* cookie */ 231 sparc_vme4m_dmamap_create, 232 _bus_dmamap_destroy, 233 sparc_vme4m_dmamap_load, 234 _bus_dmamap_load_mbuf, 235 _bus_dmamap_load_uio, 236 _bus_dmamap_load_raw, 237 sparc_vme4m_dmamap_unload, 238 sparc_vme4m_dmamap_sync, 239 240 sparc_vme4m_dmamem_alloc, 241 sparc_vme4m_dmamem_free, 242 sparc_vme_dmamem_map, 243 _bus_dmamem_unmap, 244 _bus_dmamem_mmap 245 }; 246 #endif 247 248 249 void 250 sparc_vme_bus_establish(cookie, dev) 251 void *cookie; 252 struct device *dev; 253 { 254 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 255 struct bootpath *bp = sc->sc_bp; 256 char *name; 257 258 name = dev->dv_cfdata->cf_driver->cd_name; 259 #ifdef DEBUG 260 printf("sparc_vme_bus_establish: %s%d\n", name, dev->dv_unit); 261 #endif 262 if (bp != NULL && strcmp(bp->name, name) == 0 && 263 dev->dv_unit == bp->val[1]) { 264 bp->dev = dev; 265 #ifdef DEBUG 266 printf("sparc_vme_bus_establish: on the boot path\n"); 267 #endif 268 sc->sc_bp++; 269 bootpath_store(1, sc->sc_bp); 270 } 271 } 272 273 274 int 275 vmematch_mainbus(parent, cf, aux) 276 struct device *parent; 277 struct cfdata *cf; 278 void *aux; 279 { 280 281 if (!CPU_ISSUN4) 282 return (0); 283 284 return (1); 285 } 286 287 int 288 vmematch_iommu(parent, cf, aux) 289 struct device *parent; 290 struct cfdata *cf; 291 void *aux; 292 { 293 struct mainbus_attach_args *ma = aux; 294 295 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 296 } 297 298 299 void 300 vmeattach_mainbus(parent, self, aux) 301 struct device *parent, *self; 302 void *aux; 303 { 304 #if defined(SUN4) 305 struct mainbus_attach_args *ma = aux; 306 struct vmebus_softc *sc = (struct vmebus_softc *)self; 307 struct vme_busattach_args vba; 308 309 if (self->dv_unit > 0) { 310 printf(" unsupported\n"); 311 return; 312 } 313 314 sc->sc_bustag = ma->ma_bustag; 315 sc->sc_dmatag = ma->ma_dmatag; 316 317 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 318 sc->sc_bp = ma->ma_bp + 1; 319 bootpath_store(1, sc->sc_bp); 320 } 321 322 /* VME interrupt entry point */ 323 sc->sc_vmeintr = vmeintr4; 324 325 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 326 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 327 328 vba.vba_bustag = &sparc_vme_bus_tag; 329 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 330 vba.vba_dmatag = &sparc_vme4_dma_tag; 331 332 /* Fall back to our own `range' construction */ 333 sc->sc_range = vmebus_translations; 334 sc->sc_nrange = 335 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 336 337 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 338 M_DEVBUF, 0, 0, EX_NOWAIT); 339 if (vme_dvmamap == NULL) 340 panic("vme: unable to allocate DVMA map"); 341 342 printf("\n"); 343 (void)config_search(vmesearch, self, &vba); 344 345 bootpath_store(1, NULL); 346 #endif 347 return; 348 } 349 350 /* sun4m vmebus */ 351 void 352 vmeattach_iommu(parent, self, aux) 353 struct device *parent, *self; 354 void *aux; 355 { 356 #if defined(SUN4M) 357 struct vmebus_softc *sc = (struct vmebus_softc *)self; 358 struct iommu_attach_args *ia = aux; 359 struct vme_busattach_args vba; 360 bus_space_handle_t bh; 361 struct rom_reg *rr; 362 int nreg; 363 int node; 364 int cline; 365 366 if (self->dv_unit > 0) { 367 printf(" unsupported\n"); 368 return; 369 } 370 371 sc->sc_bustag = ia->iom_bustag; 372 sc->sc_dmatag = ia->iom_dmatag; 373 374 /* VME interrupt entry point */ 375 sc->sc_vmeintr = vmeintr4m; 376 377 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 378 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 379 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 380 381 vba.vba_bustag = &sparc_vme_bus_tag; 382 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 383 vba.vba_dmatag = &sparc_vme4m_dma_tag; 384 385 node = ia->iom_node; 386 387 /* 388 * Map VME control space 389 */ 390 rr = NULL; 391 if (getprop(node, "reg", sizeof(*rr), &nreg, (void**)&rr) != 0) { 392 printf("%s: can't get register property\n", self->dv_xname); 393 return; 394 } 395 if (nreg < 2) { 396 printf("%s: only %d register sets\n", self->dv_xname, nreg); 397 return; 398 } 399 400 if (bus_space_map2(ia->iom_bustag, 401 (bus_type_t)rr[0].rr_iospace, 402 (bus_addr_t)rr[0].rr_paddr, 403 (bus_size_t)rr[0].rr_len, 404 BUS_SPACE_MAP_LINEAR, 405 0, &bh) != 0) { 406 panic("%s: can't map vmebusreg", self->dv_xname); 407 } 408 sc->sc_reg = (struct vmebusreg *)bh; 409 410 if (bus_space_map2(ia->iom_bustag, 411 (bus_type_t)rr[1].rr_iospace, 412 (bus_addr_t)rr[1].rr_paddr, 413 (bus_size_t)rr[1].rr_len, 414 BUS_SPACE_MAP_LINEAR, 415 0, &bh) != 0) { 416 panic("%s: can't map vmebusvec", self->dv_xname); 417 } 418 sc->sc_vec = (struct vmebusvec *)bh; 419 420 /* 421 * Map VME IO cache tags and flush control. 422 */ 423 if (bus_space_map2(ia->iom_bustag, 424 (bus_type_t)rr[1].rr_iospace, 425 (bus_addr_t)rr[1].rr_paddr + VME_IOC_TAGOFFSET, 426 VME_IOC_SIZE, 427 BUS_SPACE_MAP_LINEAR, 428 0, &bh) != 0) { 429 panic("%s: can't map IOC tags", self->dv_xname); 430 } 431 sc->sc_ioctags = (u_int32_t *)bh; 432 433 if (bus_space_map2(ia->iom_bustag, 434 (bus_type_t)rr[1].rr_iospace, 435 (bus_addr_t)rr[1].rr_paddr + VME_IOC_FLUSHOFFSET, 436 VME_IOC_SIZE, 437 BUS_SPACE_MAP_LINEAR, 438 0, &bh) != 0) { 439 panic("%s: can't map IOC flush registers", self->dv_xname); 440 } 441 sc->sc_iocflush = (u_int32_t *)bh; 442 443 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 444 445 /* 446 * Get "range" property. 447 */ 448 if (getprop(node, "ranges", sizeof(struct rom_range), 449 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 450 panic("%s: can't get ranges property", self->dv_xname); 451 } 452 453 vmebus_sc = sc; 454 455 /* 456 * Invalidate all IO-cache entries. 457 */ 458 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 459 sc->sc_ioctags[--cline] = 0; 460 } 461 462 /* Enable IO-cache */ 463 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 464 465 printf(": version 0x%x\n", 466 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 467 468 (void)config_search(vmesearch, self, &vba); 469 #endif 470 } 471 472 void sparc_vme_async_fault __P((void)); 473 void 474 sparc_vme_async_fault() 475 { 476 struct vmebus_softc *sc = vmebus_sc; 477 u_int32_t addr; 478 479 addr = sc->sc_reg->vmebus_afar; 480 printf("vme afsr: %x; addr %x\n", sc->sc_reg->vmebus_afsr, addr); 481 } 482 483 int 484 vmebus_translate(sc, mod, addr, btp, bap) 485 struct vmebus_softc *sc; 486 vme_mod_t mod; 487 vme_addr_t addr; 488 bus_type_t *btp; 489 bus_addr_t *bap; 490 { 491 int i; 492 493 for (i = 0; i < sc->sc_nrange; i++) { 494 495 if (sc->sc_range[i].cspace != mod) 496 continue; 497 498 /* We've found the connection to the parent bus */ 499 *bap = sc->sc_range[i].poffset + addr; 500 *btp = sc->sc_range[i].pspace; 501 return (0); 502 } 503 return (ENOENT); 504 } 505 506 int 507 sparc_vme_probe(cookie, tag, addr, offset, size, mod, callback, arg) 508 void *cookie; 509 bus_space_tag_t tag; 510 vme_addr_t addr; 511 size_t offset; 512 vme_size_t size; 513 int mod; 514 int (*callback) __P((void *, void *)); 515 void *arg; 516 { 517 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 518 bus_type_t iospace; 519 bus_addr_t paddr; 520 521 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 522 return (0); 523 524 return (bus_space_probe(sc->sc_bustag, iospace, paddr, size, offset, 525 0, callback, arg)); 526 } 527 528 int 529 sparc_vme_map(cookie, addr, size, mod, tag, hp) 530 void *cookie; 531 vme_addr_t addr; 532 vme_size_t size; 533 int mod; 534 bus_space_tag_t tag; 535 bus_space_handle_t *hp; 536 { 537 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 538 bus_type_t iospace; 539 bus_addr_t paddr; 540 int error; 541 542 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 543 if (error != 0) 544 return (error); 545 546 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 547 } 548 549 int 550 sparc_vme_mmap_cookie(cookie, addr, mod, tag, hp) 551 void *cookie; 552 vme_addr_t addr; 553 int mod; 554 bus_space_tag_t tag; 555 bus_space_handle_t *hp; 556 { 557 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 558 bus_type_t iospace; 559 bus_addr_t paddr; 560 int error; 561 562 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 563 if (error != 0) 564 return (error); 565 566 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 567 } 568 569 #if defined(SUN4M) 570 void 571 sparc_vme4m_barrier(t, h, offset, size, flags) 572 bus_space_tag_t t; 573 bus_space_handle_t h; 574 bus_size_t offset; 575 bus_size_t size; 576 int flags; 577 { 578 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 579 580 /* Read async fault status to flush write-buffers */ 581 (*(volatile int *)&vbp->vmebus_afsr); 582 } 583 #endif 584 585 586 587 /* 588 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 589 */ 590 static int vme_ipl_to_pil[] = { 591 0, 592 2, 593 3, 594 5, 595 7, 596 9, 597 11, 598 13 599 }; 600 601 602 /* 603 * All VME device interrupts go through vmeintr(). This function reads 604 * the VME vector from the bus, then dispatches the device interrupt 605 * handler. All handlers for devices that map to the same Processor 606 * Interrupt Level (according to the table above) are on a linked list 607 * of `sparc_vme_intr_handle' structures. The head of which is passed 608 * down as the argument to `vmeintr(void *arg)'. 609 */ 610 struct sparc_vme_intr_handle { 611 struct intrhand ih; 612 struct sparc_vme_intr_handle *next; 613 int vec; /* VME interrupt vector */ 614 int pri; /* VME interrupt priority */ 615 struct vmebus_softc *sc;/*XXX*/ 616 }; 617 618 #if defined(SUN4) 619 int 620 vmeintr4(arg) 621 void *arg; 622 { 623 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 624 int level, vec; 625 int i = 0; 626 627 level = (ihp->pri << 1) | 1; 628 629 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 630 631 if (vec == -1) { 632 printf("vme: spurious interrupt\n"); 633 return 1; /* XXX - pretend we handled it, for now */ 634 } 635 636 for (; ihp; ihp = ihp->next) 637 if (ihp->vec == vec && ihp->ih.ih_fun) 638 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 639 return (i); 640 } 641 #endif 642 643 #if defined(SUN4M) 644 int 645 vmeintr4m(arg) 646 void *arg; 647 { 648 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 649 int level, vec; 650 int i = 0; 651 652 level = (ihp->pri << 1) | 1; 653 654 #if 0 655 int pending; 656 657 /* Flush VME <=> Sbus write buffers */ 658 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 659 660 pending = *((int*)ICR_SI_PEND); 661 if ((pending & SINTR_VME(ihp->pri)) == 0) { 662 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 663 ihp->pri, pending); 664 return (0); 665 } 666 #endif 667 #if 0 668 /* Why gives this a bus timeout sometimes? */ 669 vec = ihp->sc->sc_vec->vmebusvec[level]; 670 #else 671 /* so, arrange to catch the fault... */ 672 { 673 extern struct user *proc0paddr; 674 extern int fkbyte __P((caddr_t, struct pcb *)); 675 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 676 struct pcb *xpcb; 677 u_long saveonfault; 678 int s; 679 680 s = splhigh(); 681 if (curproc == NULL) 682 xpcb = (struct pcb *)proc0paddr; 683 else 684 xpcb = &curproc->p_addr->u_pcb; 685 686 saveonfault = (u_long)xpcb->pcb_onfault; 687 vec = fkbyte(addr, xpcb); 688 xpcb->pcb_onfault = (caddr_t)saveonfault; 689 690 splx(s); 691 } 692 #endif 693 694 if (vec == -1) { 695 printf("vme: spurious interrupt: "); 696 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 697 *((int*)ICR_SI_PEND), 698 ihp->sc->sc_reg->vmebus_afsr, 699 ihp->sc->sc_reg->vmebus_afar); 700 return 1; /* XXX - pretend we handled it, for now */ 701 } 702 703 for (; ihp; ihp = ihp->next) 704 if (ihp->vec == vec && ihp->ih.ih_fun) 705 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 706 return (i); 707 } 708 #endif 709 710 int 711 sparc_vme_intr_map(cookie, vec, pri, ihp) 712 void *cookie; 713 int vec; 714 int pri; 715 vme_intr_handle_t *ihp; 716 { 717 struct sparc_vme_intr_handle *ih; 718 719 ih = (vme_intr_handle_t) 720 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 721 ih->pri = pri; 722 ih->vec = vec; 723 ih->sc = cookie;/*XXX*/ 724 *ihp = ih; 725 return (0); 726 } 727 728 void * 729 sparc_vme_intr_establish(cookie, vih, func, arg) 730 void *cookie; 731 vme_intr_handle_t vih; 732 int (*func) __P((void *)); 733 void *arg; 734 { 735 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 736 struct sparc_vme_intr_handle *svih = 737 (struct sparc_vme_intr_handle *)vih; 738 struct intrhand *ih; 739 int level; 740 741 /* Translate VME priority to processor IPL */ 742 level = vme_ipl_to_pil[svih->pri]; 743 744 svih->ih.ih_fun = func; 745 svih->ih.ih_arg = arg; 746 svih->next = NULL; 747 748 /* ensure the interrupt subsystem will call us at this level */ 749 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 750 if (ih->ih_fun == sc->sc_vmeintr) 751 break; 752 753 if (ih == NULL) { 754 ih = (struct intrhand *) 755 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 756 if (ih == NULL) 757 panic("vme_addirq"); 758 bzero(ih, sizeof *ih); 759 ih->ih_fun = sc->sc_vmeintr; 760 ih->ih_arg = vih; 761 intr_establish(level, ih); 762 } else { 763 svih->next = (vme_intr_handle_t)ih->ih_arg; 764 ih->ih_arg = vih; 765 } 766 return (NULL); 767 } 768 769 void 770 sparc_vme_unmap(cookie) 771 void * cookie; 772 { 773 /* Not implemented */ 774 panic("sparc_vme_unmap"); 775 } 776 777 void 778 sparc_vme_intr_disestablish(cookie, a) 779 void *cookie; 780 void *a; 781 { 782 /* Not implemented */ 783 panic("sparc_vme_intr_disestablish"); 784 } 785 786 787 788 /* 789 * VME DMA functions. 790 */ 791 792 #if defined(SUN4) 793 int 794 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 795 bus_dma_tag_t t; 796 bus_dmamap_t map; 797 void *buf; 798 bus_size_t buflen; 799 struct proc *p; 800 int flags; 801 { 802 bus_addr_t dvmaddr; 803 bus_size_t sgsize; 804 vaddr_t vaddr; 805 pmap_t pmap; 806 int pagesz = PAGE_SIZE; 807 int error; 808 809 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 810 map->_dm_boundary, 811 (flags & BUS_DMA_NOWAIT) == 0 812 ? EX_WAITOK 813 : EX_NOWAIT, 814 (u_long *)&dvmaddr); 815 if (error != 0) 816 return (error); 817 818 vaddr = (vaddr_t)buf; 819 map->dm_mapsize = buflen; 820 map->dm_nsegs = 1; 821 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 822 map->dm_segs[0].ds_len = buflen; 823 824 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 825 826 for (; buflen > 0; ) { 827 paddr_t pa; 828 /* 829 * Get the physical address for this page. 830 */ 831 pa = pmap_extract(pmap, vaddr); 832 833 /* 834 * Compute the segment size, and adjust counts. 835 */ 836 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 837 if (buflen < sgsize) 838 sgsize = buflen; 839 840 #ifdef notyet 841 if (have_iocache) 842 curaddr |= PG_IOC; 843 #endif 844 pmap_enter(pmap_kernel(), dvmaddr, 845 (pa & ~(pagesz-1)) | PMAP_NC, 846 VM_PROT_READ|VM_PROT_WRITE, 1); 847 848 dvmaddr += pagesz; 849 vaddr += sgsize; 850 buflen -= sgsize; 851 } 852 853 /* Adjust DVMA address to VME view */ 854 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 855 return (0); 856 } 857 858 void 859 sparc_vme4_dmamap_unload(t, map) 860 bus_dma_tag_t t; 861 bus_dmamap_t map; 862 { 863 bus_addr_t addr; 864 bus_size_t len; 865 866 /* Go from VME to CPU view */ 867 map->dm_segs[0].ds_addr += VME4_DVMA_BASE; 868 869 addr = map->dm_segs[0].ds_addr & ~PGOFSET; 870 len = round_page(map->dm_segs[0].ds_len); 871 872 /* Remove double-mapping in DVMA space */ 873 pmap_remove(pmap_kernel(), addr, addr + len); 874 875 /* Release DVMA space */ 876 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 877 printf("warning: %ld of DVMA space lost\n", len); 878 879 /* Mark the mappings as invalid. */ 880 map->dm_mapsize = 0; 881 map->dm_nsegs = 0; 882 } 883 884 int 885 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 886 bus_dma_tag_t t; 887 bus_size_t size, alignment, boundary; 888 bus_dma_segment_t *segs; 889 int nsegs; 890 int *rsegs; 891 int flags; 892 { 893 bus_addr_t dvmaddr; 894 struct pglist *mlist; 895 vm_page_t m; 896 paddr_t pa; 897 int error; 898 899 size = round_page(size); 900 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 901 segs, nsegs, rsegs, flags); 902 if (error != 0) 903 return (error); 904 905 if (extent_alloc(vme_dvmamap, size, alignment, boundary, 906 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 907 (u_long *)&dvmaddr) != 0) 908 return (ENOMEM); 909 910 /* 911 * Compute the location, size, and number of segments actually 912 * returned by the VM code. 913 */ 914 segs[0].ds_addr = dvmaddr - VME4_DVMA_BASE; 915 segs[0].ds_len = size; 916 *rsegs = 1; 917 918 /* Map memory into DVMA space */ 919 mlist = segs[0]._ds_mlist; 920 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 921 pa = VM_PAGE_TO_PHYS(m); 922 923 #ifdef notyet 924 if (have_iocache) 925 pa |= PG_IOC; 926 #endif 927 pmap_enter(pmap_kernel(), dvmaddr, pa | PMAP_NC, 928 VM_PROT_READ|VM_PROT_WRITE, 1); 929 dvmaddr += PAGE_SIZE; 930 } 931 932 return (0); 933 } 934 935 void 936 sparc_vme4_dmamem_free(t, segs, nsegs) 937 bus_dma_tag_t t; 938 bus_dma_segment_t *segs; 939 int nsegs; 940 { 941 bus_addr_t addr; 942 bus_size_t len; 943 944 addr = segs[0].ds_addr + VME4_DVMA_BASE; 945 len = round_page(segs[0].ds_len); 946 947 /* Remove DVMA kernel map */ 948 pmap_remove(pmap_kernel(), addr, addr + len); 949 950 /* Release DVMA address range */ 951 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 952 printf("warning: %ld of DVMA space lost\n", len); 953 954 /* 955 * Return the list of pages back to the VM system. 956 */ 957 _bus_dmamem_free_common(t, segs, nsegs); 958 } 959 960 void 961 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 962 bus_dma_tag_t t; 963 bus_dmamap_t map; 964 bus_addr_t offset; 965 bus_size_t len; 966 int ops; 967 { 968 969 /* 970 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 971 * Currently the cache is flushed in bus_dma_load()... 972 */ 973 } 974 #endif /* SUN4 */ 975 976 #if defined(SUN4M) 977 static int 978 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 979 bus_dma_tag_t t; 980 bus_size_t size; 981 int nsegments; 982 bus_size_t maxsegsz; 983 bus_size_t boundary; 984 int flags; 985 bus_dmamap_t *dmamp; 986 { 987 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 988 int error; 989 990 /* XXX - todo: allocate DVMA addresses from assigned ranges: 991 upper 8MB for A32 space; upper 1MB for A24 space */ 992 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 993 boundary, flags, dmamp); 994 if (error != 0) 995 return (error); 996 997 #if 0 998 /* VME DVMA addresses must always be 8K aligned */ 999 (*dmamp)->_dm_align = 8192; 1000 #endif 1001 1002 return (0); 1003 } 1004 1005 int 1006 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1007 bus_dma_tag_t t; 1008 bus_dmamap_t map; 1009 void *buf; 1010 bus_size_t buflen; 1011 struct proc *p; 1012 int flags; 1013 { 1014 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1015 volatile u_int32_t *ioctags; 1016 int error; 1017 1018 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 1019 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1020 if (error != 0) 1021 return (error); 1022 1023 /* allocate IO cache entries for this range */ 1024 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1025 for (;buflen > 0;) { 1026 *ioctags = VME_IOC_IC | VME_IOC_W; 1027 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1028 buflen -= VME_IOC_PAGESZ; 1029 } 1030 return (0); 1031 } 1032 1033 1034 void 1035 sparc_vme4m_dmamap_unload(t, map) 1036 bus_dma_tag_t t; 1037 bus_dmamap_t map; 1038 { 1039 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1040 volatile u_int32_t *flushregs; 1041 int len; 1042 1043 /* Flush VME IO cache */ 1044 len = map->dm_segs[0].ds_len; 1045 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1046 for (;len > 0;) { 1047 *flushregs = 0; 1048 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1049 len -= VME_IOC_PAGESZ; 1050 } 1051 /* Read a tag to synchronize the IOC flushes */ 1052 (*sc->sc_ioctags); 1053 1054 bus_dmamap_unload(sc->sc_dmatag, map); 1055 } 1056 1057 int 1058 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 1059 bus_dma_tag_t t; 1060 bus_size_t size, alignmnt, boundary; 1061 bus_dma_segment_t *segs; 1062 int nsegs; 1063 int *rsegs; 1064 int flags; 1065 { 1066 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1067 int error; 1068 1069 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 1070 segs, nsegs, rsegs, flags); 1071 if (error != 0) 1072 return (error); 1073 1074 return (0); 1075 } 1076 1077 void 1078 sparc_vme4m_dmamem_free(t, segs, nsegs) 1079 bus_dma_tag_t t; 1080 bus_dma_segment_t *segs; 1081 int nsegs; 1082 { 1083 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1084 1085 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 1086 } 1087 1088 void 1089 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1090 bus_dma_tag_t t; 1091 bus_dmamap_t map; 1092 bus_addr_t offset; 1093 bus_size_t len; 1094 int ops; 1095 { 1096 1097 /* 1098 * XXX Should perform cache flushes as necessary. 1099 */ 1100 } 1101 #endif /* SUN4M */ 1102 1103 int 1104 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1105 bus_dma_tag_t t; 1106 bus_dma_segment_t *segs; 1107 int nsegs; 1108 size_t size; 1109 caddr_t *kvap; 1110 int flags; 1111 { 1112 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1113 1114 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1115 } 1116
Indexes created Mon Sep 22 21:09:42 GMT 2025