vme_machdep.c revision 1.14
1 /* $NetBSD: vme_machdep.c,v 1.14 1998/09/19 16:45:43 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <sys/proc.h> 46 #include <sys/user.h> 47 #include <sys/syslog.h> 48 49 #include <vm/vm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <sparc/sparc/iommuvar.h> 54 #include <machine/autoconf.h> 55 #include <machine/pmap.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmevar.h> 61 62 #include <sparc/sparc/asm.h> 63 #include <sparc/sparc/vaddrs.h> 64 #include <sparc/sparc/cpuvar.h> 65 #include <sparc/dev/vmereg.h> 66 67 struct vmebus_softc { 68 struct device sc_dev; /* base device */ 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 struct vmebusreg *sc_reg; /* VME control registers */ 72 struct vmebusvec *sc_vec; /* VME interrupt vector */ 73 struct rom_range *sc_range; /* ROM range property */ 74 int sc_nrange; 75 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 76 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 77 int (*sc_vmeintr) __P((void *)); 78 struct bootpath *sc_bp; 79 }; 80 struct vmebus_softc *vmebus_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 #endif 93 static int sparc_vme_error __P((void)); 94 95 96 static int sparc_vme_probe __P((void *, bus_space_tag_t, vme_addr_t, 97 size_t, vme_size_t, vme_mod_t, 98 int (*) __P((void *, void *)), void *)); 99 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_mod_t, 100 bus_space_tag_t, bus_space_handle_t *)); 101 static void sparc_vme_unmap __P((void *)); 102 static int sparc_vme_mmap_cookie __P((void *, vme_addr_t, vme_mod_t, 103 bus_space_tag_t, bus_space_handle_t *)); 104 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 105 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, 106 int (*) __P((void *)), void *)); 107 static void sparc_vme_intr_disestablish __P((void *, void *)); 108 109 static int vmebus_translate __P((struct vmebus_softc *, vme_mod_t, 110 vme_addr_t, bus_type_t *, bus_addr_t *)); 111 static void sparc_vme_bus_establish __P((void *, struct device *)); 112 #if defined(SUN4M) 113 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 114 bus_size_t, bus_size_t, int)); 115 116 #endif 117 118 /* 119 * DMA functions. 120 */ 121 #if defined(SUN4) 122 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 123 bus_size_t, struct proc *, int)); 124 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 125 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 126 bus_addr_t, bus_size_t, int)); 127 128 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 129 bus_size_t, bus_size_t, bus_dma_segment_t *, 130 int, int *, int)); 131 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 132 bus_dma_segment_t *, int)); 133 #endif 134 135 #if defined(SUN4M) 136 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 137 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 138 139 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 140 bus_size_t, struct proc *, int)); 141 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 142 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 143 bus_addr_t, bus_size_t, int)); 144 145 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 146 bus_size_t, bus_size_t, bus_dma_segment_t *, 147 int, int *, int)); 148 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 149 bus_dma_segment_t *, int)); 150 #endif 151 152 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 153 int, size_t, caddr_t *, int)); 154 #if 0 155 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 156 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 157 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 158 bus_dma_segment_t *, int, int, int, int)); 159 #endif 160 161 struct cfattach vme_mainbus_ca = { 162 sizeof(struct vmebus_softc), vmematch_mainbus, vmeattach_mainbus 163 }; 164 165 struct cfattach vme_iommu_ca = { 166 sizeof(struct vmebus_softc), vmematch_iommu, vmeattach_iommu 167 }; 168 169 int (*vmeerr_handler) __P((void)); 170 171 /* If the PROM does not provide the `ranges' property, we make up our own */ 172 struct rom_range vmebus_translations[] = { 173 #define _DS (VMEMOD_D|VMEMOD_S) 174 { VMEMOD_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 175 { VMEMOD_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 176 { VMEMOD_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 177 { VMEMOD_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 178 { VMEMOD_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 179 { VMEMOD_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 180 #undef _DS 181 }; 182 183 /* 184 * DMA on sun4 VME devices use the last MB of virtual space, which 185 * is mapped by hardware onto the first MB of VME space. 186 */ 187 struct extent *vme_dvmamap; 188 189 struct sparc_bus_space_tag sparc_vme_bus_tag = { 190 NULL, /* cookie */ 191 NULL, /* parent bus tag */ 192 NULL, /* bus_map */ 193 NULL, /* bus_unmap */ 194 NULL, /* bus_subregion */ 195 NULL /* barrier */ 196 }; 197 198 struct vme_chipset_tag sparc_vme_chipset_tag = { 199 NULL, 200 sparc_vme_probe, 201 sparc_vme_map, 202 sparc_vme_unmap, 203 sparc_vme_mmap_cookie, 204 sparc_vme_intr_map, 205 sparc_vme_intr_establish, 206 sparc_vme_intr_disestablish, 207 sparc_vme_bus_establish 208 }; 209 210 211 #if defined(SUN4) 212 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 213 NULL, /* cookie */ 214 _bus_dmamap_create, 215 _bus_dmamap_destroy, 216 sparc_vme4_dmamap_load, 217 _bus_dmamap_load_mbuf, 218 _bus_dmamap_load_uio, 219 _bus_dmamap_load_raw, 220 sparc_vme4_dmamap_unload, 221 sparc_vme4_dmamap_sync, 222 223 sparc_vme4_dmamem_alloc, 224 sparc_vme4_dmamem_free, 225 sparc_vme_dmamem_map, 226 _bus_dmamem_unmap, 227 _bus_dmamem_mmap 228 }; 229 #endif 230 231 #if defined(SUN4M) 232 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 233 NULL, /* cookie */ 234 sparc_vme4m_dmamap_create, 235 _bus_dmamap_destroy, 236 sparc_vme4m_dmamap_load, 237 _bus_dmamap_load_mbuf, 238 _bus_dmamap_load_uio, 239 _bus_dmamap_load_raw, 240 sparc_vme4m_dmamap_unload, 241 sparc_vme4m_dmamap_sync, 242 243 sparc_vme4m_dmamem_alloc, 244 sparc_vme4m_dmamem_free, 245 sparc_vme_dmamem_map, 246 _bus_dmamem_unmap, 247 _bus_dmamem_mmap 248 }; 249 #endif 250 251 252 void 253 sparc_vme_bus_establish(cookie, dev) 254 void *cookie; 255 struct device *dev; 256 { 257 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 258 struct bootpath *bp = sc->sc_bp; 259 char *name; 260 261 name = dev->dv_cfdata->cf_driver->cd_name; 262 #ifdef DEBUG 263 printf("sparc_vme_bus_establish: %s%d\n", name, dev->dv_unit); 264 #endif 265 if (bp != NULL && strcmp(bp->name, name) == 0 && 266 dev->dv_unit == bp->val[1]) { 267 bp->dev = dev; 268 #ifdef DEBUG 269 printf("sparc_vme_bus_establish: on the boot path\n"); 270 #endif 271 sc->sc_bp++; 272 bootpath_store(1, sc->sc_bp); 273 } 274 } 275 276 277 int 278 vmematch_mainbus(parent, cf, aux) 279 struct device *parent; 280 struct cfdata *cf; 281 void *aux; 282 { 283 284 if (!CPU_ISSUN4) 285 return (0); 286 287 return (1); 288 } 289 290 int 291 vmematch_iommu(parent, cf, aux) 292 struct device *parent; 293 struct cfdata *cf; 294 void *aux; 295 { 296 struct mainbus_attach_args *ma = aux; 297 298 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 299 } 300 301 302 void 303 vmeattach_mainbus(parent, self, aux) 304 struct device *parent, *self; 305 void *aux; 306 { 307 #if defined(SUN4) 308 struct mainbus_attach_args *ma = aux; 309 struct vmebus_softc *sc = (struct vmebus_softc *)self; 310 struct vme_busattach_args vba; 311 312 if (self->dv_unit > 0) { 313 printf(" unsupported\n"); 314 return; 315 } 316 317 sc->sc_bustag = ma->ma_bustag; 318 sc->sc_dmatag = ma->ma_dmatag; 319 320 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 321 sc->sc_bp = ma->ma_bp + 1; 322 bootpath_store(1, sc->sc_bp); 323 } 324 325 /* VME interrupt entry point */ 326 sc->sc_vmeintr = vmeintr4; 327 328 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 329 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 330 331 vba.vba_bustag = &sparc_vme_bus_tag; 332 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 333 vba.vba_dmatag = &sparc_vme4_dma_tag; 334 335 /* Fall back to our own `range' construction */ 336 sc->sc_range = vmebus_translations; 337 sc->sc_nrange = 338 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 339 340 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 341 M_DEVBUF, 0, 0, EX_NOWAIT); 342 if (vme_dvmamap == NULL) 343 panic("vme: unable to allocate DVMA map"); 344 345 printf("\n"); 346 (void)config_search(vmesearch, self, &vba); 347 348 bootpath_store(1, NULL); 349 #endif 350 return; 351 } 352 353 /* sun4m vmebus */ 354 void 355 vmeattach_iommu(parent, self, aux) 356 struct device *parent, *self; 357 void *aux; 358 { 359 #if defined(SUN4M) 360 struct vmebus_softc *sc = (struct vmebus_softc *)self; 361 struct iommu_attach_args *ia = aux; 362 struct vme_busattach_args vba; 363 bus_space_handle_t bh; 364 int node; 365 int cline; 366 367 if (self->dv_unit > 0) { 368 printf(" unsupported\n"); 369 return; 370 } 371 372 sc->sc_bustag = ia->iom_bustag; 373 sc->sc_dmatag = ia->iom_dmatag; 374 375 /* VME interrupt entry point */ 376 sc->sc_vmeintr = vmeintr4m; 377 378 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 379 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 380 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 381 382 vba.vba_bustag = &sparc_vme_bus_tag; 383 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 384 vba.vba_dmatag = &sparc_vme4m_dma_tag; 385 386 node = ia->iom_node; 387 388 /* 389 * Map VME control space 390 */ 391 if (ia->iom_nreg < 2) { 392 printf("%s: only %d register sets\n", self->dv_xname, 393 ia->iom_nreg); 394 return; 395 } 396 397 if (bus_space_map2(ia->iom_bustag, 398 (bus_type_t)ia->iom_reg[0].ior_iospace, 399 (bus_addr_t)ia->iom_reg[0].ior_pa, 400 (bus_size_t)ia->iom_reg[0].ior_size, 401 BUS_SPACE_MAP_LINEAR, 402 0, &bh) != 0) { 403 panic("%s: can't map vmebusreg", self->dv_xname); 404 } 405 sc->sc_reg = (struct vmebusreg *)bh; 406 407 if (bus_space_map2(ia->iom_bustag, 408 (bus_type_t)ia->iom_reg[1].ior_iospace, 409 (bus_addr_t)ia->iom_reg[1].ior_pa, 410 (bus_size_t)ia->iom_reg[1].ior_size, 411 BUS_SPACE_MAP_LINEAR, 412 0, &bh) != 0) { 413 panic("%s: can't map vmebusvec", self->dv_xname); 414 } 415 sc->sc_vec = (struct vmebusvec *)bh; 416 417 /* 418 * Map VME IO cache tags and flush control. 419 */ 420 if (bus_space_map2(ia->iom_bustag, 421 (bus_type_t)ia->iom_reg[1].ior_iospace, 422 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 423 VME_IOC_SIZE, 424 BUS_SPACE_MAP_LINEAR, 425 0, &bh) != 0) { 426 panic("%s: can't map IOC tags", self->dv_xname); 427 } 428 sc->sc_ioctags = (u_int32_t *)bh; 429 430 if (bus_space_map2(ia->iom_bustag, 431 (bus_type_t)ia->iom_reg[1].ior_iospace, 432 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 433 VME_IOC_SIZE, 434 BUS_SPACE_MAP_LINEAR, 435 0, &bh) != 0) { 436 panic("%s: can't map IOC flush registers", self->dv_xname); 437 } 438 sc->sc_iocflush = (u_int32_t *)bh; 439 440 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 441 442 /* 443 * Get "range" property. 444 */ 445 if (getprop(node, "ranges", sizeof(struct rom_range), 446 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 447 panic("%s: can't get ranges property", self->dv_xname); 448 } 449 450 vmebus_sc = sc; 451 vmeerr_handler = sparc_vme_error; 452 453 /* 454 * Invalidate all IO-cache entries. 455 */ 456 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 457 sc->sc_ioctags[--cline] = 0; 458 } 459 460 /* Enable IO-cache */ 461 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 462 463 printf(": version 0x%x\n", 464 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 465 466 (void)config_search(vmesearch, self, &vba); 467 #endif 468 } 469 470 int 471 sparc_vme_error() 472 { 473 struct vmebus_softc *sc = vmebus_sc; 474 u_int32_t afsr, afpa; 475 char bits[64]; 476 477 afsr = sc->sc_reg->vmebus_afsr, 478 afpa = sc->sc_reg->vmebus_afar; 479 printf("VME error:\n\tAFSR %s\n", 480 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 481 printf("\taddress: 0x%x%x\n", afsr, afpa); 482 return (0); 483 } 484 485 int 486 vmebus_translate(sc, mod, addr, btp, bap) 487 struct vmebus_softc *sc; 488 vme_mod_t mod; 489 vme_addr_t addr; 490 bus_type_t *btp; 491 bus_addr_t *bap; 492 { 493 int i; 494 495 for (i = 0; i < sc->sc_nrange; i++) { 496 497 if (sc->sc_range[i].cspace != mod) 498 continue; 499 500 /* We've found the connection to the parent bus */ 501 *bap = sc->sc_range[i].poffset + addr; 502 *btp = sc->sc_range[i].pspace; 503 return (0); 504 } 505 return (ENOENT); 506 } 507 508 int 509 sparc_vme_probe(cookie, tag, addr, offset, size, mod, callback, arg) 510 void *cookie; 511 bus_space_tag_t tag; 512 vme_addr_t addr; 513 size_t offset; 514 vme_size_t size; 515 int mod; 516 int (*callback) __P((void *, void *)); 517 void *arg; 518 { 519 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 520 bus_type_t iospace; 521 bus_addr_t paddr; 522 523 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 524 return (0); 525 526 return (bus_space_probe(sc->sc_bustag, iospace, paddr, size, offset, 527 0, callback, arg)); 528 } 529 530 int 531 sparc_vme_map(cookie, addr, size, mod, tag, hp) 532 void *cookie; 533 vme_addr_t addr; 534 vme_size_t size; 535 int mod; 536 bus_space_tag_t tag; 537 bus_space_handle_t *hp; 538 { 539 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 540 bus_type_t iospace; 541 bus_addr_t paddr; 542 int error; 543 544 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 545 if (error != 0) 546 return (error); 547 548 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 549 } 550 551 int 552 sparc_vme_mmap_cookie(cookie, addr, mod, tag, hp) 553 void *cookie; 554 vme_addr_t addr; 555 int mod; 556 bus_space_tag_t tag; 557 bus_space_handle_t *hp; 558 { 559 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 560 bus_type_t iospace; 561 bus_addr_t paddr; 562 int error; 563 564 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 565 if (error != 0) 566 return (error); 567 568 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 569 } 570 571 #if defined(SUN4M) 572 void 573 sparc_vme4m_barrier(t, h, offset, size, flags) 574 bus_space_tag_t t; 575 bus_space_handle_t h; 576 bus_size_t offset; 577 bus_size_t size; 578 int flags; 579 { 580 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 581 582 /* Read async fault status to flush write-buffers */ 583 (*(volatile int *)&vbp->vmebus_afsr); 584 } 585 #endif 586 587 588 589 /* 590 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 591 */ 592 static int vme_ipl_to_pil[] = { 593 0, 594 2, 595 3, 596 5, 597 7, 598 9, 599 11, 600 13 601 }; 602 603 604 /* 605 * All VME device interrupts go through vmeintr(). This function reads 606 * the VME vector from the bus, then dispatches the device interrupt 607 * handler. All handlers for devices that map to the same Processor 608 * Interrupt Level (according to the table above) are on a linked list 609 * of `sparc_vme_intr_handle' structures. The head of which is passed 610 * down as the argument to `vmeintr(void *arg)'. 611 */ 612 struct sparc_vme_intr_handle { 613 struct intrhand ih; 614 struct sparc_vme_intr_handle *next; 615 int vec; /* VME interrupt vector */ 616 int pri; /* VME interrupt priority */ 617 struct vmebus_softc *sc;/*XXX*/ 618 }; 619 620 #if defined(SUN4) 621 int 622 vmeintr4(arg) 623 void *arg; 624 { 625 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 626 int level, vec; 627 int i = 0; 628 629 level = (ihp->pri << 1) | 1; 630 631 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 632 633 if (vec == -1) { 634 printf("vme: spurious interrupt\n"); 635 return 1; /* XXX - pretend we handled it, for now */ 636 } 637 638 for (; ihp; ihp = ihp->next) 639 if (ihp->vec == vec && ihp->ih.ih_fun) 640 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 641 return (i); 642 } 643 #endif 644 645 #if defined(SUN4M) 646 int 647 vmeintr4m(arg) 648 void *arg; 649 { 650 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 651 int level, vec; 652 int i = 0; 653 654 level = (ihp->pri << 1) | 1; 655 656 #if 0 657 int pending; 658 659 /* Flush VME <=> Sbus write buffers */ 660 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 661 662 pending = *((int*)ICR_SI_PEND); 663 if ((pending & SINTR_VME(ihp->pri)) == 0) { 664 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 665 ihp->pri, pending); 666 return (0); 667 } 668 #endif 669 #if 0 670 /* Why gives this a bus timeout sometimes? */ 671 vec = ihp->sc->sc_vec->vmebusvec[level]; 672 #else 673 /* so, arrange to catch the fault... */ 674 { 675 extern struct user *proc0paddr; 676 extern int fkbyte __P((caddr_t, struct pcb *)); 677 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 678 struct pcb *xpcb; 679 u_long saveonfault; 680 int s; 681 682 s = splhigh(); 683 if (curproc == NULL) 684 xpcb = (struct pcb *)proc0paddr; 685 else 686 xpcb = &curproc->p_addr->u_pcb; 687 688 saveonfault = (u_long)xpcb->pcb_onfault; 689 vec = fkbyte(addr, xpcb); 690 xpcb->pcb_onfault = (caddr_t)saveonfault; 691 692 splx(s); 693 } 694 #endif 695 696 if (vec == -1) { 697 printf("vme: spurious interrupt: "); 698 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 699 *((int*)ICR_SI_PEND), 700 ihp->sc->sc_reg->vmebus_afsr, 701 ihp->sc->sc_reg->vmebus_afar); 702 return (1); /* XXX - pretend we handled it, for now */ 703 } 704 705 for (; ihp; ihp = ihp->next) 706 if (ihp->vec == vec && ihp->ih.ih_fun) 707 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 708 return (i); 709 } 710 #endif 711 712 int 713 sparc_vme_intr_map(cookie, vec, pri, ihp) 714 void *cookie; 715 int vec; 716 int pri; 717 vme_intr_handle_t *ihp; 718 { 719 struct sparc_vme_intr_handle *ih; 720 721 ih = (vme_intr_handle_t) 722 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 723 ih->pri = pri; 724 ih->vec = vec; 725 ih->sc = cookie;/*XXX*/ 726 *ihp = ih; 727 return (0); 728 } 729 730 void * 731 sparc_vme_intr_establish(cookie, vih, func, arg) 732 void *cookie; 733 vme_intr_handle_t vih; 734 int (*func) __P((void *)); 735 void *arg; 736 { 737 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 738 struct sparc_vme_intr_handle *svih = 739 (struct sparc_vme_intr_handle *)vih; 740 struct intrhand *ih; 741 int level; 742 743 /* Translate VME priority to processor IPL */ 744 level = vme_ipl_to_pil[svih->pri]; 745 746 svih->ih.ih_fun = func; 747 svih->ih.ih_arg = arg; 748 svih->next = NULL; 749 750 /* ensure the interrupt subsystem will call us at this level */ 751 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 752 if (ih->ih_fun == sc->sc_vmeintr) 753 break; 754 755 if (ih == NULL) { 756 ih = (struct intrhand *) 757 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 758 if (ih == NULL) 759 panic("vme_addirq"); 760 bzero(ih, sizeof *ih); 761 ih->ih_fun = sc->sc_vmeintr; 762 ih->ih_arg = vih; 763 intr_establish(level, ih); 764 } else { 765 svih->next = (vme_intr_handle_t)ih->ih_arg; 766 ih->ih_arg = vih; 767 } 768 return (NULL); 769 } 770 771 void 772 sparc_vme_unmap(cookie) 773 void * cookie; 774 { 775 /* Not implemented */ 776 panic("sparc_vme_unmap"); 777 } 778 779 void 780 sparc_vme_intr_disestablish(cookie, a) 781 void *cookie; 782 void *a; 783 { 784 /* Not implemented */ 785 panic("sparc_vme_intr_disestablish"); 786 } 787 788 789 790 /* 791 * VME DMA functions. 792 */ 793 794 #if defined(SUN4) 795 int 796 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 797 bus_dma_tag_t t; 798 bus_dmamap_t map; 799 void *buf; 800 bus_size_t buflen; 801 struct proc *p; 802 int flags; 803 { 804 bus_addr_t dvmaddr; 805 bus_size_t sgsize; 806 vaddr_t vaddr; 807 pmap_t pmap; 808 int pagesz = PAGE_SIZE; 809 int error; 810 811 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 812 map->_dm_boundary, 813 (flags & BUS_DMA_NOWAIT) == 0 814 ? EX_WAITOK 815 : EX_NOWAIT, 816 (u_long *)&dvmaddr); 817 if (error != 0) 818 return (error); 819 820 vaddr = (vaddr_t)buf; 821 map->dm_mapsize = buflen; 822 map->dm_nsegs = 1; 823 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 824 map->dm_segs[0].ds_len = buflen; 825 826 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 827 828 for (; buflen > 0; ) { 829 paddr_t pa; 830 /* 831 * Get the physical address for this page. 832 */ 833 pa = pmap_extract(pmap, vaddr); 834 835 /* 836 * Compute the segment size, and adjust counts. 837 */ 838 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 839 if (buflen < sgsize) 840 sgsize = buflen; 841 842 #ifdef notyet 843 if (have_iocache) 844 curaddr |= PG_IOC; 845 #endif 846 pmap_enter(pmap_kernel(), dvmaddr, 847 (pa & ~(pagesz-1)) | PMAP_NC, 848 VM_PROT_READ|VM_PROT_WRITE, 1); 849 850 dvmaddr += pagesz; 851 vaddr += sgsize; 852 buflen -= sgsize; 853 } 854 855 /* Adjust DVMA address to VME view */ 856 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 857 return (0); 858 } 859 860 void 861 sparc_vme4_dmamap_unload(t, map) 862 bus_dma_tag_t t; 863 bus_dmamap_t map; 864 { 865 bus_addr_t addr; 866 bus_size_t len; 867 868 /* Go from VME to CPU view */ 869 map->dm_segs[0].ds_addr += VME4_DVMA_BASE; 870 871 addr = map->dm_segs[0].ds_addr & ~PGOFSET; 872 len = round_page(map->dm_segs[0].ds_len); 873 874 /* Remove double-mapping in DVMA space */ 875 pmap_remove(pmap_kernel(), addr, addr + len); 876 877 /* Release DVMA space */ 878 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 879 printf("warning: %ld of DVMA space lost\n", len); 880 881 /* Mark the mappings as invalid. */ 882 map->dm_mapsize = 0; 883 map->dm_nsegs = 0; 884 } 885 886 int 887 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 888 bus_dma_tag_t t; 889 bus_size_t size, alignment, boundary; 890 bus_dma_segment_t *segs; 891 int nsegs; 892 int *rsegs; 893 int flags; 894 { 895 bus_addr_t dvmaddr; 896 struct pglist *mlist; 897 vm_page_t m; 898 paddr_t pa; 899 int error; 900 901 size = round_page(size); 902 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 903 segs, nsegs, rsegs, flags); 904 if (error != 0) 905 return (error); 906 907 if (extent_alloc(vme_dvmamap, size, alignment, boundary, 908 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 909 (u_long *)&dvmaddr) != 0) 910 return (ENOMEM); 911 912 /* 913 * Compute the location, size, and number of segments actually 914 * returned by the VM code. 915 */ 916 segs[0].ds_addr = dvmaddr - VME4_DVMA_BASE; 917 segs[0].ds_len = size; 918 *rsegs = 1; 919 920 /* Map memory into DVMA space */ 921 mlist = segs[0]._ds_mlist; 922 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 923 pa = VM_PAGE_TO_PHYS(m); 924 925 #ifdef notyet 926 if (have_iocache) 927 pa |= PG_IOC; 928 #endif 929 pmap_enter(pmap_kernel(), dvmaddr, pa | PMAP_NC, 930 VM_PROT_READ|VM_PROT_WRITE, 1); 931 dvmaddr += PAGE_SIZE; 932 } 933 934 return (0); 935 } 936 937 void 938 sparc_vme4_dmamem_free(t, segs, nsegs) 939 bus_dma_tag_t t; 940 bus_dma_segment_t *segs; 941 int nsegs; 942 { 943 bus_addr_t addr; 944 bus_size_t len; 945 946 addr = segs[0].ds_addr + VME4_DVMA_BASE; 947 len = round_page(segs[0].ds_len); 948 949 /* Remove DVMA kernel map */ 950 pmap_remove(pmap_kernel(), addr, addr + len); 951 952 /* Release DVMA address range */ 953 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 954 printf("warning: %ld of DVMA space lost\n", len); 955 956 /* 957 * Return the list of pages back to the VM system. 958 */ 959 _bus_dmamem_free_common(t, segs, nsegs); 960 } 961 962 void 963 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 964 bus_dma_tag_t t; 965 bus_dmamap_t map; 966 bus_addr_t offset; 967 bus_size_t len; 968 int ops; 969 { 970 971 /* 972 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 973 * Currently the cache is flushed in bus_dma_load()... 974 */ 975 } 976 #endif /* SUN4 */ 977 978 #if defined(SUN4M) 979 static int 980 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 981 bus_dma_tag_t t; 982 bus_size_t size; 983 int nsegments; 984 bus_size_t maxsegsz; 985 bus_size_t boundary; 986 int flags; 987 bus_dmamap_t *dmamp; 988 { 989 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 990 int error; 991 992 /* XXX - todo: allocate DVMA addresses from assigned ranges: 993 upper 8MB for A32 space; upper 1MB for A24 space */ 994 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 995 boundary, flags, dmamp); 996 if (error != 0) 997 return (error); 998 999 #if 0 1000 /* VME DVMA addresses must always be 8K aligned */ 1001 (*dmamp)->_dm_align = 8192; 1002 #endif 1003 1004 return (0); 1005 } 1006 1007 int 1008 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1009 bus_dma_tag_t t; 1010 bus_dmamap_t map; 1011 void *buf; 1012 bus_size_t buflen; 1013 struct proc *p; 1014 int flags; 1015 { 1016 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1017 volatile u_int32_t *ioctags; 1018 int error; 1019 1020 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 1021 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1022 if (error != 0) 1023 return (error); 1024 1025 /* allocate IO cache entries for this range */ 1026 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1027 for (;buflen > 0;) { 1028 *ioctags = VME_IOC_IC | VME_IOC_W; 1029 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1030 buflen -= VME_IOC_PAGESZ; 1031 } 1032 return (0); 1033 } 1034 1035 1036 void 1037 sparc_vme4m_dmamap_unload(t, map) 1038 bus_dma_tag_t t; 1039 bus_dmamap_t map; 1040 { 1041 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1042 volatile u_int32_t *flushregs; 1043 int len; 1044 1045 /* Flush VME IO cache */ 1046 len = map->dm_segs[0].ds_len; 1047 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1048 for (;len > 0;) { 1049 *flushregs = 0; 1050 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1051 len -= VME_IOC_PAGESZ; 1052 } 1053 /* Read a tag to synchronize the IOC flushes */ 1054 (*sc->sc_ioctags); 1055 1056 bus_dmamap_unload(sc->sc_dmatag, map); 1057 } 1058 1059 int 1060 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 1061 bus_dma_tag_t t; 1062 bus_size_t size, alignmnt, boundary; 1063 bus_dma_segment_t *segs; 1064 int nsegs; 1065 int *rsegs; 1066 int flags; 1067 { 1068 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1069 int error; 1070 1071 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 1072 segs, nsegs, rsegs, flags); 1073 if (error != 0) 1074 return (error); 1075 1076 return (0); 1077 } 1078 1079 void 1080 sparc_vme4m_dmamem_free(t, segs, nsegs) 1081 bus_dma_tag_t t; 1082 bus_dma_segment_t *segs; 1083 int nsegs; 1084 { 1085 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1086 1087 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 1088 } 1089 1090 void 1091 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1092 bus_dma_tag_t t; 1093 bus_dmamap_t map; 1094 bus_addr_t offset; 1095 bus_size_t len; 1096 int ops; 1097 { 1098 1099 /* 1100 * XXX Should perform cache flushes as necessary. 1101 */ 1102 } 1103 #endif /* SUN4M */ 1104 1105 int 1106 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1107 bus_dma_tag_t t; 1108 bus_dma_segment_t *segs; 1109 int nsegs; 1110 size_t size; 1111 caddr_t *kvap; 1112 int flags; 1113 { 1114 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1115 1116 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1117 } 1118
Indexes created Tue Sep 23 07:09:52 GMT 2025