vme_machdep.c revision 1.15
1 /* $NetBSD: vme_machdep.c,v 1.15 1999/01/15 00:26:24 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <sys/proc.h> 46 #include <sys/user.h> 47 #include <sys/syslog.h> 48 49 #include <vm/vm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <sparc/sparc/iommuvar.h> 54 #include <machine/autoconf.h> 55 #include <machine/pmap.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmevar.h> 61 62 #include <sparc/sparc/asm.h> 63 #include <sparc/sparc/vaddrs.h> 64 #include <sparc/sparc/cpuvar.h> 65 #include <sparc/dev/vmereg.h> 66 67 struct vmebus_softc { 68 struct device sc_dev; /* base device */ 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 struct vmebusreg *sc_reg; /* VME control registers */ 72 struct vmebusvec *sc_vec; /* VME interrupt vector */ 73 struct rom_range *sc_range; /* ROM range property */ 74 int sc_nrange; 75 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 76 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 77 int (*sc_vmeintr) __P((void *)); 78 struct bootpath *sc_bp; 79 }; 80 struct vmebus_softc *vmebus_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 #endif 93 static int sparc_vme_error __P((void)); 94 95 96 static int sparc_vme_probe __P((void *, bus_space_tag_t, vme_addr_t, 97 size_t, vme_size_t, vme_mod_t, 98 int (*) __P((void *, void *)), void *)); 99 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_mod_t, 100 bus_space_tag_t, bus_space_handle_t *)); 101 static void sparc_vme_unmap __P((void *)); 102 static int sparc_vme_mmap_cookie __P((void *, vme_addr_t, vme_mod_t, 103 bus_space_tag_t, bus_space_handle_t *)); 104 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 105 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, 106 int (*) __P((void *)), void *)); 107 static void sparc_vme_intr_disestablish __P((void *, void *)); 108 109 static int vmebus_translate __P((struct vmebus_softc *, vme_mod_t, 110 vme_addr_t, bus_type_t *, bus_addr_t *)); 111 static void sparc_vme_bus_establish __P((void *, struct device *)); 112 #if defined(SUN4M) 113 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 114 bus_size_t, bus_size_t, int)); 115 116 #endif 117 118 /* 119 * DMA functions. 120 */ 121 #if defined(SUN4) 122 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 123 bus_size_t, struct proc *, int)); 124 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 125 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 126 bus_addr_t, bus_size_t, int)); 127 128 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 129 bus_size_t, bus_size_t, bus_dma_segment_t *, 130 int, int *, int)); 131 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 132 bus_dma_segment_t *, int)); 133 #endif 134 135 #if defined(SUN4M) 136 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 137 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 138 139 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 140 bus_size_t, struct proc *, int)); 141 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 142 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 143 bus_addr_t, bus_size_t, int)); 144 145 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 146 bus_size_t, bus_size_t, bus_dma_segment_t *, 147 int, int *, int)); 148 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 149 bus_dma_segment_t *, int)); 150 #endif 151 152 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 153 int, size_t, caddr_t *, int)); 154 #if 0 155 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 156 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 157 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 158 bus_dma_segment_t *, int, int, int, int)); 159 #endif 160 161 struct cfattach vme_mainbus_ca = { 162 sizeof(struct vmebus_softc), vmematch_mainbus, vmeattach_mainbus 163 }; 164 165 struct cfattach vme_iommu_ca = { 166 sizeof(struct vmebus_softc), vmematch_iommu, vmeattach_iommu 167 }; 168 169 int (*vmeerr_handler) __P((void)); 170 171 /* If the PROM does not provide the `ranges' property, we make up our own */ 172 struct rom_range vmebus_translations[] = { 173 #define _DS (VMEMOD_D|VMEMOD_S) 174 { VMEMOD_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 175 { VMEMOD_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 176 { VMEMOD_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 177 { VMEMOD_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 178 { VMEMOD_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 179 { VMEMOD_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 180 #undef _DS 181 }; 182 183 /* 184 * DMA on sun4 VME devices use the last MB of virtual space, which 185 * is mapped by hardware onto the first MB of VME space. 186 */ 187 struct extent *vme_dvmamap; 188 189 struct sparc_bus_space_tag sparc_vme_bus_tag = { 190 NULL, /* cookie */ 191 NULL, /* parent bus tag */ 192 NULL, /* bus_map */ 193 NULL, /* bus_unmap */ 194 NULL, /* bus_subregion */ 195 NULL /* barrier */ 196 }; 197 198 struct vme_chipset_tag sparc_vme_chipset_tag = { 199 NULL, 200 sparc_vme_probe, 201 sparc_vme_map, 202 sparc_vme_unmap, 203 sparc_vme_mmap_cookie, 204 sparc_vme_intr_map, 205 sparc_vme_intr_establish, 206 sparc_vme_intr_disestablish, 207 sparc_vme_bus_establish 208 }; 209 210 211 #if defined(SUN4) 212 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 213 NULL, /* cookie */ 214 _bus_dmamap_create, 215 _bus_dmamap_destroy, 216 sparc_vme4_dmamap_load, 217 _bus_dmamap_load_mbuf, 218 _bus_dmamap_load_uio, 219 _bus_dmamap_load_raw, 220 sparc_vme4_dmamap_unload, 221 sparc_vme4_dmamap_sync, 222 223 sparc_vme4_dmamem_alloc, 224 sparc_vme4_dmamem_free, 225 sparc_vme_dmamem_map, 226 _bus_dmamem_unmap, 227 _bus_dmamem_mmap 228 }; 229 #endif 230 231 #if defined(SUN4M) 232 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 233 NULL, /* cookie */ 234 sparc_vme4m_dmamap_create, 235 _bus_dmamap_destroy, 236 sparc_vme4m_dmamap_load, 237 _bus_dmamap_load_mbuf, 238 _bus_dmamap_load_uio, 239 _bus_dmamap_load_raw, 240 sparc_vme4m_dmamap_unload, 241 sparc_vme4m_dmamap_sync, 242 243 sparc_vme4m_dmamem_alloc, 244 sparc_vme4m_dmamem_free, 245 sparc_vme_dmamem_map, 246 _bus_dmamem_unmap, 247 _bus_dmamem_mmap 248 }; 249 #endif 250 251 252 void 253 sparc_vme_bus_establish(cookie, dev) 254 void *cookie; 255 struct device *dev; 256 { 257 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 258 struct bootpath *bp = sc->sc_bp; 259 char *name; 260 261 name = dev->dv_cfdata->cf_driver->cd_name; 262 #ifdef DEBUG 263 printf("sparc_vme_bus_establish: %s%d\n", name, dev->dv_unit); 264 #endif 265 if (bp != NULL && strcmp(bp->name, name) == 0 && 266 dev->dv_unit == bp->val[1]) { 267 bp->dev = dev; 268 #ifdef DEBUG 269 printf("sparc_vme_bus_establish: on the boot path\n"); 270 #endif 271 sc->sc_bp++; 272 bootpath_store(1, sc->sc_bp); 273 } 274 } 275 276 277 int 278 vmematch_mainbus(parent, cf, aux) 279 struct device *parent; 280 struct cfdata *cf; 281 void *aux; 282 { 283 struct mainbus_attach_args *ma = aux; 284 285 if (!CPU_ISSUN4) 286 return (0); 287 288 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 289 } 290 291 int 292 vmematch_iommu(parent, cf, aux) 293 struct device *parent; 294 struct cfdata *cf; 295 void *aux; 296 { 297 struct iommu_attach_args *ia = aux; 298 299 return (strcmp(cf->cf_driver->cd_name, ia->iom_name) == 0); 300 } 301 302 303 void 304 vmeattach_mainbus(parent, self, aux) 305 struct device *parent, *self; 306 void *aux; 307 { 308 #if defined(SUN4) 309 struct mainbus_attach_args *ma = aux; 310 struct vmebus_softc *sc = (struct vmebus_softc *)self; 311 struct vme_busattach_args vba; 312 313 if (self->dv_unit > 0) { 314 printf(" unsupported\n"); 315 return; 316 } 317 318 sc->sc_bustag = ma->ma_bustag; 319 sc->sc_dmatag = ma->ma_dmatag; 320 321 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 322 sc->sc_bp = ma->ma_bp + 1; 323 bootpath_store(1, sc->sc_bp); 324 } 325 326 /* VME interrupt entry point */ 327 sc->sc_vmeintr = vmeintr4; 328 329 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 330 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 331 332 vba.vba_bustag = &sparc_vme_bus_tag; 333 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 334 vba.vba_dmatag = &sparc_vme4_dma_tag; 335 336 /* Fall back to our own `range' construction */ 337 sc->sc_range = vmebus_translations; 338 sc->sc_nrange = 339 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 340 341 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 342 M_DEVBUF, 0, 0, EX_NOWAIT); 343 if (vme_dvmamap == NULL) 344 panic("vme: unable to allocate DVMA map"); 345 346 printf("\n"); 347 (void)config_search(vmesearch, self, &vba); 348 349 bootpath_store(1, NULL); 350 #endif 351 return; 352 } 353 354 /* sun4m vmebus */ 355 void 356 vmeattach_iommu(parent, self, aux) 357 struct device *parent, *self; 358 void *aux; 359 { 360 #if defined(SUN4M) 361 struct vmebus_softc *sc = (struct vmebus_softc *)self; 362 struct iommu_attach_args *ia = aux; 363 struct vme_busattach_args vba; 364 bus_space_handle_t bh; 365 int node; 366 int cline; 367 368 if (self->dv_unit > 0) { 369 printf(" unsupported\n"); 370 return; 371 } 372 373 sc->sc_bustag = ia->iom_bustag; 374 sc->sc_dmatag = ia->iom_dmatag; 375 376 /* VME interrupt entry point */ 377 sc->sc_vmeintr = vmeintr4m; 378 379 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 380 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 381 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 382 383 vba.vba_bustag = &sparc_vme_bus_tag; 384 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 385 vba.vba_dmatag = &sparc_vme4m_dma_tag; 386 387 node = ia->iom_node; 388 389 /* 390 * Map VME control space 391 */ 392 if (ia->iom_nreg < 2) { 393 printf("%s: only %d register sets\n", self->dv_xname, 394 ia->iom_nreg); 395 return; 396 } 397 398 if (bus_space_map2(ia->iom_bustag, 399 (bus_type_t)ia->iom_reg[0].ior_iospace, 400 (bus_addr_t)ia->iom_reg[0].ior_pa, 401 (bus_size_t)ia->iom_reg[0].ior_size, 402 BUS_SPACE_MAP_LINEAR, 403 0, &bh) != 0) { 404 panic("%s: can't map vmebusreg", self->dv_xname); 405 } 406 sc->sc_reg = (struct vmebusreg *)bh; 407 408 if (bus_space_map2(ia->iom_bustag, 409 (bus_type_t)ia->iom_reg[1].ior_iospace, 410 (bus_addr_t)ia->iom_reg[1].ior_pa, 411 (bus_size_t)ia->iom_reg[1].ior_size, 412 BUS_SPACE_MAP_LINEAR, 413 0, &bh) != 0) { 414 panic("%s: can't map vmebusvec", self->dv_xname); 415 } 416 sc->sc_vec = (struct vmebusvec *)bh; 417 418 /* 419 * Map VME IO cache tags and flush control. 420 */ 421 if (bus_space_map2(ia->iom_bustag, 422 (bus_type_t)ia->iom_reg[1].ior_iospace, 423 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 424 VME_IOC_SIZE, 425 BUS_SPACE_MAP_LINEAR, 426 0, &bh) != 0) { 427 panic("%s: can't map IOC tags", self->dv_xname); 428 } 429 sc->sc_ioctags = (u_int32_t *)bh; 430 431 if (bus_space_map2(ia->iom_bustag, 432 (bus_type_t)ia->iom_reg[1].ior_iospace, 433 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 434 VME_IOC_SIZE, 435 BUS_SPACE_MAP_LINEAR, 436 0, &bh) != 0) { 437 panic("%s: can't map IOC flush registers", self->dv_xname); 438 } 439 sc->sc_iocflush = (u_int32_t *)bh; 440 441 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 442 443 /* 444 * Get "range" property. 445 */ 446 if (getprop(node, "ranges", sizeof(struct rom_range), 447 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 448 panic("%s: can't get ranges property", self->dv_xname); 449 } 450 451 vmebus_sc = sc; 452 vmeerr_handler = sparc_vme_error; 453 454 /* 455 * Invalidate all IO-cache entries. 456 */ 457 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 458 sc->sc_ioctags[--cline] = 0; 459 } 460 461 /* Enable IO-cache */ 462 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 463 464 printf(": version 0x%x\n", 465 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 466 467 (void)config_search(vmesearch, self, &vba); 468 #endif 469 } 470 471 int 472 sparc_vme_error() 473 { 474 struct vmebus_softc *sc = vmebus_sc; 475 u_int32_t afsr, afpa; 476 char bits[64]; 477 478 afsr = sc->sc_reg->vmebus_afsr, 479 afpa = sc->sc_reg->vmebus_afar; 480 printf("VME error:\n\tAFSR %s\n", 481 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 482 printf("\taddress: 0x%x%x\n", afsr, afpa); 483 return (0); 484 } 485 486 int 487 vmebus_translate(sc, mod, addr, btp, bap) 488 struct vmebus_softc *sc; 489 vme_mod_t mod; 490 vme_addr_t addr; 491 bus_type_t *btp; 492 bus_addr_t *bap; 493 { 494 int i; 495 496 for (i = 0; i < sc->sc_nrange; i++) { 497 498 if (sc->sc_range[i].cspace != mod) 499 continue; 500 501 /* We've found the connection to the parent bus */ 502 *bap = sc->sc_range[i].poffset + addr; 503 *btp = sc->sc_range[i].pspace; 504 return (0); 505 } 506 return (ENOENT); 507 } 508 509 int 510 sparc_vme_probe(cookie, tag, addr, offset, size, mod, callback, arg) 511 void *cookie; 512 bus_space_tag_t tag; 513 vme_addr_t addr; 514 size_t offset; 515 vme_size_t size; 516 int mod; 517 int (*callback) __P((void *, void *)); 518 void *arg; 519 { 520 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 521 bus_type_t iospace; 522 bus_addr_t paddr; 523 524 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 525 return (0); 526 527 return (bus_space_probe(sc->sc_bustag, iospace, paddr, size, offset, 528 0, callback, arg)); 529 } 530 531 int 532 sparc_vme_map(cookie, addr, size, mod, tag, hp) 533 void *cookie; 534 vme_addr_t addr; 535 vme_size_t size; 536 int mod; 537 bus_space_tag_t tag; 538 bus_space_handle_t *hp; 539 { 540 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 541 bus_type_t iospace; 542 bus_addr_t paddr; 543 int error; 544 545 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 546 if (error != 0) 547 return (error); 548 549 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 550 } 551 552 int 553 sparc_vme_mmap_cookie(cookie, addr, mod, tag, hp) 554 void *cookie; 555 vme_addr_t addr; 556 int mod; 557 bus_space_tag_t tag; 558 bus_space_handle_t *hp; 559 { 560 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 561 bus_type_t iospace; 562 bus_addr_t paddr; 563 int error; 564 565 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 566 if (error != 0) 567 return (error); 568 569 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 570 } 571 572 #if defined(SUN4M) 573 void 574 sparc_vme4m_barrier(t, h, offset, size, flags) 575 bus_space_tag_t t; 576 bus_space_handle_t h; 577 bus_size_t offset; 578 bus_size_t size; 579 int flags; 580 { 581 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 582 583 /* Read async fault status to flush write-buffers */ 584 (*(volatile int *)&vbp->vmebus_afsr); 585 } 586 #endif 587 588 589 590 /* 591 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 592 */ 593 static int vme_ipl_to_pil[] = { 594 0, 595 2, 596 3, 597 5, 598 7, 599 9, 600 11, 601 13 602 }; 603 604 605 /* 606 * All VME device interrupts go through vmeintr(). This function reads 607 * the VME vector from the bus, then dispatches the device interrupt 608 * handler. All handlers for devices that map to the same Processor 609 * Interrupt Level (according to the table above) are on a linked list 610 * of `sparc_vme_intr_handle' structures. The head of which is passed 611 * down as the argument to `vmeintr(void *arg)'. 612 */ 613 struct sparc_vme_intr_handle { 614 struct intrhand ih; 615 struct sparc_vme_intr_handle *next; 616 int vec; /* VME interrupt vector */ 617 int pri; /* VME interrupt priority */ 618 struct vmebus_softc *sc;/*XXX*/ 619 }; 620 621 #if defined(SUN4) 622 int 623 vmeintr4(arg) 624 void *arg; 625 { 626 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 627 int level, vec; 628 int i = 0; 629 630 level = (ihp->pri << 1) | 1; 631 632 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 633 634 if (vec == -1) { 635 printf("vme: spurious interrupt\n"); 636 return 1; /* XXX - pretend we handled it, for now */ 637 } 638 639 for (; ihp; ihp = ihp->next) 640 if (ihp->vec == vec && ihp->ih.ih_fun) 641 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 642 return (i); 643 } 644 #endif 645 646 #if defined(SUN4M) 647 int 648 vmeintr4m(arg) 649 void *arg; 650 { 651 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 652 int level, vec; 653 int i = 0; 654 655 level = (ihp->pri << 1) | 1; 656 657 #if 0 658 int pending; 659 660 /* Flush VME <=> Sbus write buffers */ 661 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 662 663 pending = *((int*)ICR_SI_PEND); 664 if ((pending & SINTR_VME(ihp->pri)) == 0) { 665 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 666 ihp->pri, pending); 667 return (0); 668 } 669 #endif 670 #if 0 671 /* Why gives this a bus timeout sometimes? */ 672 vec = ihp->sc->sc_vec->vmebusvec[level]; 673 #else 674 /* so, arrange to catch the fault... */ 675 { 676 extern struct user *proc0paddr; 677 extern int fkbyte __P((caddr_t, struct pcb *)); 678 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 679 struct pcb *xpcb; 680 u_long saveonfault; 681 int s; 682 683 s = splhigh(); 684 if (curproc == NULL) 685 xpcb = (struct pcb *)proc0paddr; 686 else 687 xpcb = &curproc->p_addr->u_pcb; 688 689 saveonfault = (u_long)xpcb->pcb_onfault; 690 vec = fkbyte(addr, xpcb); 691 xpcb->pcb_onfault = (caddr_t)saveonfault; 692 693 splx(s); 694 } 695 #endif 696 697 if (vec == -1) { 698 printf("vme: spurious interrupt: "); 699 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 700 *((int*)ICR_SI_PEND), 701 ihp->sc->sc_reg->vmebus_afsr, 702 ihp->sc->sc_reg->vmebus_afar); 703 return (1); /* XXX - pretend we handled it, for now */ 704 } 705 706 for (; ihp; ihp = ihp->next) 707 if (ihp->vec == vec && ihp->ih.ih_fun) 708 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 709 return (i); 710 } 711 #endif 712 713 int 714 sparc_vme_intr_map(cookie, vec, pri, ihp) 715 void *cookie; 716 int vec; 717 int pri; 718 vme_intr_handle_t *ihp; 719 { 720 struct sparc_vme_intr_handle *ih; 721 722 ih = (vme_intr_handle_t) 723 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 724 ih->pri = pri; 725 ih->vec = vec; 726 ih->sc = cookie;/*XXX*/ 727 *ihp = ih; 728 return (0); 729 } 730 731 void * 732 sparc_vme_intr_establish(cookie, vih, func, arg) 733 void *cookie; 734 vme_intr_handle_t vih; 735 int (*func) __P((void *)); 736 void *arg; 737 { 738 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 739 struct sparc_vme_intr_handle *svih = 740 (struct sparc_vme_intr_handle *)vih; 741 struct intrhand *ih; 742 int level; 743 744 /* Translate VME priority to processor IPL */ 745 level = vme_ipl_to_pil[svih->pri]; 746 747 svih->ih.ih_fun = func; 748 svih->ih.ih_arg = arg; 749 svih->next = NULL; 750 751 /* ensure the interrupt subsystem will call us at this level */ 752 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 753 if (ih->ih_fun == sc->sc_vmeintr) 754 break; 755 756 if (ih == NULL) { 757 ih = (struct intrhand *) 758 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 759 if (ih == NULL) 760 panic("vme_addirq"); 761 bzero(ih, sizeof *ih); 762 ih->ih_fun = sc->sc_vmeintr; 763 ih->ih_arg = vih; 764 intr_establish(level, ih); 765 } else { 766 svih->next = (vme_intr_handle_t)ih->ih_arg; 767 ih->ih_arg = vih; 768 } 769 return (NULL); 770 } 771 772 void 773 sparc_vme_unmap(cookie) 774 void * cookie; 775 { 776 /* Not implemented */ 777 panic("sparc_vme_unmap"); 778 } 779 780 void 781 sparc_vme_intr_disestablish(cookie, a) 782 void *cookie; 783 void *a; 784 { 785 /* Not implemented */ 786 panic("sparc_vme_intr_disestablish"); 787 } 788 789 790 791 /* 792 * VME DMA functions. 793 */ 794 795 #if defined(SUN4) 796 int 797 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 798 bus_dma_tag_t t; 799 bus_dmamap_t map; 800 void *buf; 801 bus_size_t buflen; 802 struct proc *p; 803 int flags; 804 { 805 bus_addr_t dvmaddr; 806 bus_size_t sgsize; 807 vaddr_t vaddr; 808 pmap_t pmap; 809 int pagesz = PAGE_SIZE; 810 int error; 811 812 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 813 map->_dm_boundary, 814 (flags & BUS_DMA_NOWAIT) == 0 815 ? EX_WAITOK 816 : EX_NOWAIT, 817 (u_long *)&dvmaddr); 818 if (error != 0) 819 return (error); 820 821 vaddr = (vaddr_t)buf; 822 map->dm_mapsize = buflen; 823 map->dm_nsegs = 1; 824 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 825 map->dm_segs[0].ds_len = buflen; 826 827 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 828 829 for (; buflen > 0; ) { 830 paddr_t pa; 831 /* 832 * Get the physical address for this page. 833 */ 834 pa = pmap_extract(pmap, vaddr); 835 836 /* 837 * Compute the segment size, and adjust counts. 838 */ 839 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 840 if (buflen < sgsize) 841 sgsize = buflen; 842 843 #ifdef notyet 844 if (have_iocache) 845 curaddr |= PG_IOC; 846 #endif 847 pmap_enter(pmap_kernel(), dvmaddr, 848 (pa & ~(pagesz-1)) | PMAP_NC, 849 VM_PROT_READ|VM_PROT_WRITE, 1); 850 851 dvmaddr += pagesz; 852 vaddr += sgsize; 853 buflen -= sgsize; 854 } 855 856 /* Adjust DVMA address to VME view */ 857 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 858 return (0); 859 } 860 861 void 862 sparc_vme4_dmamap_unload(t, map) 863 bus_dma_tag_t t; 864 bus_dmamap_t map; 865 { 866 bus_addr_t addr; 867 bus_size_t len; 868 869 /* Go from VME to CPU view */ 870 map->dm_segs[0].ds_addr += VME4_DVMA_BASE; 871 872 addr = map->dm_segs[0].ds_addr & ~PGOFSET; 873 len = round_page(map->dm_segs[0].ds_len); 874 875 /* Remove double-mapping in DVMA space */ 876 pmap_remove(pmap_kernel(), addr, addr + len); 877 878 /* Release DVMA space */ 879 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 880 printf("warning: %ld of DVMA space lost\n", len); 881 882 /* Mark the mappings as invalid. */ 883 map->dm_mapsize = 0; 884 map->dm_nsegs = 0; 885 } 886 887 int 888 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 889 bus_dma_tag_t t; 890 bus_size_t size, alignment, boundary; 891 bus_dma_segment_t *segs; 892 int nsegs; 893 int *rsegs; 894 int flags; 895 { 896 bus_addr_t dvmaddr; 897 struct pglist *mlist; 898 vm_page_t m; 899 paddr_t pa; 900 int error; 901 902 size = round_page(size); 903 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 904 segs, nsegs, rsegs, flags); 905 if (error != 0) 906 return (error); 907 908 if (extent_alloc(vme_dvmamap, size, alignment, boundary, 909 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 910 (u_long *)&dvmaddr) != 0) 911 return (ENOMEM); 912 913 /* 914 * Compute the location, size, and number of segments actually 915 * returned by the VM code. 916 */ 917 segs[0].ds_addr = dvmaddr - VME4_DVMA_BASE; 918 segs[0].ds_len = size; 919 *rsegs = 1; 920 921 /* Map memory into DVMA space */ 922 mlist = segs[0]._ds_mlist; 923 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 924 pa = VM_PAGE_TO_PHYS(m); 925 926 #ifdef notyet 927 if (have_iocache) 928 pa |= PG_IOC; 929 #endif 930 pmap_enter(pmap_kernel(), dvmaddr, pa | PMAP_NC, 931 VM_PROT_READ|VM_PROT_WRITE, 1); 932 dvmaddr += PAGE_SIZE; 933 } 934 935 return (0); 936 } 937 938 void 939 sparc_vme4_dmamem_free(t, segs, nsegs) 940 bus_dma_tag_t t; 941 bus_dma_segment_t *segs; 942 int nsegs; 943 { 944 bus_addr_t addr; 945 bus_size_t len; 946 947 addr = segs[0].ds_addr + VME4_DVMA_BASE; 948 len = round_page(segs[0].ds_len); 949 950 /* Remove DVMA kernel map */ 951 pmap_remove(pmap_kernel(), addr, addr + len); 952 953 /* Release DVMA address range */ 954 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 955 printf("warning: %ld of DVMA space lost\n", len); 956 957 /* 958 * Return the list of pages back to the VM system. 959 */ 960 _bus_dmamem_free_common(t, segs, nsegs); 961 } 962 963 void 964 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 965 bus_dma_tag_t t; 966 bus_dmamap_t map; 967 bus_addr_t offset; 968 bus_size_t len; 969 int ops; 970 { 971 972 /* 973 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 974 * Currently the cache is flushed in bus_dma_load()... 975 */ 976 } 977 #endif /* SUN4 */ 978 979 #if defined(SUN4M) 980 static int 981 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 982 bus_dma_tag_t t; 983 bus_size_t size; 984 int nsegments; 985 bus_size_t maxsegsz; 986 bus_size_t boundary; 987 int flags; 988 bus_dmamap_t *dmamp; 989 { 990 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 991 int error; 992 993 /* XXX - todo: allocate DVMA addresses from assigned ranges: 994 upper 8MB for A32 space; upper 1MB for A24 space */ 995 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 996 boundary, flags, dmamp); 997 if (error != 0) 998 return (error); 999 1000 #if 0 1001 /* VME DVMA addresses must always be 8K aligned */ 1002 (*dmamp)->_dm_align = 8192; 1003 #endif 1004 1005 return (0); 1006 } 1007 1008 int 1009 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1010 bus_dma_tag_t t; 1011 bus_dmamap_t map; 1012 void *buf; 1013 bus_size_t buflen; 1014 struct proc *p; 1015 int flags; 1016 { 1017 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1018 volatile u_int32_t *ioctags; 1019 int error; 1020 1021 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 1022 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1023 if (error != 0) 1024 return (error); 1025 1026 /* allocate IO cache entries for this range */ 1027 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1028 for (;buflen > 0;) { 1029 *ioctags = VME_IOC_IC | VME_IOC_W; 1030 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1031 buflen -= VME_IOC_PAGESZ; 1032 } 1033 return (0); 1034 } 1035 1036 1037 void 1038 sparc_vme4m_dmamap_unload(t, map) 1039 bus_dma_tag_t t; 1040 bus_dmamap_t map; 1041 { 1042 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1043 volatile u_int32_t *flushregs; 1044 int len; 1045 1046 /* Flush VME IO cache */ 1047 len = map->dm_segs[0].ds_len; 1048 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1049 for (;len > 0;) { 1050 *flushregs = 0; 1051 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1052 len -= VME_IOC_PAGESZ; 1053 } 1054 /* Read a tag to synchronize the IOC flushes */ 1055 (*sc->sc_ioctags); 1056 1057 bus_dmamap_unload(sc->sc_dmatag, map); 1058 } 1059 1060 int 1061 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 1062 bus_dma_tag_t t; 1063 bus_size_t size, alignmnt, boundary; 1064 bus_dma_segment_t *segs; 1065 int nsegs; 1066 int *rsegs; 1067 int flags; 1068 { 1069 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1070 int error; 1071 1072 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 1073 segs, nsegs, rsegs, flags); 1074 if (error != 0) 1075 return (error); 1076 1077 return (0); 1078 } 1079 1080 void 1081 sparc_vme4m_dmamem_free(t, segs, nsegs) 1082 bus_dma_tag_t t; 1083 bus_dma_segment_t *segs; 1084 int nsegs; 1085 { 1086 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1087 1088 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 1089 } 1090 1091 void 1092 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1093 bus_dma_tag_t t; 1094 bus_dmamap_t map; 1095 bus_addr_t offset; 1096 bus_size_t len; 1097 int ops; 1098 { 1099 1100 /* 1101 * XXX Should perform cache flushes as necessary. 1102 */ 1103 } 1104 #endif /* SUN4M */ 1105 1106 int 1107 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1108 bus_dma_tag_t t; 1109 bus_dma_segment_t *segs; 1110 int nsegs; 1111 size_t size; 1112 caddr_t *kvap; 1113 int flags; 1114 { 1115 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1116 1117 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1118 } 1119
Indexes created Fri Sep 26 20:09:58 GMT 2025