vme_machdep.c revision 1.17
1 /* $NetBSD: vme_machdep.c,v 1.17 1999/03/26 23:41:34 mycroft Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <sys/proc.h> 46 #include <sys/user.h> 47 #include <sys/syslog.h> 48 49 #include <vm/vm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <sparc/sparc/iommuvar.h> 54 #include <machine/autoconf.h> 55 #include <machine/pmap.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmevar.h> 61 62 #include <sparc/sparc/asm.h> 63 #include <sparc/sparc/vaddrs.h> 64 #include <sparc/sparc/cpuvar.h> 65 #include <sparc/dev/vmereg.h> 66 67 struct vmebus_softc { 68 struct device sc_dev; /* base device */ 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 struct vmebusreg *sc_reg; /* VME control registers */ 72 struct vmebusvec *sc_vec; /* VME interrupt vector */ 73 struct rom_range *sc_range; /* ROM range property */ 74 int sc_nrange; 75 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 76 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 77 int (*sc_vmeintr) __P((void *)); 78 struct bootpath *sc_bp; 79 }; 80 struct vmebus_softc *vmebus_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 static int sparc_vme_error __P((void)); 93 #endif 94 95 96 static int sparc_vme_probe __P((void *, bus_space_tag_t, vme_addr_t, 97 size_t, vme_size_t, vme_mod_t, 98 int (*) __P((void *, void *)), void *)); 99 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_mod_t, 100 bus_space_tag_t, bus_space_handle_t *)); 101 static void sparc_vme_unmap __P((void *)); 102 static int sparc_vme_mmap_cookie __P((void *, vme_addr_t, vme_mod_t, 103 bus_space_tag_t, bus_space_handle_t *)); 104 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 105 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, 106 int (*) __P((void *)), void *)); 107 static void sparc_vme_intr_disestablish __P((void *, void *)); 108 109 static int vmebus_translate __P((struct vmebus_softc *, vme_mod_t, 110 vme_addr_t, bus_type_t *, bus_addr_t *)); 111 static void sparc_vme_bus_establish __P((void *, struct device *)); 112 #if defined(SUN4M) 113 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 114 bus_size_t, bus_size_t, int)); 115 116 #endif 117 118 /* 119 * DMA functions. 120 */ 121 #if defined(SUN4) 122 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 123 bus_size_t, struct proc *, int)); 124 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 125 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 126 bus_addr_t, bus_size_t, int)); 127 128 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 129 bus_size_t, bus_size_t, bus_dma_segment_t *, 130 int, int *, int)); 131 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 132 bus_dma_segment_t *, int)); 133 #endif 134 135 #if defined(SUN4M) 136 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 137 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 138 139 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 140 bus_size_t, struct proc *, int)); 141 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 142 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 143 bus_addr_t, bus_size_t, int)); 144 145 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 146 bus_size_t, bus_size_t, bus_dma_segment_t *, 147 int, int *, int)); 148 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 149 bus_dma_segment_t *, int)); 150 #endif 151 152 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 153 int, size_t, caddr_t *, int)); 154 #if 0 155 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 156 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 157 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 158 bus_dma_segment_t *, int, int, int, int)); 159 #endif 160 161 struct cfattach vme_mainbus_ca = { 162 sizeof(struct vmebus_softc), vmematch_mainbus, vmeattach_mainbus 163 }; 164 165 struct cfattach vme_iommu_ca = { 166 sizeof(struct vmebus_softc), vmematch_iommu, vmeattach_iommu 167 }; 168 169 int (*vmeerr_handler) __P((void)); 170 171 /* If the PROM does not provide the `ranges' property, we make up our own */ 172 struct rom_range vmebus_translations[] = { 173 #define _DS (VMEMOD_D|VMEMOD_S) 174 { VMEMOD_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 175 { VMEMOD_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 176 { VMEMOD_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 177 { VMEMOD_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 178 { VMEMOD_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 179 { VMEMOD_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 180 #undef _DS 181 }; 182 183 /* 184 * DMA on sun4 VME devices use the last MB of virtual space, which 185 * is mapped by hardware onto the first MB of VME space. 186 */ 187 struct extent *vme_dvmamap; 188 189 struct sparc_bus_space_tag sparc_vme_bus_tag = { 190 NULL, /* cookie */ 191 NULL, /* parent bus tag */ 192 NULL, /* bus_map */ 193 NULL, /* bus_unmap */ 194 NULL, /* bus_subregion */ 195 NULL /* barrier */ 196 }; 197 198 struct vme_chipset_tag sparc_vme_chipset_tag = { 199 NULL, 200 sparc_vme_probe, 201 sparc_vme_map, 202 sparc_vme_unmap, 203 sparc_vme_mmap_cookie, 204 sparc_vme_intr_map, 205 sparc_vme_intr_establish, 206 sparc_vme_intr_disestablish, 207 sparc_vme_bus_establish 208 }; 209 210 211 #if defined(SUN4) 212 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 213 NULL, /* cookie */ 214 _bus_dmamap_create, 215 _bus_dmamap_destroy, 216 sparc_vme4_dmamap_load, 217 _bus_dmamap_load_mbuf, 218 _bus_dmamap_load_uio, 219 _bus_dmamap_load_raw, 220 sparc_vme4_dmamap_unload, 221 sparc_vme4_dmamap_sync, 222 223 sparc_vme4_dmamem_alloc, 224 sparc_vme4_dmamem_free, 225 sparc_vme_dmamem_map, 226 _bus_dmamem_unmap, 227 _bus_dmamem_mmap 228 }; 229 #endif 230 231 #if defined(SUN4M) 232 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 233 NULL, /* cookie */ 234 sparc_vme4m_dmamap_create, 235 _bus_dmamap_destroy, 236 sparc_vme4m_dmamap_load, 237 _bus_dmamap_load_mbuf, 238 _bus_dmamap_load_uio, 239 _bus_dmamap_load_raw, 240 sparc_vme4m_dmamap_unload, 241 sparc_vme4m_dmamap_sync, 242 243 sparc_vme4m_dmamem_alloc, 244 sparc_vme4m_dmamem_free, 245 sparc_vme_dmamem_map, 246 _bus_dmamem_unmap, 247 _bus_dmamem_mmap 248 }; 249 #endif 250 251 252 void 253 sparc_vme_bus_establish(cookie, dev) 254 void *cookie; 255 struct device *dev; 256 { 257 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 258 struct bootpath *bp = sc->sc_bp; 259 char *name; 260 261 name = dev->dv_cfdata->cf_driver->cd_name; 262 #ifdef DEBUG 263 printf("sparc_vme_bus_establish: %s%d\n", name, dev->dv_unit); 264 #endif 265 if (bp != NULL && strcmp(bp->name, name) == 0 && 266 dev->dv_unit == bp->val[1]) { 267 bp->dev = dev; 268 #ifdef DEBUG 269 printf("sparc_vme_bus_establish: on the boot path\n"); 270 #endif 271 sc->sc_bp++; 272 bootpath_store(1, sc->sc_bp); 273 } 274 } 275 276 277 int 278 vmematch_mainbus(parent, cf, aux) 279 struct device *parent; 280 struct cfdata *cf; 281 void *aux; 282 { 283 struct mainbus_attach_args *ma = aux; 284 285 if (!CPU_ISSUN4) 286 return (0); 287 288 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 289 } 290 291 int 292 vmematch_iommu(parent, cf, aux) 293 struct device *parent; 294 struct cfdata *cf; 295 void *aux; 296 { 297 struct iommu_attach_args *ia = aux; 298 299 return (strcmp(cf->cf_driver->cd_name, ia->iom_name) == 0); 300 } 301 302 303 void 304 vmeattach_mainbus(parent, self, aux) 305 struct device *parent, *self; 306 void *aux; 307 { 308 #if defined(SUN4) 309 struct mainbus_attach_args *ma = aux; 310 struct vmebus_softc *sc = (struct vmebus_softc *)self; 311 struct vme_busattach_args vba; 312 313 if (self->dv_unit > 0) { 314 printf(" unsupported\n"); 315 return; 316 } 317 318 sc->sc_bustag = ma->ma_bustag; 319 sc->sc_dmatag = ma->ma_dmatag; 320 321 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 322 sc->sc_bp = ma->ma_bp + 1; 323 bootpath_store(1, sc->sc_bp); 324 } 325 326 /* VME interrupt entry point */ 327 sc->sc_vmeintr = vmeintr4; 328 329 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 330 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 331 332 vba.vba_bustag = &sparc_vme_bus_tag; 333 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 334 vba.vba_dmatag = &sparc_vme4_dma_tag; 335 336 /* Fall back to our own `range' construction */ 337 sc->sc_range = vmebus_translations; 338 sc->sc_nrange = 339 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 340 341 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 342 M_DEVBUF, 0, 0, EX_NOWAIT); 343 if (vme_dvmamap == NULL) 344 panic("vme: unable to allocate DVMA map"); 345 346 printf("\n"); 347 (void)config_search(vmesearch, self, &vba); 348 349 bootpath_store(1, NULL); 350 #endif 351 return; 352 } 353 354 /* sun4m vmebus */ 355 void 356 vmeattach_iommu(parent, self, aux) 357 struct device *parent, *self; 358 void *aux; 359 { 360 #if defined(SUN4M) 361 struct vmebus_softc *sc = (struct vmebus_softc *)self; 362 struct iommu_attach_args *ia = aux; 363 struct vme_busattach_args vba; 364 bus_space_handle_t bh; 365 int node; 366 int cline; 367 368 if (self->dv_unit > 0) { 369 printf(" unsupported\n"); 370 return; 371 } 372 373 sc->sc_bustag = ia->iom_bustag; 374 sc->sc_dmatag = ia->iom_dmatag; 375 376 /* VME interrupt entry point */ 377 sc->sc_vmeintr = vmeintr4m; 378 379 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 380 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 381 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 382 383 vba.vba_bustag = &sparc_vme_bus_tag; 384 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 385 vba.vba_dmatag = &sparc_vme4m_dma_tag; 386 387 node = ia->iom_node; 388 389 /* 390 * Map VME control space 391 */ 392 if (ia->iom_nreg < 2) { 393 printf("%s: only %d register sets\n", self->dv_xname, 394 ia->iom_nreg); 395 return; 396 } 397 398 if (bus_space_map2(ia->iom_bustag, 399 (bus_type_t)ia->iom_reg[0].ior_iospace, 400 (bus_addr_t)ia->iom_reg[0].ior_pa, 401 (bus_size_t)ia->iom_reg[0].ior_size, 402 BUS_SPACE_MAP_LINEAR, 403 0, &bh) != 0) { 404 panic("%s: can't map vmebusreg", self->dv_xname); 405 } 406 sc->sc_reg = (struct vmebusreg *)bh; 407 408 if (bus_space_map2(ia->iom_bustag, 409 (bus_type_t)ia->iom_reg[1].ior_iospace, 410 (bus_addr_t)ia->iom_reg[1].ior_pa, 411 (bus_size_t)ia->iom_reg[1].ior_size, 412 BUS_SPACE_MAP_LINEAR, 413 0, &bh) != 0) { 414 panic("%s: can't map vmebusvec", self->dv_xname); 415 } 416 sc->sc_vec = (struct vmebusvec *)bh; 417 418 /* 419 * Map VME IO cache tags and flush control. 420 */ 421 if (bus_space_map2(ia->iom_bustag, 422 (bus_type_t)ia->iom_reg[1].ior_iospace, 423 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 424 VME_IOC_SIZE, 425 BUS_SPACE_MAP_LINEAR, 426 0, &bh) != 0) { 427 panic("%s: can't map IOC tags", self->dv_xname); 428 } 429 sc->sc_ioctags = (u_int32_t *)bh; 430 431 if (bus_space_map2(ia->iom_bustag, 432 (bus_type_t)ia->iom_reg[1].ior_iospace, 433 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 434 VME_IOC_SIZE, 435 BUS_SPACE_MAP_LINEAR, 436 0, &bh) != 0) { 437 panic("%s: can't map IOC flush registers", self->dv_xname); 438 } 439 sc->sc_iocflush = (u_int32_t *)bh; 440 441 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 442 443 /* 444 * Get "range" property. 445 */ 446 if (getprop(node, "ranges", sizeof(struct rom_range), 447 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 448 panic("%s: can't get ranges property", self->dv_xname); 449 } 450 451 vmebus_sc = sc; 452 vmeerr_handler = sparc_vme_error; 453 454 /* 455 * Invalidate all IO-cache entries. 456 */ 457 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 458 sc->sc_ioctags[--cline] = 0; 459 } 460 461 /* Enable IO-cache */ 462 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 463 464 printf(": version 0x%x\n", 465 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 466 467 (void)config_search(vmesearch, self, &vba); 468 #endif 469 } 470 471 #if defined(SUN4M) 472 static int 473 sparc_vme_error() 474 { 475 struct vmebus_softc *sc = vmebus_sc; 476 u_int32_t afsr, afpa; 477 char bits[64]; 478 479 afsr = sc->sc_reg->vmebus_afsr, 480 afpa = sc->sc_reg->vmebus_afar; 481 printf("VME error:\n\tAFSR %s\n", 482 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 483 printf("\taddress: 0x%x%x\n", afsr, afpa); 484 return (0); 485 } 486 #endif 487 488 int 489 vmebus_translate(sc, mod, addr, btp, bap) 490 struct vmebus_softc *sc; 491 vme_mod_t mod; 492 vme_addr_t addr; 493 bus_type_t *btp; 494 bus_addr_t *bap; 495 { 496 int i; 497 498 for (i = 0; i < sc->sc_nrange; i++) { 499 500 if (sc->sc_range[i].cspace != mod) 501 continue; 502 503 /* We've found the connection to the parent bus */ 504 *bap = sc->sc_range[i].poffset + addr; 505 *btp = sc->sc_range[i].pspace; 506 return (0); 507 } 508 return (ENOENT); 509 } 510 511 int 512 sparc_vme_probe(cookie, tag, addr, offset, size, mod, callback, arg) 513 void *cookie; 514 bus_space_tag_t tag; 515 vme_addr_t addr; 516 size_t offset; 517 vme_size_t size; 518 int mod; 519 int (*callback) __P((void *, void *)); 520 void *arg; 521 { 522 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 523 bus_type_t iospace; 524 bus_addr_t paddr; 525 526 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 527 return (0); 528 529 return (bus_space_probe(sc->sc_bustag, iospace, paddr, size, offset, 530 0, callback, arg)); 531 } 532 533 int 534 sparc_vme_map(cookie, addr, size, mod, tag, hp) 535 void *cookie; 536 vme_addr_t addr; 537 vme_size_t size; 538 int mod; 539 bus_space_tag_t tag; 540 bus_space_handle_t *hp; 541 { 542 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 543 bus_type_t iospace; 544 bus_addr_t paddr; 545 int error; 546 547 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 548 if (error != 0) 549 return (error); 550 551 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 552 } 553 554 int 555 sparc_vme_mmap_cookie(cookie, addr, mod, tag, hp) 556 void *cookie; 557 vme_addr_t addr; 558 int mod; 559 bus_space_tag_t tag; 560 bus_space_handle_t *hp; 561 { 562 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 563 bus_type_t iospace; 564 bus_addr_t paddr; 565 int error; 566 567 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 568 if (error != 0) 569 return (error); 570 571 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 572 } 573 574 #if defined(SUN4M) 575 void 576 sparc_vme4m_barrier(t, h, offset, size, flags) 577 bus_space_tag_t t; 578 bus_space_handle_t h; 579 bus_size_t offset; 580 bus_size_t size; 581 int flags; 582 { 583 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 584 585 /* Read async fault status to flush write-buffers */ 586 (*(volatile int *)&vbp->vmebus_afsr); 587 } 588 #endif 589 590 591 592 /* 593 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 594 */ 595 static int vme_ipl_to_pil[] = { 596 0, 597 2, 598 3, 599 5, 600 7, 601 9, 602 11, 603 13 604 }; 605 606 607 /* 608 * All VME device interrupts go through vmeintr(). This function reads 609 * the VME vector from the bus, then dispatches the device interrupt 610 * handler. All handlers for devices that map to the same Processor 611 * Interrupt Level (according to the table above) are on a linked list 612 * of `sparc_vme_intr_handle' structures. The head of which is passed 613 * down as the argument to `vmeintr(void *arg)'. 614 */ 615 struct sparc_vme_intr_handle { 616 struct intrhand ih; 617 struct sparc_vme_intr_handle *next; 618 int vec; /* VME interrupt vector */ 619 int pri; /* VME interrupt priority */ 620 struct vmebus_softc *sc;/*XXX*/ 621 }; 622 623 #if defined(SUN4) 624 int 625 vmeintr4(arg) 626 void *arg; 627 { 628 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 629 int level, vec; 630 int i = 0; 631 632 level = (ihp->pri << 1) | 1; 633 634 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 635 636 if (vec == -1) { 637 printf("vme: spurious interrupt\n"); 638 return 1; /* XXX - pretend we handled it, for now */ 639 } 640 641 for (; ihp; ihp = ihp->next) 642 if (ihp->vec == vec && ihp->ih.ih_fun) 643 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 644 return (i); 645 } 646 #endif 647 648 #if defined(SUN4M) 649 int 650 vmeintr4m(arg) 651 void *arg; 652 { 653 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 654 int level, vec; 655 int i = 0; 656 657 level = (ihp->pri << 1) | 1; 658 659 #if 0 660 int pending; 661 662 /* Flush VME <=> Sbus write buffers */ 663 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 664 665 pending = *((int*)ICR_SI_PEND); 666 if ((pending & SINTR_VME(ihp->pri)) == 0) { 667 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 668 ihp->pri, pending); 669 return (0); 670 } 671 #endif 672 #if 0 673 /* Why gives this a bus timeout sometimes? */ 674 vec = ihp->sc->sc_vec->vmebusvec[level]; 675 #else 676 /* so, arrange to catch the fault... */ 677 { 678 extern struct user *proc0paddr; 679 extern int fkbyte __P((caddr_t, struct pcb *)); 680 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 681 struct pcb *xpcb; 682 u_long saveonfault; 683 int s; 684 685 s = splhigh(); 686 if (curproc == NULL) 687 xpcb = (struct pcb *)proc0paddr; 688 else 689 xpcb = &curproc->p_addr->u_pcb; 690 691 saveonfault = (u_long)xpcb->pcb_onfault; 692 vec = fkbyte(addr, xpcb); 693 xpcb->pcb_onfault = (caddr_t)saveonfault; 694 695 splx(s); 696 } 697 #endif 698 699 if (vec == -1) { 700 printf("vme: spurious interrupt: "); 701 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 702 *((int*)ICR_SI_PEND), 703 ihp->sc->sc_reg->vmebus_afsr, 704 ihp->sc->sc_reg->vmebus_afar); 705 return (1); /* XXX - pretend we handled it, for now */ 706 } 707 708 for (; ihp; ihp = ihp->next) 709 if (ihp->vec == vec && ihp->ih.ih_fun) 710 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 711 return (i); 712 } 713 #endif 714 715 int 716 sparc_vme_intr_map(cookie, vec, pri, ihp) 717 void *cookie; 718 int vec; 719 int pri; 720 vme_intr_handle_t *ihp; 721 { 722 struct sparc_vme_intr_handle *ih; 723 724 ih = (vme_intr_handle_t) 725 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 726 ih->pri = pri; 727 ih->vec = vec; 728 ih->sc = cookie;/*XXX*/ 729 *ihp = ih; 730 return (0); 731 } 732 733 void * 734 sparc_vme_intr_establish(cookie, vih, func, arg) 735 void *cookie; 736 vme_intr_handle_t vih; 737 int (*func) __P((void *)); 738 void *arg; 739 { 740 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 741 struct sparc_vme_intr_handle *svih = 742 (struct sparc_vme_intr_handle *)vih; 743 struct intrhand *ih; 744 int level; 745 746 /* Translate VME priority to processor IPL */ 747 level = vme_ipl_to_pil[svih->pri]; 748 749 svih->ih.ih_fun = func; 750 svih->ih.ih_arg = arg; 751 svih->next = NULL; 752 753 /* ensure the interrupt subsystem will call us at this level */ 754 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 755 if (ih->ih_fun == sc->sc_vmeintr) 756 break; 757 758 if (ih == NULL) { 759 ih = (struct intrhand *) 760 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 761 if (ih == NULL) 762 panic("vme_addirq"); 763 bzero(ih, sizeof *ih); 764 ih->ih_fun = sc->sc_vmeintr; 765 ih->ih_arg = vih; 766 intr_establish(level, ih); 767 } else { 768 svih->next = (vme_intr_handle_t)ih->ih_arg; 769 ih->ih_arg = vih; 770 } 771 return (NULL); 772 } 773 774 void 775 sparc_vme_unmap(cookie) 776 void * cookie; 777 { 778 /* Not implemented */ 779 panic("sparc_vme_unmap"); 780 } 781 782 void 783 sparc_vme_intr_disestablish(cookie, a) 784 void *cookie; 785 void *a; 786 { 787 /* Not implemented */ 788 panic("sparc_vme_intr_disestablish"); 789 } 790 791 792 793 /* 794 * VME DMA functions. 795 */ 796 797 #if defined(SUN4) 798 int 799 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 800 bus_dma_tag_t t; 801 bus_dmamap_t map; 802 void *buf; 803 bus_size_t buflen; 804 struct proc *p; 805 int flags; 806 { 807 bus_addr_t dvmaddr; 808 bus_size_t sgsize; 809 vaddr_t vaddr; 810 pmap_t pmap; 811 int pagesz = PAGE_SIZE; 812 int error; 813 814 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 815 map->_dm_boundary, 816 (flags & BUS_DMA_NOWAIT) == 0 817 ? EX_WAITOK 818 : EX_NOWAIT, 819 (u_long *)&dvmaddr); 820 if (error != 0) 821 return (error); 822 823 vaddr = (vaddr_t)buf; 824 map->dm_mapsize = buflen; 825 map->dm_nsegs = 1; 826 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 827 map->dm_segs[0].ds_len = buflen; 828 829 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 830 831 for (; buflen > 0; ) { 832 paddr_t pa; 833 /* 834 * Get the physical address for this page. 835 */ 836 pa = pmap_extract(pmap, vaddr); 837 838 /* 839 * Compute the segment size, and adjust counts. 840 */ 841 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 842 if (buflen < sgsize) 843 sgsize = buflen; 844 845 #ifdef notyet 846 if (have_iocache) 847 curaddr |= PG_IOC; 848 #endif 849 pmap_enter(pmap_kernel(), dvmaddr, 850 (pa & ~(pagesz-1)) | PMAP_NC, 851 VM_PROT_READ|VM_PROT_WRITE, 1, 0); 852 853 dvmaddr += pagesz; 854 vaddr += sgsize; 855 buflen -= sgsize; 856 } 857 858 /* Adjust DVMA address to VME view */ 859 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 860 return (0); 861 } 862 863 void 864 sparc_vme4_dmamap_unload(t, map) 865 bus_dma_tag_t t; 866 bus_dmamap_t map; 867 { 868 bus_addr_t addr; 869 bus_size_t len; 870 871 /* Go from VME to CPU view */ 872 map->dm_segs[0].ds_addr += VME4_DVMA_BASE; 873 874 addr = map->dm_segs[0].ds_addr & ~PGOFSET; 875 len = round_page(map->dm_segs[0].ds_len); 876 877 /* Remove double-mapping in DVMA space */ 878 pmap_remove(pmap_kernel(), addr, addr + len); 879 880 /* Release DVMA space */ 881 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 882 printf("warning: %ld of DVMA space lost\n", len); 883 884 /* Mark the mappings as invalid. */ 885 map->dm_mapsize = 0; 886 map->dm_nsegs = 0; 887 } 888 889 int 890 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 891 bus_dma_tag_t t; 892 bus_size_t size, alignment, boundary; 893 bus_dma_segment_t *segs; 894 int nsegs; 895 int *rsegs; 896 int flags; 897 { 898 bus_addr_t dvmaddr; 899 struct pglist *mlist; 900 vm_page_t m; 901 paddr_t pa; 902 int error; 903 904 size = round_page(size); 905 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 906 segs, nsegs, rsegs, flags); 907 if (error != 0) 908 return (error); 909 910 if (extent_alloc(vme_dvmamap, size, alignment, boundary, 911 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 912 (u_long *)&dvmaddr) != 0) 913 return (ENOMEM); 914 915 /* 916 * Compute the location, size, and number of segments actually 917 * returned by the VM code. 918 */ 919 segs[0].ds_addr = dvmaddr - VME4_DVMA_BASE; 920 segs[0].ds_len = size; 921 *rsegs = 1; 922 923 /* Map memory into DVMA space */ 924 mlist = segs[0]._ds_mlist; 925 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 926 pa = VM_PAGE_TO_PHYS(m); 927 928 #ifdef notyet 929 if (have_iocache) 930 pa |= PG_IOC; 931 #endif 932 pmap_enter(pmap_kernel(), dvmaddr, pa | PMAP_NC, 933 VM_PROT_READ|VM_PROT_WRITE, 1, 0); 934 dvmaddr += PAGE_SIZE; 935 } 936 937 return (0); 938 } 939 940 void 941 sparc_vme4_dmamem_free(t, segs, nsegs) 942 bus_dma_tag_t t; 943 bus_dma_segment_t *segs; 944 int nsegs; 945 { 946 bus_addr_t addr; 947 bus_size_t len; 948 949 addr = segs[0].ds_addr + VME4_DVMA_BASE; 950 len = round_page(segs[0].ds_len); 951 952 /* Remove DVMA kernel map */ 953 pmap_remove(pmap_kernel(), addr, addr + len); 954 955 /* Release DVMA address range */ 956 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 957 printf("warning: %ld of DVMA space lost\n", len); 958 959 /* 960 * Return the list of pages back to the VM system. 961 */ 962 _bus_dmamem_free_common(t, segs, nsegs); 963 } 964 965 void 966 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 967 bus_dma_tag_t t; 968 bus_dmamap_t map; 969 bus_addr_t offset; 970 bus_size_t len; 971 int ops; 972 { 973 974 /* 975 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 976 * Currently the cache is flushed in bus_dma_load()... 977 */ 978 } 979 #endif /* SUN4 */ 980 981 #if defined(SUN4M) 982 static int 983 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 984 bus_dma_tag_t t; 985 bus_size_t size; 986 int nsegments; 987 bus_size_t maxsegsz; 988 bus_size_t boundary; 989 int flags; 990 bus_dmamap_t *dmamp; 991 { 992 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 993 int error; 994 995 /* XXX - todo: allocate DVMA addresses from assigned ranges: 996 upper 8MB for A32 space; upper 1MB for A24 space */ 997 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 998 boundary, flags, dmamp); 999 if (error != 0) 1000 return (error); 1001 1002 #if 0 1003 /* VME DVMA addresses must always be 8K aligned */ 1004 (*dmamp)->_dm_align = 8192; 1005 #endif 1006 1007 return (0); 1008 } 1009 1010 int 1011 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1012 bus_dma_tag_t t; 1013 bus_dmamap_t map; 1014 void *buf; 1015 bus_size_t buflen; 1016 struct proc *p; 1017 int flags; 1018 { 1019 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1020 volatile u_int32_t *ioctags; 1021 int error; 1022 1023 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 1024 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1025 if (error != 0) 1026 return (error); 1027 1028 /* allocate IO cache entries for this range */ 1029 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1030 for (;buflen > 0;) { 1031 *ioctags = VME_IOC_IC | VME_IOC_W; 1032 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1033 buflen -= VME_IOC_PAGESZ; 1034 } 1035 return (0); 1036 } 1037 1038 1039 void 1040 sparc_vme4m_dmamap_unload(t, map) 1041 bus_dma_tag_t t; 1042 bus_dmamap_t map; 1043 { 1044 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1045 volatile u_int32_t *flushregs; 1046 int len; 1047 1048 /* Flush VME IO cache */ 1049 len = map->dm_segs[0].ds_len; 1050 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1051 for (;len > 0;) { 1052 *flushregs = 0; 1053 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1054 len -= VME_IOC_PAGESZ; 1055 } 1056 /* Read a tag to synchronize the IOC flushes */ 1057 (*sc->sc_ioctags); 1058 1059 bus_dmamap_unload(sc->sc_dmatag, map); 1060 } 1061 1062 int 1063 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 1064 bus_dma_tag_t t; 1065 bus_size_t size, alignmnt, boundary; 1066 bus_dma_segment_t *segs; 1067 int nsegs; 1068 int *rsegs; 1069 int flags; 1070 { 1071 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1072 int error; 1073 1074 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 1075 segs, nsegs, rsegs, flags); 1076 if (error != 0) 1077 return (error); 1078 1079 return (0); 1080 } 1081 1082 void 1083 sparc_vme4m_dmamem_free(t, segs, nsegs) 1084 bus_dma_tag_t t; 1085 bus_dma_segment_t *segs; 1086 int nsegs; 1087 { 1088 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1089 1090 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 1091 } 1092 1093 void 1094 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1095 bus_dma_tag_t t; 1096 bus_dmamap_t map; 1097 bus_addr_t offset; 1098 bus_size_t len; 1099 int ops; 1100 { 1101 1102 /* 1103 * XXX Should perform cache flushes as necessary. 1104 */ 1105 } 1106 #endif /* SUN4M */ 1107 1108 int 1109 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1110 bus_dma_tag_t t; 1111 bus_dma_segment_t *segs; 1112 int nsegs; 1113 size_t size; 1114 caddr_t *kvap; 1115 int flags; 1116 { 1117 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1118 1119 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1120 } 1121
Indexes created Tue Sep 23 23:09:58 GMT 2025