vme_machdep.c revision 1.18
1 /* $NetBSD: vme_machdep.c,v 1.18 1999/04/14 10:28:23 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 45 #include <sys/proc.h> 46 #include <sys/user.h> 47 #include <sys/syslog.h> 48 49 #include <vm/vm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <sparc/sparc/iommuvar.h> 54 #include <machine/autoconf.h> 55 #include <machine/pmap.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmevar.h> 61 62 #include <sparc/sparc/asm.h> 63 #include <sparc/sparc/vaddrs.h> 64 #include <sparc/sparc/cpuvar.h> 65 #include <sparc/dev/vmereg.h> 66 67 struct vmebus_softc { 68 struct device sc_dev; /* base device */ 69 bus_space_tag_t sc_bustag; 70 bus_dma_tag_t sc_dmatag; 71 struct vmebusreg *sc_reg; /* VME control registers */ 72 struct vmebusvec *sc_vec; /* VME interrupt vector */ 73 struct rom_range *sc_range; /* ROM range property */ 74 int sc_nrange; 75 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 76 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 77 int (*sc_vmeintr) __P((void *)); 78 struct bootpath *sc_bp; 79 }; 80 struct vmebus_softc *vmebus_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 static int sparc_vme_error __P((void)); 93 #endif 94 95 96 static int sparc_vme_probe __P((void *, bus_space_tag_t, vme_addr_t, 97 size_t, vme_size_t, vme_mod_t, 98 int (*) __P((void *, void *)), void *)); 99 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_mod_t, 100 bus_space_tag_t, bus_space_handle_t *)); 101 static void sparc_vme_unmap __P((void *)); 102 static int sparc_vme_mmap_cookie __P((void *, vme_addr_t, vme_mod_t, 103 bus_space_tag_t, bus_space_handle_t *)); 104 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 105 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, 106 int (*) __P((void *)), void *)); 107 static void sparc_vme_intr_disestablish __P((void *, void *)); 108 109 static int vmebus_translate __P((struct vmebus_softc *, vme_mod_t, 110 vme_addr_t, bus_type_t *, bus_addr_t *)); 111 static void sparc_vme_bus_establish __P((void *, struct device *)); 112 #if defined(SUN4M) 113 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 114 bus_size_t, bus_size_t, int)); 115 116 #endif 117 118 /* 119 * DMA functions. 120 */ 121 #if defined(SUN4) 122 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 123 bus_size_t, struct proc *, int)); 124 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 125 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 126 bus_addr_t, bus_size_t, int)); 127 128 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 129 bus_size_t, bus_size_t, bus_dma_segment_t *, 130 int, int *, int)); 131 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 132 bus_dma_segment_t *, int)); 133 #endif 134 135 #if defined(SUN4M) 136 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 137 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 138 139 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 140 bus_size_t, struct proc *, int)); 141 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 142 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 143 bus_addr_t, bus_size_t, int)); 144 145 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 146 bus_size_t, bus_size_t, bus_dma_segment_t *, 147 int, int *, int)); 148 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 149 bus_dma_segment_t *, int)); 150 #endif 151 152 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 153 int, size_t, caddr_t *, int)); 154 #if 0 155 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 156 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 157 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 158 bus_dma_segment_t *, int, int, int, int)); 159 #endif 160 161 struct cfattach vme_mainbus_ca = { 162 sizeof(struct vmebus_softc), vmematch_mainbus, vmeattach_mainbus 163 }; 164 165 struct cfattach vme_iommu_ca = { 166 sizeof(struct vmebus_softc), vmematch_iommu, vmeattach_iommu 167 }; 168 169 int (*vmeerr_handler) __P((void)); 170 171 /* If the PROM does not provide the `ranges' property, we make up our own */ 172 struct rom_range vmebus_translations[] = { 173 #define _DS (VMEMOD_D|VMEMOD_S) 174 { VMEMOD_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 175 { VMEMOD_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 176 { VMEMOD_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 177 { VMEMOD_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 178 { VMEMOD_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 179 { VMEMOD_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 180 #undef _DS 181 }; 182 183 /* 184 * DMA on sun4 VME devices use the last MB of virtual space, which 185 * is mapped by hardware onto the first MB of VME space. 186 */ 187 struct extent *vme_dvmamap; 188 189 struct sparc_bus_space_tag sparc_vme_bus_tag = { 190 NULL, /* cookie */ 191 NULL, /* parent bus tag */ 192 NULL, /* bus_map */ 193 NULL, /* bus_unmap */ 194 NULL, /* bus_subregion */ 195 NULL /* barrier */ 196 }; 197 198 struct vme_chipset_tag sparc_vme_chipset_tag = { 199 NULL, 200 sparc_vme_probe, 201 sparc_vme_map, 202 sparc_vme_unmap, 203 sparc_vme_mmap_cookie, 204 sparc_vme_intr_map, 205 sparc_vme_intr_establish, 206 sparc_vme_intr_disestablish, 207 sparc_vme_bus_establish 208 }; 209 210 211 #if defined(SUN4) 212 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 213 NULL, /* cookie */ 214 _bus_dmamap_create, 215 _bus_dmamap_destroy, 216 sparc_vme4_dmamap_load, 217 _bus_dmamap_load_mbuf, 218 _bus_dmamap_load_uio, 219 _bus_dmamap_load_raw, 220 sparc_vme4_dmamap_unload, 221 sparc_vme4_dmamap_sync, 222 223 sparc_vme4_dmamem_alloc, 224 sparc_vme4_dmamem_free, 225 sparc_vme_dmamem_map, 226 _bus_dmamem_unmap, 227 _bus_dmamem_mmap 228 }; 229 #endif 230 231 #if defined(SUN4M) 232 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 233 NULL, /* cookie */ 234 sparc_vme4m_dmamap_create, 235 _bus_dmamap_destroy, 236 sparc_vme4m_dmamap_load, 237 _bus_dmamap_load_mbuf, 238 _bus_dmamap_load_uio, 239 _bus_dmamap_load_raw, 240 sparc_vme4m_dmamap_unload, 241 sparc_vme4m_dmamap_sync, 242 243 sparc_vme4m_dmamem_alloc, 244 sparc_vme4m_dmamem_free, 245 sparc_vme_dmamem_map, 246 _bus_dmamem_unmap, 247 _bus_dmamem_mmap 248 }; 249 #endif 250 251 252 void 253 sparc_vme_bus_establish(cookie, dev) 254 void *cookie; 255 struct device *dev; 256 { 257 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 258 struct bootpath *bp = sc->sc_bp; 259 char *name; 260 261 name = dev->dv_cfdata->cf_driver->cd_name; 262 #ifdef DEBUG 263 printf("sparc_vme_bus_establish: %s%d\n", name, dev->dv_unit); 264 #endif 265 if (bp != NULL && strcmp(bp->name, name) == 0 && 266 dev->dv_unit == bp->val[1]) { 267 bp->dev = dev; 268 #ifdef DEBUG 269 printf("sparc_vme_bus_establish: on the boot path\n"); 270 #endif 271 sc->sc_bp++; 272 bootpath_store(1, sc->sc_bp); 273 } 274 } 275 276 277 int 278 vmematch_mainbus(parent, cf, aux) 279 struct device *parent; 280 struct cfdata *cf; 281 void *aux; 282 { 283 struct mainbus_attach_args *ma = aux; 284 285 if (!CPU_ISSUN4) 286 return (0); 287 288 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 289 } 290 291 int 292 vmematch_iommu(parent, cf, aux) 293 struct device *parent; 294 struct cfdata *cf; 295 void *aux; 296 { 297 struct iommu_attach_args *ia = aux; 298 299 return (strcmp(cf->cf_driver->cd_name, ia->iom_name) == 0); 300 } 301 302 303 void 304 vmeattach_mainbus(parent, self, aux) 305 struct device *parent, *self; 306 void *aux; 307 { 308 #if defined(SUN4) 309 struct mainbus_attach_args *ma = aux; 310 struct vmebus_softc *sc = (struct vmebus_softc *)self; 311 struct vme_busattach_args vba; 312 313 if (self->dv_unit > 0) { 314 printf(" unsupported\n"); 315 return; 316 } 317 318 sc->sc_bustag = ma->ma_bustag; 319 sc->sc_dmatag = ma->ma_dmatag; 320 321 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 322 sc->sc_bp = ma->ma_bp + 1; 323 bootpath_store(1, sc->sc_bp); 324 } 325 326 /* VME interrupt entry point */ 327 sc->sc_vmeintr = vmeintr4; 328 329 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 330 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 331 332 sparc_vme_bus_tag.parent = ma->ma_bustag; 333 vba.vba_bustag = &sparc_vme_bus_tag; 334 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 335 vba.vba_dmatag = &sparc_vme4_dma_tag; 336 337 /* Fall back to our own `range' construction */ 338 sc->sc_range = vmebus_translations; 339 sc->sc_nrange = 340 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 341 342 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 343 M_DEVBUF, 0, 0, EX_NOWAIT); 344 if (vme_dvmamap == NULL) 345 panic("vme: unable to allocate DVMA map"); 346 347 printf("\n"); 348 (void)config_search(vmesearch, self, &vba); 349 350 bootpath_store(1, NULL); 351 #endif 352 return; 353 } 354 355 /* sun4m vmebus */ 356 void 357 vmeattach_iommu(parent, self, aux) 358 struct device *parent, *self; 359 void *aux; 360 { 361 #if defined(SUN4M) 362 struct vmebus_softc *sc = (struct vmebus_softc *)self; 363 struct iommu_attach_args *ia = aux; 364 struct vme_busattach_args vba; 365 bus_space_handle_t bh; 366 int node; 367 int cline; 368 369 if (self->dv_unit > 0) { 370 printf(" unsupported\n"); 371 return; 372 } 373 374 sc->sc_bustag = ia->iom_bustag; 375 sc->sc_dmatag = ia->iom_dmatag; 376 377 /* VME interrupt entry point */ 378 sc->sc_vmeintr = vmeintr4m; 379 380 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 381 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 382 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 383 384 vba.vba_bustag = &sparc_vme_bus_tag; 385 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 386 vba.vba_dmatag = &sparc_vme4m_dma_tag; 387 388 node = ia->iom_node; 389 390 /* 391 * Map VME control space 392 */ 393 if (ia->iom_nreg < 2) { 394 printf("%s: only %d register sets\n", self->dv_xname, 395 ia->iom_nreg); 396 return; 397 } 398 399 if (bus_space_map2(ia->iom_bustag, 400 (bus_type_t)ia->iom_reg[0].ior_iospace, 401 (bus_addr_t)ia->iom_reg[0].ior_pa, 402 (bus_size_t)ia->iom_reg[0].ior_size, 403 BUS_SPACE_MAP_LINEAR, 404 0, &bh) != 0) { 405 panic("%s: can't map vmebusreg", self->dv_xname); 406 } 407 sc->sc_reg = (struct vmebusreg *)bh; 408 409 if (bus_space_map2(ia->iom_bustag, 410 (bus_type_t)ia->iom_reg[1].ior_iospace, 411 (bus_addr_t)ia->iom_reg[1].ior_pa, 412 (bus_size_t)ia->iom_reg[1].ior_size, 413 BUS_SPACE_MAP_LINEAR, 414 0, &bh) != 0) { 415 panic("%s: can't map vmebusvec", self->dv_xname); 416 } 417 sc->sc_vec = (struct vmebusvec *)bh; 418 419 /* 420 * Map VME IO cache tags and flush control. 421 */ 422 if (bus_space_map2(ia->iom_bustag, 423 (bus_type_t)ia->iom_reg[1].ior_iospace, 424 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 425 VME_IOC_SIZE, 426 BUS_SPACE_MAP_LINEAR, 427 0, &bh) != 0) { 428 panic("%s: can't map IOC tags", self->dv_xname); 429 } 430 sc->sc_ioctags = (u_int32_t *)bh; 431 432 if (bus_space_map2(ia->iom_bustag, 433 (bus_type_t)ia->iom_reg[1].ior_iospace, 434 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 435 VME_IOC_SIZE, 436 BUS_SPACE_MAP_LINEAR, 437 0, &bh) != 0) { 438 panic("%s: can't map IOC flush registers", self->dv_xname); 439 } 440 sc->sc_iocflush = (u_int32_t *)bh; 441 442 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 443 444 /* 445 * Get "range" property. 446 */ 447 if (getprop(node, "ranges", sizeof(struct rom_range), 448 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 449 panic("%s: can't get ranges property", self->dv_xname); 450 } 451 452 vmebus_sc = sc; 453 vmeerr_handler = sparc_vme_error; 454 455 /* 456 * Invalidate all IO-cache entries. 457 */ 458 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 459 sc->sc_ioctags[--cline] = 0; 460 } 461 462 /* Enable IO-cache */ 463 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 464 465 printf(": version 0x%x\n", 466 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 467 468 (void)config_search(vmesearch, self, &vba); 469 #endif 470 } 471 472 #if defined(SUN4M) 473 static int 474 sparc_vme_error() 475 { 476 struct vmebus_softc *sc = vmebus_sc; 477 u_int32_t afsr, afpa; 478 char bits[64]; 479 480 afsr = sc->sc_reg->vmebus_afsr, 481 afpa = sc->sc_reg->vmebus_afar; 482 printf("VME error:\n\tAFSR %s\n", 483 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 484 printf("\taddress: 0x%x%x\n", afsr, afpa); 485 return (0); 486 } 487 #endif 488 489 int 490 vmebus_translate(sc, mod, addr, btp, bap) 491 struct vmebus_softc *sc; 492 vme_mod_t mod; 493 vme_addr_t addr; 494 bus_type_t *btp; 495 bus_addr_t *bap; 496 { 497 int i; 498 499 for (i = 0; i < sc->sc_nrange; i++) { 500 501 if (sc->sc_range[i].cspace != mod) 502 continue; 503 504 /* We've found the connection to the parent bus */ 505 *bap = sc->sc_range[i].poffset + addr; 506 *btp = sc->sc_range[i].pspace; 507 return (0); 508 } 509 return (ENOENT); 510 } 511 512 int 513 sparc_vme_probe(cookie, tag, addr, offset, size, mod, callback, arg) 514 void *cookie; 515 bus_space_tag_t tag; 516 vme_addr_t addr; 517 size_t offset; 518 vme_size_t size; 519 int mod; 520 int (*callback) __P((void *, void *)); 521 void *arg; 522 { 523 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 524 bus_type_t iospace; 525 bus_addr_t paddr; 526 527 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 528 return (0); 529 530 return (bus_space_probe(sc->sc_bustag, iospace, paddr, size, offset, 531 0, callback, arg)); 532 } 533 534 int 535 sparc_vme_map(cookie, addr, size, mod, tag, hp) 536 void *cookie; 537 vme_addr_t addr; 538 vme_size_t size; 539 int mod; 540 bus_space_tag_t tag; 541 bus_space_handle_t *hp; 542 { 543 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 544 bus_type_t iospace; 545 bus_addr_t paddr; 546 int error; 547 548 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 549 if (error != 0) 550 return (error); 551 552 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 553 } 554 555 int 556 sparc_vme_mmap_cookie(cookie, addr, mod, tag, hp) 557 void *cookie; 558 vme_addr_t addr; 559 int mod; 560 bus_space_tag_t tag; 561 bus_space_handle_t *hp; 562 { 563 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 564 bus_type_t iospace; 565 bus_addr_t paddr; 566 int error; 567 568 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 569 if (error != 0) 570 return (error); 571 572 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 573 } 574 575 #if defined(SUN4M) 576 void 577 sparc_vme4m_barrier(t, h, offset, size, flags) 578 bus_space_tag_t t; 579 bus_space_handle_t h; 580 bus_size_t offset; 581 bus_size_t size; 582 int flags; 583 { 584 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 585 586 /* Read async fault status to flush write-buffers */ 587 (*(volatile int *)&vbp->vmebus_afsr); 588 } 589 #endif 590 591 592 593 /* 594 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 595 */ 596 static int vme_ipl_to_pil[] = { 597 0, 598 2, 599 3, 600 5, 601 7, 602 9, 603 11, 604 13 605 }; 606 607 608 /* 609 * All VME device interrupts go through vmeintr(). This function reads 610 * the VME vector from the bus, then dispatches the device interrupt 611 * handler. All handlers for devices that map to the same Processor 612 * Interrupt Level (according to the table above) are on a linked list 613 * of `sparc_vme_intr_handle' structures. The head of which is passed 614 * down as the argument to `vmeintr(void *arg)'. 615 */ 616 struct sparc_vme_intr_handle { 617 struct intrhand ih; 618 struct sparc_vme_intr_handle *next; 619 int vec; /* VME interrupt vector */ 620 int pri; /* VME interrupt priority */ 621 struct vmebus_softc *sc;/*XXX*/ 622 }; 623 624 #if defined(SUN4) 625 int 626 vmeintr4(arg) 627 void *arg; 628 { 629 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 630 int level, vec; 631 int i = 0; 632 633 level = (ihp->pri << 1) | 1; 634 635 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 636 637 if (vec == -1) { 638 printf("vme: spurious interrupt\n"); 639 return 1; /* XXX - pretend we handled it, for now */ 640 } 641 642 for (; ihp; ihp = ihp->next) 643 if (ihp->vec == vec && ihp->ih.ih_fun) 644 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 645 return (i); 646 } 647 #endif 648 649 #if defined(SUN4M) 650 int 651 vmeintr4m(arg) 652 void *arg; 653 { 654 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 655 int level, vec; 656 int i = 0; 657 658 level = (ihp->pri << 1) | 1; 659 660 #if 0 661 int pending; 662 663 /* Flush VME <=> Sbus write buffers */ 664 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 665 666 pending = *((int*)ICR_SI_PEND); 667 if ((pending & SINTR_VME(ihp->pri)) == 0) { 668 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 669 ihp->pri, pending); 670 return (0); 671 } 672 #endif 673 #if 0 674 /* Why gives this a bus timeout sometimes? */ 675 vec = ihp->sc->sc_vec->vmebusvec[level]; 676 #else 677 /* so, arrange to catch the fault... */ 678 { 679 extern struct user *proc0paddr; 680 extern int fkbyte __P((caddr_t, struct pcb *)); 681 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 682 struct pcb *xpcb; 683 u_long saveonfault; 684 int s; 685 686 s = splhigh(); 687 if (curproc == NULL) 688 xpcb = (struct pcb *)proc0paddr; 689 else 690 xpcb = &curproc->p_addr->u_pcb; 691 692 saveonfault = (u_long)xpcb->pcb_onfault; 693 vec = fkbyte(addr, xpcb); 694 xpcb->pcb_onfault = (caddr_t)saveonfault; 695 696 splx(s); 697 } 698 #endif 699 700 if (vec == -1) { 701 printf("vme: spurious interrupt: "); 702 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 703 *((int*)ICR_SI_PEND), 704 ihp->sc->sc_reg->vmebus_afsr, 705 ihp->sc->sc_reg->vmebus_afar); 706 return (1); /* XXX - pretend we handled it, for now */ 707 } 708 709 for (; ihp; ihp = ihp->next) 710 if (ihp->vec == vec && ihp->ih.ih_fun) 711 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 712 return (i); 713 } 714 #endif 715 716 int 717 sparc_vme_intr_map(cookie, vec, pri, ihp) 718 void *cookie; 719 int vec; 720 int pri; 721 vme_intr_handle_t *ihp; 722 { 723 struct sparc_vme_intr_handle *ih; 724 725 ih = (vme_intr_handle_t) 726 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 727 ih->pri = pri; 728 ih->vec = vec; 729 ih->sc = cookie;/*XXX*/ 730 *ihp = ih; 731 return (0); 732 } 733 734 void * 735 sparc_vme_intr_establish(cookie, vih, func, arg) 736 void *cookie; 737 vme_intr_handle_t vih; 738 int (*func) __P((void *)); 739 void *arg; 740 { 741 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 742 struct sparc_vme_intr_handle *svih = 743 (struct sparc_vme_intr_handle *)vih; 744 struct intrhand *ih; 745 int level; 746 747 /* Translate VME priority to processor IPL */ 748 level = vme_ipl_to_pil[svih->pri]; 749 750 svih->ih.ih_fun = func; 751 svih->ih.ih_arg = arg; 752 svih->next = NULL; 753 754 /* ensure the interrupt subsystem will call us at this level */ 755 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 756 if (ih->ih_fun == sc->sc_vmeintr) 757 break; 758 759 if (ih == NULL) { 760 ih = (struct intrhand *) 761 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 762 if (ih == NULL) 763 panic("vme_addirq"); 764 bzero(ih, sizeof *ih); 765 ih->ih_fun = sc->sc_vmeintr; 766 ih->ih_arg = vih; 767 intr_establish(level, ih); 768 } else { 769 svih->next = (vme_intr_handle_t)ih->ih_arg; 770 ih->ih_arg = vih; 771 } 772 return (NULL); 773 } 774 775 void 776 sparc_vme_unmap(cookie) 777 void * cookie; 778 { 779 /* Not implemented */ 780 panic("sparc_vme_unmap"); 781 } 782 783 void 784 sparc_vme_intr_disestablish(cookie, a) 785 void *cookie; 786 void *a; 787 { 788 /* Not implemented */ 789 panic("sparc_vme_intr_disestablish"); 790 } 791 792 793 794 /* 795 * VME DMA functions. 796 */ 797 798 #if defined(SUN4) 799 int 800 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 801 bus_dma_tag_t t; 802 bus_dmamap_t map; 803 void *buf; 804 bus_size_t buflen; 805 struct proc *p; 806 int flags; 807 { 808 bus_addr_t dvmaddr; 809 bus_size_t sgsize; 810 vaddr_t vaddr; 811 pmap_t pmap; 812 int pagesz = PAGE_SIZE; 813 int error; 814 815 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 816 map->_dm_boundary, 817 (flags & BUS_DMA_NOWAIT) == 0 818 ? EX_WAITOK 819 : EX_NOWAIT, 820 (u_long *)&dvmaddr); 821 if (error != 0) 822 return (error); 823 824 vaddr = (vaddr_t)buf; 825 map->dm_mapsize = buflen; 826 map->dm_nsegs = 1; 827 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 828 map->dm_segs[0].ds_len = buflen; 829 830 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 831 832 for (; buflen > 0; ) { 833 paddr_t pa; 834 /* 835 * Get the physical address for this page. 836 */ 837 pa = pmap_extract(pmap, vaddr); 838 839 /* 840 * Compute the segment size, and adjust counts. 841 */ 842 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 843 if (buflen < sgsize) 844 sgsize = buflen; 845 846 #ifdef notyet 847 if (have_iocache) 848 curaddr |= PG_IOC; 849 #endif 850 pmap_enter(pmap_kernel(), dvmaddr, 851 (pa & ~(pagesz-1)) | PMAP_NC, 852 VM_PROT_READ|VM_PROT_WRITE, 1, 0); 853 854 dvmaddr += pagesz; 855 vaddr += sgsize; 856 buflen -= sgsize; 857 } 858 859 /* Adjust DVMA address to VME view */ 860 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 861 return (0); 862 } 863 864 void 865 sparc_vme4_dmamap_unload(t, map) 866 bus_dma_tag_t t; 867 bus_dmamap_t map; 868 { 869 bus_addr_t addr; 870 bus_size_t len; 871 872 /* Go from VME to CPU view */ 873 map->dm_segs[0].ds_addr += VME4_DVMA_BASE; 874 875 addr = map->dm_segs[0].ds_addr & ~PGOFSET; 876 len = round_page(map->dm_segs[0].ds_len); 877 878 /* Remove double-mapping in DVMA space */ 879 pmap_remove(pmap_kernel(), addr, addr + len); 880 881 /* Release DVMA space */ 882 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 883 printf("warning: %ld of DVMA space lost\n", len); 884 885 /* Mark the mappings as invalid. */ 886 map->dm_mapsize = 0; 887 map->dm_nsegs = 0; 888 } 889 890 int 891 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 892 bus_dma_tag_t t; 893 bus_size_t size, alignment, boundary; 894 bus_dma_segment_t *segs; 895 int nsegs; 896 int *rsegs; 897 int flags; 898 { 899 bus_addr_t dvmaddr; 900 struct pglist *mlist; 901 vm_page_t m; 902 paddr_t pa; 903 int error; 904 905 size = round_page(size); 906 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 907 segs, nsegs, rsegs, flags); 908 if (error != 0) 909 return (error); 910 911 if (extent_alloc(vme_dvmamap, size, alignment, boundary, 912 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 913 (u_long *)&dvmaddr) != 0) 914 return (ENOMEM); 915 916 /* 917 * Compute the location, size, and number of segments actually 918 * returned by the VM code. 919 */ 920 segs[0].ds_addr = dvmaddr - VME4_DVMA_BASE; 921 segs[0].ds_len = size; 922 *rsegs = 1; 923 924 /* Map memory into DVMA space */ 925 mlist = segs[0]._ds_mlist; 926 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 927 pa = VM_PAGE_TO_PHYS(m); 928 929 #ifdef notyet 930 if (have_iocache) 931 pa |= PG_IOC; 932 #endif 933 pmap_enter(pmap_kernel(), dvmaddr, pa | PMAP_NC, 934 VM_PROT_READ|VM_PROT_WRITE, 1, 0); 935 dvmaddr += PAGE_SIZE; 936 } 937 938 return (0); 939 } 940 941 void 942 sparc_vme4_dmamem_free(t, segs, nsegs) 943 bus_dma_tag_t t; 944 bus_dma_segment_t *segs; 945 int nsegs; 946 { 947 bus_addr_t addr; 948 bus_size_t len; 949 950 addr = segs[0].ds_addr + VME4_DVMA_BASE; 951 len = round_page(segs[0].ds_len); 952 953 /* Remove DVMA kernel map */ 954 pmap_remove(pmap_kernel(), addr, addr + len); 955 956 /* Release DVMA address range */ 957 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 958 printf("warning: %ld of DVMA space lost\n", len); 959 960 /* 961 * Return the list of pages back to the VM system. 962 */ 963 _bus_dmamem_free_common(t, segs, nsegs); 964 } 965 966 void 967 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 968 bus_dma_tag_t t; 969 bus_dmamap_t map; 970 bus_addr_t offset; 971 bus_size_t len; 972 int ops; 973 { 974 975 /* 976 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 977 * Currently the cache is flushed in bus_dma_load()... 978 */ 979 } 980 #endif /* SUN4 */ 981 982 #if defined(SUN4M) 983 static int 984 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 985 bus_dma_tag_t t; 986 bus_size_t size; 987 int nsegments; 988 bus_size_t maxsegsz; 989 bus_size_t boundary; 990 int flags; 991 bus_dmamap_t *dmamp; 992 { 993 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 994 int error; 995 996 /* XXX - todo: allocate DVMA addresses from assigned ranges: 997 upper 8MB for A32 space; upper 1MB for A24 space */ 998 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 999 boundary, flags, dmamp); 1000 if (error != 0) 1001 return (error); 1002 1003 #if 0 1004 /* VME DVMA addresses must always be 8K aligned */ 1005 (*dmamp)->_dm_align = 8192; 1006 #endif 1007 1008 return (0); 1009 } 1010 1011 int 1012 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1013 bus_dma_tag_t t; 1014 bus_dmamap_t map; 1015 void *buf; 1016 bus_size_t buflen; 1017 struct proc *p; 1018 int flags; 1019 { 1020 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1021 volatile u_int32_t *ioctags; 1022 int error; 1023 1024 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 1025 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1026 if (error != 0) 1027 return (error); 1028 1029 /* allocate IO cache entries for this range */ 1030 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1031 for (;buflen > 0;) { 1032 *ioctags = VME_IOC_IC | VME_IOC_W; 1033 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1034 buflen -= VME_IOC_PAGESZ; 1035 } 1036 return (0); 1037 } 1038 1039 1040 void 1041 sparc_vme4m_dmamap_unload(t, map) 1042 bus_dma_tag_t t; 1043 bus_dmamap_t map; 1044 { 1045 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1046 volatile u_int32_t *flushregs; 1047 int len; 1048 1049 /* Flush VME IO cache */ 1050 len = map->dm_segs[0].ds_len; 1051 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1052 for (;len > 0;) { 1053 *flushregs = 0; 1054 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1055 len -= VME_IOC_PAGESZ; 1056 } 1057 /* Read a tag to synchronize the IOC flushes */ 1058 (*sc->sc_ioctags); 1059 1060 bus_dmamap_unload(sc->sc_dmatag, map); 1061 } 1062 1063 int 1064 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 1065 bus_dma_tag_t t; 1066 bus_size_t size, alignmnt, boundary; 1067 bus_dma_segment_t *segs; 1068 int nsegs; 1069 int *rsegs; 1070 int flags; 1071 { 1072 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1073 int error; 1074 1075 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 1076 segs, nsegs, rsegs, flags); 1077 if (error != 0) 1078 return (error); 1079 1080 return (0); 1081 } 1082 1083 void 1084 sparc_vme4m_dmamem_free(t, segs, nsegs) 1085 bus_dma_tag_t t; 1086 bus_dma_segment_t *segs; 1087 int nsegs; 1088 { 1089 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1090 1091 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 1092 } 1093 1094 void 1095 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1096 bus_dma_tag_t t; 1097 bus_dmamap_t map; 1098 bus_addr_t offset; 1099 bus_size_t len; 1100 int ops; 1101 { 1102 1103 /* 1104 * XXX Should perform cache flushes as necessary. 1105 */ 1106 } 1107 #endif /* SUN4M */ 1108 1109 int 1110 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1111 bus_dma_tag_t t; 1112 bus_dma_segment_t *segs; 1113 int nsegs; 1114 size_t size; 1115 caddr_t *kvap; 1116 int flags; 1117 { 1118 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 1119 1120 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1121 } 1122
Indexes created Tue Sep 23 21:09:50 GMT 2025