vme_machdep.c revision 1.21
1 /* $NetBSD: vme_machdep.c,v 1.21 1999/11/13 00:32:12 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/errno.h> 45 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/syslog.h> 49 50 #include <vm/vm.h> 51 52 #define _SPARC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 #include <sparc/sparc/iommuvar.h> 55 #include <machine/autoconf.h> 56 #include <machine/pmap.h> 57 #include <machine/oldmon.h> 58 #include <machine/cpu.h> 59 #include <machine/ctlreg.h> 60 61 #include <dev/vme/vmereg.h> 62 #include <dev/vme/vmevar.h> 63 64 #include <sparc/sparc/asm.h> 65 #include <sparc/sparc/vaddrs.h> 66 #include <sparc/sparc/cpuvar.h> 67 #include <sparc/dev/vmereg.h> 68 69 struct sparcvme_softc { 70 struct device sc_dev; /* base device */ 71 bus_space_tag_t sc_bustag; 72 bus_dma_tag_t sc_dmatag; 73 struct vmebusreg *sc_reg; /* VME control registers */ 74 struct vmebusvec *sc_vec; /* VME interrupt vector */ 75 struct rom_range *sc_range; /* ROM range property */ 76 int sc_nrange; 77 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 78 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 79 int (*sc_vmeintr) __P((void *)); 80 struct bootpath *sc_bp; 81 }; 82 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 83 84 /* autoconfiguration driver */ 85 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 87 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 88 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 89 #if defined(SUN4) 90 int vmeintr4 __P((void *)); 91 #endif 92 #if defined(SUN4M) 93 int vmeintr4m __P((void *)); 94 static int sparc_vme_error __P((void)); 95 #endif 96 97 98 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 99 vme_am_t, vme_datasize_t, 100 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 101 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 102 vme_datasize_t, vme_swap_t, 103 bus_space_tag_t *, bus_space_handle_t *, 104 vme_mapresc_t *)); 105 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 106 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 107 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 108 int (*) __P((void *)), void *)); 109 static void sparc_vme_intr_disestablish __P((void *, void *)); 110 111 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 112 vme_addr_t, bus_type_t *, bus_addr_t *)); 113 #if defined(SUN4M) 114 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 115 bus_size_t, bus_size_t, int)); 116 117 #endif 118 119 /* 120 * DMA functions. 121 */ 122 #if defined(SUN4) 123 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 124 bus_size_t, struct proc *, int)); 125 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 126 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 127 bus_addr_t, bus_size_t, int)); 128 129 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 130 bus_size_t, bus_size_t, bus_dma_segment_t *, 131 int, int *, int)); 132 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 133 bus_dma_segment_t *, int)); 134 #endif 135 136 #if defined(SUN4M) 137 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 138 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 139 140 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 141 bus_size_t, struct proc *, int)); 142 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 143 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 144 bus_addr_t, bus_size_t, int)); 145 146 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 147 bus_size_t, bus_size_t, bus_dma_segment_t *, 148 int, int *, int)); 149 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 150 bus_dma_segment_t *, int)); 151 #endif 152 153 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 154 int, size_t, caddr_t *, int)); 155 #if 0 156 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 157 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 158 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 159 bus_dma_segment_t *, int, int, int, int)); 160 #endif 161 162 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 163 164 struct cfattach vme_mainbus_ca = { 165 sizeof(struct sparcvme_softc), vmematch_mainbus, vmeattach_mainbus 166 }; 167 168 struct cfattach vme_iommu_ca = { 169 sizeof(struct sparcvme_softc), vmematch_iommu, vmeattach_iommu 170 }; 171 172 int (*vmeerr_handler) __P((void)); 173 174 #define VMEMOD_D32 0x40 /* ??? */ 175 176 /* If the PROM does not provide the `ranges' property, we make up our own */ 177 struct rom_range vmebus_translations[] = { 178 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 179 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 180 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 181 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 182 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 183 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 184 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 185 #undef _DS 186 }; 187 188 /* 189 * DMA on sun4 VME devices use the last MB of virtual space, which 190 * is mapped by hardware onto the first MB of VME space. 191 */ 192 struct extent *vme_dvmamap; 193 194 struct sparc_bus_space_tag sparc_vme_bus_tag = { 195 NULL, /* cookie */ 196 NULL, /* parent bus tag */ 197 NULL, /* bus_map */ 198 NULL, /* bus_unmap */ 199 NULL, /* bus_subregion */ 200 NULL /* barrier */ 201 }; 202 203 struct vme_chipset_tag sparc_vme_chipset_tag = { 204 NULL, 205 sparc_vme_map, 206 sparc_vme_unmap, 207 sparc_vme_probe, 208 sparc_vme_intr_map, 209 sparc_vme_intr_establish, 210 sparc_vme_intr_disestablish, 211 0, 0, 0 /* bus specific DMA stuff */ 212 }; 213 214 215 #if defined(SUN4) 216 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 217 NULL, /* cookie */ 218 _bus_dmamap_create, 219 _bus_dmamap_destroy, 220 sparc_vme4_dmamap_load, 221 _bus_dmamap_load_mbuf, 222 _bus_dmamap_load_uio, 223 _bus_dmamap_load_raw, 224 sparc_vme4_dmamap_unload, 225 sparc_vme4_dmamap_sync, 226 227 sparc_vme4_dmamem_alloc, 228 sparc_vme4_dmamem_free, 229 sparc_vme_dmamem_map, 230 _bus_dmamem_unmap, 231 _bus_dmamem_mmap 232 }; 233 #endif 234 235 #if defined(SUN4M) 236 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 237 NULL, /* cookie */ 238 sparc_vme4m_dmamap_create, 239 _bus_dmamap_destroy, 240 sparc_vme4m_dmamap_load, 241 _bus_dmamap_load_mbuf, 242 _bus_dmamap_load_uio, 243 _bus_dmamap_load_raw, 244 sparc_vme4m_dmamap_unload, 245 sparc_vme4m_dmamap_sync, 246 247 sparc_vme4m_dmamem_alloc, 248 sparc_vme4m_dmamem_free, 249 sparc_vme_dmamem_map, 250 _bus_dmamem_unmap, 251 _bus_dmamem_mmap 252 }; 253 #endif 254 255 256 int 257 vmematch_mainbus(parent, cf, aux) 258 struct device *parent; 259 struct cfdata *cf; 260 void *aux; 261 { 262 struct mainbus_attach_args *ma = aux; 263 264 if (!CPU_ISSUN4) 265 return (0); 266 267 return (strcmp("vme", ma->ma_name) == 0); 268 } 269 270 int 271 vmematch_iommu(parent, cf, aux) 272 struct device *parent; 273 struct cfdata *cf; 274 void *aux; 275 { 276 struct iommu_attach_args *ia = aux; 277 278 return (strcmp("vme", ia->iom_name) == 0); 279 } 280 281 282 void 283 vmeattach_mainbus(parent, self, aux) 284 struct device *parent, *self; 285 void *aux; 286 { 287 #if defined(SUN4) 288 struct mainbus_attach_args *ma = aux; 289 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 290 struct vmebus_attach_args vba; 291 292 if (self->dv_unit > 0) { 293 printf(" unsupported\n"); 294 return; 295 } 296 297 sc->sc_bustag = ma->ma_bustag; 298 sc->sc_dmatag = ma->ma_dmatag; 299 300 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 301 sc->sc_bp = ma->ma_bp + 1; 302 bootpath_store(1, sc->sc_bp); 303 } 304 305 /* VME interrupt entry point */ 306 sc->sc_vmeintr = vmeintr4; 307 308 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 309 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 310 311 #if 0 312 sparc_vme_bus_tag.parent = ma->ma_bustag; 313 vba.vba_bustag = &sparc_vme_bus_tag; 314 #endif 315 vba.va_vct = &sparc_vme_chipset_tag; 316 vba.va_bdt = &sparc_vme4_dma_tag; 317 vba.va_slaveconfig = 0; 318 319 /* Fall back to our own `range' construction */ 320 sc->sc_range = vmebus_translations; 321 sc->sc_nrange = 322 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 323 324 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 325 M_DEVBUF, 0, 0, EX_NOWAIT); 326 if (vme_dvmamap == NULL) 327 panic("vme: unable to allocate DVMA map"); 328 329 printf("\n"); 330 (void)config_found(self, &vba, 0); 331 332 bootpath_store(1, NULL); 333 #endif 334 return; 335 } 336 337 /* sun4m vmebus */ 338 void 339 vmeattach_iommu(parent, self, aux) 340 struct device *parent, *self; 341 void *aux; 342 { 343 #if defined(SUN4M) 344 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 345 struct iommu_attach_args *ia = aux; 346 struct vmebus_attach_args vba; 347 bus_space_handle_t bh; 348 int node; 349 int cline; 350 351 if (self->dv_unit > 0) { 352 printf(" unsupported\n"); 353 return; 354 } 355 356 sc->sc_bustag = ia->iom_bustag; 357 sc->sc_dmatag = ia->iom_dmatag; 358 359 /* VME interrupt entry point */ 360 sc->sc_vmeintr = vmeintr4m; 361 362 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 363 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 364 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 365 366 #if 0 367 vba.vba_bustag = &sparc_vme_bus_tag; 368 #endif 369 vba.va_vct = &sparc_vme_chipset_tag; 370 vba.va_bdt = &sparc_vme4m_dma_tag; 371 vba.va_slaveconfig = 0; 372 373 node = ia->iom_node; 374 375 /* 376 * Map VME control space 377 */ 378 if (ia->iom_nreg < 2) { 379 printf("%s: only %d register sets\n", self->dv_xname, 380 ia->iom_nreg); 381 return; 382 } 383 384 if (bus_space_map2(ia->iom_bustag, 385 (bus_type_t)ia->iom_reg[0].ior_iospace, 386 (bus_addr_t)ia->iom_reg[0].ior_pa, 387 (bus_size_t)ia->iom_reg[0].ior_size, 388 BUS_SPACE_MAP_LINEAR, 389 0, &bh) != 0) { 390 panic("%s: can't map vmebusreg", self->dv_xname); 391 } 392 sc->sc_reg = (struct vmebusreg *)bh; 393 394 if (bus_space_map2(ia->iom_bustag, 395 (bus_type_t)ia->iom_reg[1].ior_iospace, 396 (bus_addr_t)ia->iom_reg[1].ior_pa, 397 (bus_size_t)ia->iom_reg[1].ior_size, 398 BUS_SPACE_MAP_LINEAR, 399 0, &bh) != 0) { 400 panic("%s: can't map vmebusvec", self->dv_xname); 401 } 402 sc->sc_vec = (struct vmebusvec *)bh; 403 404 /* 405 * Map VME IO cache tags and flush control. 406 */ 407 if (bus_space_map2(ia->iom_bustag, 408 (bus_type_t)ia->iom_reg[1].ior_iospace, 409 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 410 VME_IOC_SIZE, 411 BUS_SPACE_MAP_LINEAR, 412 0, &bh) != 0) { 413 panic("%s: can't map IOC tags", self->dv_xname); 414 } 415 sc->sc_ioctags = (u_int32_t *)bh; 416 417 if (bus_space_map2(ia->iom_bustag, 418 (bus_type_t)ia->iom_reg[1].ior_iospace, 419 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 420 VME_IOC_SIZE, 421 BUS_SPACE_MAP_LINEAR, 422 0, &bh) != 0) { 423 panic("%s: can't map IOC flush registers", self->dv_xname); 424 } 425 sc->sc_iocflush = (u_int32_t *)bh; 426 427 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 428 429 /* 430 * Get "range" property. 431 */ 432 if (getprop(node, "ranges", sizeof(struct rom_range), 433 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 434 panic("%s: can't get ranges property", self->dv_xname); 435 } 436 437 sparcvme_sc = sc; 438 vmeerr_handler = sparc_vme_error; 439 440 /* 441 * Invalidate all IO-cache entries. 442 */ 443 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 444 sc->sc_ioctags[--cline] = 0; 445 } 446 447 /* Enable IO-cache */ 448 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 449 450 printf(": version 0x%x\n", 451 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 452 453 (void)config_found(self, &vba, 0); 454 #endif 455 } 456 457 #if defined(SUN4M) 458 static int 459 sparc_vme_error() 460 { 461 struct sparcvme_softc *sc = sparcvme_sc; 462 u_int32_t afsr, afpa; 463 char bits[64]; 464 465 afsr = sc->sc_reg->vmebus_afsr; 466 afpa = sc->sc_reg->vmebus_afar; 467 printf("VME error:\n\tAFSR %s\n", 468 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 469 printf("\taddress: 0x%x%x\n", afsr, afpa); 470 return (0); 471 } 472 #endif 473 474 int 475 vmebus_translate(sc, mod, addr, btp, bap) 476 struct sparcvme_softc *sc; 477 vme_am_t mod; 478 vme_addr_t addr; 479 bus_type_t *btp; 480 bus_addr_t *bap; 481 { 482 int i; 483 484 for (i = 0; i < sc->sc_nrange; i++) { 485 486 if (sc->sc_range[i].cspace != mod) 487 continue; 488 489 /* We've found the connection to the parent bus */ 490 *bap = sc->sc_range[i].poffset + addr; 491 *btp = sc->sc_range[i].pspace; 492 return (0); 493 } 494 return (ENOENT); 495 } 496 497 struct vmeprobe_myarg { 498 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 499 void *cbarg; 500 bus_space_tag_t tag; 501 int res; /* backwards */ 502 }; 503 504 static int vmeprobe_mycb __P((void *, void *)); 505 static int 506 vmeprobe_mycb(bh, arg) 507 void *bh, *arg; 508 { 509 struct vmeprobe_myarg *a = arg; 510 511 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 512 return (!a->res); 513 } 514 515 int 516 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 517 void *cookie; 518 vme_addr_t addr; 519 vme_size_t len; 520 vme_am_t mod; 521 vme_datasize_t datasize; 522 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 523 void *arg; 524 { 525 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 526 bus_type_t iospace; 527 bus_addr_t paddr; 528 bus_size_t size; 529 struct vmeprobe_myarg myarg; 530 int res, i; 531 532 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 533 return (EINVAL); 534 535 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 536 537 if (callback) { 538 myarg.cb = callback; 539 myarg.cbarg = arg; 540 myarg.tag = sc->sc_bustag; 541 myarg.res = 0; 542 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 543 0, vmeprobe_mycb, &myarg); 544 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 545 } 546 547 for (i = 0; i < len / size; i++) { 548 myarg.res = 0; 549 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 550 0, 0, 0); 551 if (res == 0) 552 return (EIO); 553 paddr += size; 554 } 555 return (0); 556 } 557 558 int 559 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 560 void *cookie; 561 vme_addr_t addr; 562 vme_size_t size; 563 vme_am_t mod; 564 vme_datasize_t datasize; 565 bus_space_tag_t *tp; 566 bus_space_handle_t *hp; 567 vme_mapresc_t *rp; 568 { 569 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 570 bus_type_t iospace; 571 bus_addr_t paddr; 572 int error; 573 574 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 575 if (error != 0) 576 return (error); 577 578 *tp = sc->sc_bustag; 579 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 580 } 581 582 int 583 sparc_vme_mmap_cookie(addr, mod, hp) 584 vme_addr_t addr; 585 vme_am_t mod; 586 bus_space_handle_t *hp; 587 { 588 struct sparcvme_softc *sc = sparcvme_sc; 589 bus_type_t iospace; 590 bus_addr_t paddr; 591 int error; 592 593 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 594 if (error != 0) 595 return (error); 596 597 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 598 } 599 600 #if defined(SUN4M) 601 void 602 sparc_vme4m_barrier(t, h, offset, size, flags) 603 bus_space_tag_t t; 604 bus_space_handle_t h; 605 bus_size_t offset; 606 bus_size_t size; 607 int flags; 608 { 609 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 610 611 /* Read async fault status to flush write-buffers */ 612 (*(volatile int *)&vbp->vmebus_afsr); 613 } 614 #endif 615 616 617 618 /* 619 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 620 */ 621 static int vme_ipl_to_pil[] = { 622 0, 623 2, 624 3, 625 5, 626 7, 627 9, 628 11, 629 13 630 }; 631 632 633 /* 634 * All VME device interrupts go through vmeintr(). This function reads 635 * the VME vector from the bus, then dispatches the device interrupt 636 * handler. All handlers for devices that map to the same Processor 637 * Interrupt Level (according to the table above) are on a linked list 638 * of `sparc_vme_intr_handle' structures. The head of which is passed 639 * down as the argument to `vmeintr(void *arg)'. 640 */ 641 struct sparc_vme_intr_handle { 642 struct intrhand ih; 643 struct sparc_vme_intr_handle *next; 644 int vec; /* VME interrupt vector */ 645 int pri; /* VME interrupt priority */ 646 struct sparcvme_softc *sc;/*XXX*/ 647 }; 648 649 #if defined(SUN4) 650 int 651 vmeintr4(arg) 652 void *arg; 653 { 654 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 655 int level, vec; 656 int i = 0; 657 658 level = (ihp->pri << 1) | 1; 659 660 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 661 662 if (vec == -1) { 663 printf("vme: spurious interrupt\n"); 664 return 1; /* XXX - pretend we handled it, for now */ 665 } 666 667 for (; ihp; ihp = ihp->next) 668 if (ihp->vec == vec && ihp->ih.ih_fun) 669 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 670 return (i); 671 } 672 #endif 673 674 #if defined(SUN4M) 675 int 676 vmeintr4m(arg) 677 void *arg; 678 { 679 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 680 int level, vec; 681 int i = 0; 682 683 level = (ihp->pri << 1) | 1; 684 685 #if 0 686 int pending; 687 688 /* Flush VME <=> Sbus write buffers */ 689 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 690 691 pending = *((int*)ICR_SI_PEND); 692 if ((pending & SINTR_VME(ihp->pri)) == 0) { 693 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 694 ihp->pri, pending); 695 return (0); 696 } 697 #endif 698 #if 0 699 /* Why gives this a bus timeout sometimes? */ 700 vec = ihp->sc->sc_vec->vmebusvec[level]; 701 #else 702 /* so, arrange to catch the fault... */ 703 { 704 extern struct user *proc0paddr; 705 extern int fkbyte __P((caddr_t, struct pcb *)); 706 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 707 struct pcb *xpcb; 708 u_long saveonfault; 709 int s; 710 711 s = splhigh(); 712 if (curproc == NULL) 713 xpcb = (struct pcb *)proc0paddr; 714 else 715 xpcb = &curproc->p_addr->u_pcb; 716 717 saveonfault = (u_long)xpcb->pcb_onfault; 718 vec = fkbyte(addr, xpcb); 719 xpcb->pcb_onfault = (caddr_t)saveonfault; 720 721 splx(s); 722 } 723 #endif 724 725 if (vec == -1) { 726 printf("vme: spurious interrupt: "); 727 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 728 *((int*)ICR_SI_PEND), 729 ihp->sc->sc_reg->vmebus_afsr, 730 ihp->sc->sc_reg->vmebus_afar); 731 return (1); /* XXX - pretend we handled it, for now */ 732 } 733 734 for (; ihp; ihp = ihp->next) 735 if (ihp->vec == vec && ihp->ih.ih_fun) 736 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 737 return (i); 738 } 739 #endif 740 741 int 742 sparc_vme_intr_map(cookie, level, vec, ihp) 743 void *cookie; 744 int level; 745 int vec; 746 vme_intr_handle_t *ihp; 747 { 748 struct sparc_vme_intr_handle *ih; 749 750 ih = (vme_intr_handle_t) 751 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 752 ih->pri = level; 753 ih->vec = vec; 754 ih->sc = cookie;/*XXX*/ 755 *ihp = ih; 756 return (0); 757 } 758 759 void * 760 sparc_vme_intr_establish(cookie, vih, pri, func, arg) 761 void *cookie; 762 vme_intr_handle_t vih; 763 int pri; 764 int (*func) __P((void *)); 765 void *arg; 766 { 767 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 768 struct sparc_vme_intr_handle *svih = 769 (struct sparc_vme_intr_handle *)vih; 770 struct intrhand *ih; 771 int level; 772 773 /* XXX pri == svih->pri ??? */ 774 775 /* Translate VME priority to processor IPL */ 776 level = vme_ipl_to_pil[svih->pri]; 777 778 svih->ih.ih_fun = func; 779 svih->ih.ih_arg = arg; 780 svih->next = NULL; 781 782 /* ensure the interrupt subsystem will call us at this level */ 783 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 784 if (ih->ih_fun == sc->sc_vmeintr) 785 break; 786 787 if (ih == NULL) { 788 ih = (struct intrhand *) 789 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 790 if (ih == NULL) 791 panic("vme_addirq"); 792 bzero(ih, sizeof *ih); 793 ih->ih_fun = sc->sc_vmeintr; 794 ih->ih_arg = vih; 795 intr_establish(level, ih); 796 } else { 797 svih->next = (vme_intr_handle_t)ih->ih_arg; 798 ih->ih_arg = vih; 799 } 800 return (NULL); 801 } 802 803 void 804 sparc_vme_unmap(cookie, resc) 805 void * cookie; 806 vme_mapresc_t resc; 807 { 808 /* Not implemented */ 809 panic("sparc_vme_unmap"); 810 } 811 812 void 813 sparc_vme_intr_disestablish(cookie, a) 814 void *cookie; 815 void *a; 816 { 817 /* Not implemented */ 818 panic("sparc_vme_intr_disestablish"); 819 } 820 821 822 823 /* 824 * VME DMA functions. 825 */ 826 827 #if defined(SUN4) 828 int 829 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 830 bus_dma_tag_t t; 831 bus_dmamap_t map; 832 void *buf; 833 bus_size_t buflen; 834 struct proc *p; 835 int flags; 836 { 837 bus_addr_t dvmaddr; 838 bus_size_t sgsize; 839 vaddr_t vaddr; 840 pmap_t pmap; 841 int pagesz = PAGE_SIZE; 842 int error; 843 844 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 845 map->_dm_boundary, 846 (flags & BUS_DMA_NOWAIT) == 0 847 ? EX_WAITOK 848 : EX_NOWAIT, 849 (u_long *)&dvmaddr); 850 if (error != 0) 851 return (error); 852 853 vaddr = (vaddr_t)buf; 854 map->dm_mapsize = buflen; 855 map->dm_nsegs = 1; 856 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 857 map->dm_segs[0].ds_len = buflen; 858 859 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 860 861 for (; buflen > 0; ) { 862 paddr_t pa; 863 /* 864 * Get the physical address for this page. 865 */ 866 (void) pmap_extract(pmap, vaddr, &pa); 867 868 /* 869 * Compute the segment size, and adjust counts. 870 */ 871 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 872 if (buflen < sgsize) 873 sgsize = buflen; 874 875 #ifdef notyet 876 if (have_iocache) 877 curaddr |= PG_IOC; 878 #endif 879 pmap_enter(pmap_kernel(), dvmaddr, 880 (pa & ~(pagesz-1)) | PMAP_NC, 881 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 882 883 dvmaddr += pagesz; 884 vaddr += sgsize; 885 buflen -= sgsize; 886 } 887 888 /* Adjust DVMA address to VME view */ 889 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 890 return (0); 891 } 892 893 void 894 sparc_vme4_dmamap_unload(t, map) 895 bus_dma_tag_t t; 896 bus_dmamap_t map; 897 { 898 bus_addr_t addr; 899 bus_size_t len; 900 901 /* Go from VME to CPU view */ 902 map->dm_segs[0].ds_addr += VME4_DVMA_BASE; 903 904 addr = map->dm_segs[0].ds_addr & ~PGOFSET; 905 len = round_page(map->dm_segs[0].ds_len); 906 907 /* Remove double-mapping in DVMA space */ 908 pmap_remove(pmap_kernel(), addr, addr + len); 909 910 /* Release DVMA space */ 911 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 912 printf("warning: %ld of DVMA space lost\n", len); 913 914 /* Mark the mappings as invalid. */ 915 map->dm_mapsize = 0; 916 map->dm_nsegs = 0; 917 } 918 919 int 920 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 921 bus_dma_tag_t t; 922 bus_size_t size, alignment, boundary; 923 bus_dma_segment_t *segs; 924 int nsegs; 925 int *rsegs; 926 int flags; 927 { 928 bus_addr_t dvmaddr; 929 struct pglist *mlist; 930 vm_page_t m; 931 paddr_t pa; 932 int error; 933 934 size = round_page(size); 935 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 936 segs, nsegs, rsegs, flags); 937 if (error != 0) 938 return (error); 939 940 if (extent_alloc(vme_dvmamap, size, alignment, boundary, 941 (flags & BUS_DMA_NOWAIT) == 0 ? EX_WAITOK : EX_NOWAIT, 942 (u_long *)&dvmaddr) != 0) 943 return (ENOMEM); 944 945 /* 946 * Compute the location, size, and number of segments actually 947 * returned by the VM code. 948 */ 949 segs[0].ds_addr = dvmaddr - VME4_DVMA_BASE; 950 segs[0].ds_len = size; 951 *rsegs = 1; 952 953 /* Map memory into DVMA space */ 954 mlist = segs[0]._ds_mlist; 955 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 956 pa = VM_PAGE_TO_PHYS(m); 957 958 #ifdef notyet 959 if (have_iocache) 960 pa |= PG_IOC; 961 #endif 962 pmap_enter(pmap_kernel(), dvmaddr, pa | PMAP_NC, 963 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 964 dvmaddr += PAGE_SIZE; 965 } 966 967 return (0); 968 } 969 970 void 971 sparc_vme4_dmamem_free(t, segs, nsegs) 972 bus_dma_tag_t t; 973 bus_dma_segment_t *segs; 974 int nsegs; 975 { 976 bus_addr_t addr; 977 bus_size_t len; 978 979 addr = segs[0].ds_addr + VME4_DVMA_BASE; 980 len = round_page(segs[0].ds_len); 981 982 /* Remove DVMA kernel map */ 983 pmap_remove(pmap_kernel(), addr, addr + len); 984 985 /* Release DVMA address range */ 986 if (extent_free(vme_dvmamap, addr, len, EX_NOWAIT) != 0) 987 printf("warning: %ld of DVMA space lost\n", len); 988 989 /* 990 * Return the list of pages back to the VM system. 991 */ 992 _bus_dmamem_free_common(t, segs, nsegs); 993 } 994 995 void 996 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 997 bus_dma_tag_t t; 998 bus_dmamap_t map; 999 bus_addr_t offset; 1000 bus_size_t len; 1001 int ops; 1002 { 1003 1004 /* 1005 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 1006 * Currently the cache is flushed in bus_dma_load()... 1007 */ 1008 } 1009 #endif /* SUN4 */ 1010 1011 #if defined(SUN4M) 1012 static int 1013 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 1014 bus_dma_tag_t t; 1015 bus_size_t size; 1016 int nsegments; 1017 bus_size_t maxsegsz; 1018 bus_size_t boundary; 1019 int flags; 1020 bus_dmamap_t *dmamp; 1021 { 1022 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1023 int error; 1024 1025 /* XXX - todo: allocate DVMA addresses from assigned ranges: 1026 upper 8MB for A32 space; upper 1MB for A24 space */ 1027 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1028 boundary, flags, dmamp); 1029 if (error != 0) 1030 return (error); 1031 1032 #if 0 1033 /* VME DVMA addresses must always be 8K aligned */ 1034 (*dmamp)->_dm_align = 8192; 1035 #endif 1036 1037 return (0); 1038 } 1039 1040 int 1041 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1042 bus_dma_tag_t t; 1043 bus_dmamap_t map; 1044 void *buf; 1045 bus_size_t buflen; 1046 struct proc *p; 1047 int flags; 1048 { 1049 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1050 volatile u_int32_t *ioctags; 1051 int error; 1052 1053 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 1054 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1055 if (error != 0) 1056 return (error); 1057 1058 /* allocate IO cache entries for this range */ 1059 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1060 for (;buflen > 0;) { 1061 *ioctags = VME_IOC_IC | VME_IOC_W; 1062 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1063 buflen -= VME_IOC_PAGESZ; 1064 } 1065 return (0); 1066 } 1067 1068 1069 void 1070 sparc_vme4m_dmamap_unload(t, map) 1071 bus_dma_tag_t t; 1072 bus_dmamap_t map; 1073 { 1074 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1075 volatile u_int32_t *flushregs; 1076 int len; 1077 1078 /* Flush VME IO cache */ 1079 len = map->dm_segs[0].ds_len; 1080 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1081 for (;len > 0;) { 1082 *flushregs = 0; 1083 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1084 len -= VME_IOC_PAGESZ; 1085 } 1086 /* Read a tag to synchronize the IOC flushes */ 1087 (*sc->sc_ioctags); 1088 1089 bus_dmamap_unload(sc->sc_dmatag, map); 1090 } 1091 1092 int 1093 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 1094 bus_dma_tag_t t; 1095 bus_size_t size, alignmnt, boundary; 1096 bus_dma_segment_t *segs; 1097 int nsegs; 1098 int *rsegs; 1099 int flags; 1100 { 1101 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1102 int error; 1103 1104 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 1105 segs, nsegs, rsegs, flags); 1106 if (error != 0) 1107 return (error); 1108 1109 return (0); 1110 } 1111 1112 void 1113 sparc_vme4m_dmamem_free(t, segs, nsegs) 1114 bus_dma_tag_t t; 1115 bus_dma_segment_t *segs; 1116 int nsegs; 1117 { 1118 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1119 1120 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 1121 } 1122 1123 void 1124 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1125 bus_dma_tag_t t; 1126 bus_dmamap_t map; 1127 bus_addr_t offset; 1128 bus_size_t len; 1129 int ops; 1130 { 1131 1132 /* 1133 * XXX Should perform cache flushes as necessary. 1134 */ 1135 } 1136 #endif /* SUN4M */ 1137 1138 int 1139 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1140 bus_dma_tag_t t; 1141 bus_dma_segment_t *segs; 1142 int nsegs; 1143 size_t size; 1144 caddr_t *kvap; 1145 int flags; 1146 { 1147 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1148 1149 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1150 } 1151
Indexes created Tue Sep 23 23:09:58 GMT 2025