vme_machdep.c revision 1.23
1 /* $NetBSD: vme_machdep.c,v 1.23 2000/05/09 22:39:36 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/errno.h> 45 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/syslog.h> 49 50 #include <vm/vm.h> 51 52 #define _SPARC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 #include <sparc/sparc/iommuvar.h> 55 #include <machine/autoconf.h> 56 #include <machine/pmap.h> 57 #include <machine/oldmon.h> 58 #include <machine/cpu.h> 59 #include <machine/ctlreg.h> 60 61 #include <dev/vme/vmereg.h> 62 #include <dev/vme/vmevar.h> 63 64 #include <sparc/sparc/asm.h> 65 #include <sparc/sparc/vaddrs.h> 66 #include <sparc/sparc/cpuvar.h> 67 #include <sparc/dev/vmereg.h> 68 69 struct sparcvme_softc { 70 struct device sc_dev; /* base device */ 71 bus_space_tag_t sc_bustag; 72 bus_dma_tag_t sc_dmatag; 73 struct vmebusreg *sc_reg; /* VME control registers */ 74 struct vmebusvec *sc_vec; /* VME interrupt vector */ 75 struct rom_range *sc_range; /* ROM range property */ 76 int sc_nrange; 77 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 78 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 79 int (*sc_vmeintr) __P((void *)); 80 }; 81 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 82 83 /* autoconfiguration driver */ 84 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 85 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 86 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 87 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 88 #if defined(SUN4) 89 int vmeintr4 __P((void *)); 90 #endif 91 #if defined(SUN4M) 92 int vmeintr4m __P((void *)); 93 static int sparc_vme_error __P((void)); 94 #endif 95 96 97 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 98 vme_am_t, vme_datasize_t, 99 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 100 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 101 vme_datasize_t, vme_swap_t, 102 bus_space_tag_t *, bus_space_handle_t *, 103 vme_mapresc_t *)); 104 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 105 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 106 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 107 int (*) __P((void *)), void *)); 108 static void sparc_vme_intr_disestablish __P((void *, void *)); 109 110 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 111 vme_addr_t, bus_type_t *, bus_addr_t *)); 112 #if defined(SUN4M) 113 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 114 bus_size_t, bus_size_t, int)); 115 116 #endif 117 118 /* 119 * DMA functions. 120 */ 121 #if defined(SUN4) 122 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 123 bus_size_t, struct proc *, int)); 124 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 125 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 126 bus_addr_t, bus_size_t, int)); 127 #endif 128 129 #if defined(SUN4M) 130 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 131 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 132 133 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 134 bus_size_t, struct proc *, int)); 135 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 136 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 137 bus_addr_t, bus_size_t, int)); 138 #endif 139 140 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 141 int, size_t, caddr_t *, int)); 142 #if 0 143 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 144 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 145 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 146 bus_dma_segment_t *, int, int, int, int)); 147 #endif 148 149 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 150 151 struct cfattach vme_mainbus_ca = { 152 sizeof(struct sparcvme_softc), vmematch_mainbus, vmeattach_mainbus 153 }; 154 155 struct cfattach vme_iommu_ca = { 156 sizeof(struct sparcvme_softc), vmematch_iommu, vmeattach_iommu 157 }; 158 159 int (*vmeerr_handler) __P((void)); 160 161 #define VMEMOD_D32 0x40 /* ??? */ 162 163 /* If the PROM does not provide the `ranges' property, we make up our own */ 164 struct rom_range vmebus_translations[] = { 165 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 166 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 167 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 168 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 169 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 170 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 171 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 172 #undef _DS 173 }; 174 175 /* 176 * DMA on sun4 VME devices use the last MB of virtual space, which 177 * is mapped by hardware onto the first MB of VME space. 178 */ 179 struct extent *vme_dvmamap; 180 181 struct sparc_bus_space_tag sparc_vme_bus_tag = { 182 NULL, /* cookie */ 183 NULL, /* parent bus tag */ 184 NULL, /* bus_map */ 185 NULL, /* bus_unmap */ 186 NULL, /* bus_subregion */ 187 NULL /* barrier */ 188 }; 189 190 struct vme_chipset_tag sparc_vme_chipset_tag = { 191 NULL, 192 sparc_vme_map, 193 sparc_vme_unmap, 194 sparc_vme_probe, 195 sparc_vme_intr_map, 196 sparc_vme_intr_establish, 197 sparc_vme_intr_disestablish, 198 0, 0, 0 /* bus specific DMA stuff */ 199 }; 200 201 202 #if defined(SUN4) 203 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 204 NULL, /* cookie */ 205 _bus_dmamap_create, 206 _bus_dmamap_destroy, 207 sparc_vme4_dmamap_load, 208 _bus_dmamap_load_mbuf, 209 _bus_dmamap_load_uio, 210 _bus_dmamap_load_raw, 211 sparc_vme4_dmamap_unload, 212 sparc_vme4_dmamap_sync, 213 214 _bus_dmamem_alloc, 215 _bus_dmamem_free, 216 sparc_vme_dmamem_map, 217 _bus_dmamem_unmap, 218 _bus_dmamem_mmap 219 }; 220 #endif 221 222 #if defined(SUN4M) 223 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 224 NULL, /* cookie */ 225 sparc_vme4m_dmamap_create, 226 _bus_dmamap_destroy, 227 sparc_vme4m_dmamap_load, 228 _bus_dmamap_load_mbuf, 229 _bus_dmamap_load_uio, 230 _bus_dmamap_load_raw, 231 sparc_vme4m_dmamap_unload, 232 sparc_vme4m_dmamap_sync, 233 234 _bus_dmamem_alloc, 235 _bus_dmamem_free, 236 sparc_vme_dmamem_map, 237 _bus_dmamem_unmap, 238 _bus_dmamem_mmap 239 }; 240 #endif 241 242 243 int 244 vmematch_mainbus(parent, cf, aux) 245 struct device *parent; 246 struct cfdata *cf; 247 void *aux; 248 { 249 struct mainbus_attach_args *ma = aux; 250 251 if (!CPU_ISSUN4) 252 return (0); 253 254 return (strcmp("vme", ma->ma_name) == 0); 255 } 256 257 int 258 vmematch_iommu(parent, cf, aux) 259 struct device *parent; 260 struct cfdata *cf; 261 void *aux; 262 { 263 struct iommu_attach_args *ia = aux; 264 265 return (strcmp("vme", ia->iom_name) == 0); 266 } 267 268 269 void 270 vmeattach_mainbus(parent, self, aux) 271 struct device *parent, *self; 272 void *aux; 273 { 274 #if defined(SUN4) 275 struct mainbus_attach_args *ma = aux; 276 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 277 struct vmebus_attach_args vba; 278 279 if (self->dv_unit > 0) { 280 printf(" unsupported\n"); 281 return; 282 } 283 284 sc->sc_bustag = ma->ma_bustag; 285 sc->sc_dmatag = ma->ma_dmatag; 286 287 /* VME interrupt entry point */ 288 sc->sc_vmeintr = vmeintr4; 289 290 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 291 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 292 293 #if 0 294 sparc_vme_bus_tag.parent = ma->ma_bustag; 295 vba.vba_bustag = &sparc_vme_bus_tag; 296 #endif 297 vba.va_vct = &sparc_vme_chipset_tag; 298 vba.va_bdt = &sparc_vme4_dma_tag; 299 vba.va_slaveconfig = 0; 300 301 /* Fall back to our own `range' construction */ 302 sc->sc_range = vmebus_translations; 303 sc->sc_nrange = 304 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 305 306 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 307 M_DEVBUF, 0, 0, EX_NOWAIT); 308 if (vme_dvmamap == NULL) 309 panic("vme: unable to allocate DVMA map"); 310 311 printf("\n"); 312 (void)config_found(self, &vba, 0); 313 314 #endif 315 return; 316 } 317 318 /* sun4m vmebus */ 319 void 320 vmeattach_iommu(parent, self, aux) 321 struct device *parent, *self; 322 void *aux; 323 { 324 #if defined(SUN4M) 325 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 326 struct iommu_attach_args *ia = aux; 327 struct vmebus_attach_args vba; 328 bus_space_handle_t bh; 329 int node; 330 int cline; 331 332 if (self->dv_unit > 0) { 333 printf(" unsupported\n"); 334 return; 335 } 336 337 sc->sc_bustag = ia->iom_bustag; 338 sc->sc_dmatag = ia->iom_dmatag; 339 340 /* VME interrupt entry point */ 341 sc->sc_vmeintr = vmeintr4m; 342 343 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 344 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 345 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 346 347 #if 0 348 vba.vba_bustag = &sparc_vme_bus_tag; 349 #endif 350 vba.va_vct = &sparc_vme_chipset_tag; 351 vba.va_bdt = &sparc_vme4m_dma_tag; 352 vba.va_slaveconfig = 0; 353 354 node = ia->iom_node; 355 356 /* 357 * Map VME control space 358 */ 359 if (ia->iom_nreg < 2) { 360 printf("%s: only %d register sets\n", self->dv_xname, 361 ia->iom_nreg); 362 return; 363 } 364 365 if (bus_space_map2(ia->iom_bustag, 366 (bus_type_t)ia->iom_reg[0].ior_iospace, 367 (bus_addr_t)ia->iom_reg[0].ior_pa, 368 (bus_size_t)ia->iom_reg[0].ior_size, 369 BUS_SPACE_MAP_LINEAR, 370 0, &bh) != 0) { 371 panic("%s: can't map vmebusreg", self->dv_xname); 372 } 373 sc->sc_reg = (struct vmebusreg *)bh; 374 375 if (bus_space_map2(ia->iom_bustag, 376 (bus_type_t)ia->iom_reg[1].ior_iospace, 377 (bus_addr_t)ia->iom_reg[1].ior_pa, 378 (bus_size_t)ia->iom_reg[1].ior_size, 379 BUS_SPACE_MAP_LINEAR, 380 0, &bh) != 0) { 381 panic("%s: can't map vmebusvec", self->dv_xname); 382 } 383 sc->sc_vec = (struct vmebusvec *)bh; 384 385 /* 386 * Map VME IO cache tags and flush control. 387 */ 388 if (bus_space_map2(ia->iom_bustag, 389 (bus_type_t)ia->iom_reg[1].ior_iospace, 390 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 391 VME_IOC_SIZE, 392 BUS_SPACE_MAP_LINEAR, 393 0, &bh) != 0) { 394 panic("%s: can't map IOC tags", self->dv_xname); 395 } 396 sc->sc_ioctags = (u_int32_t *)bh; 397 398 if (bus_space_map2(ia->iom_bustag, 399 (bus_type_t)ia->iom_reg[1].ior_iospace, 400 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 401 VME_IOC_SIZE, 402 BUS_SPACE_MAP_LINEAR, 403 0, &bh) != 0) { 404 panic("%s: can't map IOC flush registers", self->dv_xname); 405 } 406 sc->sc_iocflush = (u_int32_t *)bh; 407 408 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 409 410 /* 411 * Get "range" property. 412 */ 413 if (getprop(node, "ranges", sizeof(struct rom_range), 414 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 415 panic("%s: can't get ranges property", self->dv_xname); 416 } 417 418 sparcvme_sc = sc; 419 vmeerr_handler = sparc_vme_error; 420 421 /* 422 * Invalidate all IO-cache entries. 423 */ 424 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 425 sc->sc_ioctags[--cline] = 0; 426 } 427 428 /* Enable IO-cache */ 429 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 430 431 printf(": version 0x%x\n", 432 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 433 434 (void)config_found(self, &vba, 0); 435 #endif 436 } 437 438 #if defined(SUN4M) 439 static int 440 sparc_vme_error() 441 { 442 struct sparcvme_softc *sc = sparcvme_sc; 443 u_int32_t afsr, afpa; 444 char bits[64]; 445 446 afsr = sc->sc_reg->vmebus_afsr; 447 afpa = sc->sc_reg->vmebus_afar; 448 printf("VME error:\n\tAFSR %s\n", 449 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 450 printf("\taddress: 0x%x%x\n", afsr, afpa); 451 return (0); 452 } 453 #endif 454 455 int 456 vmebus_translate(sc, mod, addr, btp, bap) 457 struct sparcvme_softc *sc; 458 vme_am_t mod; 459 vme_addr_t addr; 460 bus_type_t *btp; 461 bus_addr_t *bap; 462 { 463 int i; 464 465 for (i = 0; i < sc->sc_nrange; i++) { 466 467 if (sc->sc_range[i].cspace != mod) 468 continue; 469 470 /* We've found the connection to the parent bus */ 471 *bap = sc->sc_range[i].poffset + addr; 472 *btp = sc->sc_range[i].pspace; 473 return (0); 474 } 475 return (ENOENT); 476 } 477 478 struct vmeprobe_myarg { 479 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 480 void *cbarg; 481 bus_space_tag_t tag; 482 int res; /* backwards */ 483 }; 484 485 static int vmeprobe_mycb __P((void *, void *)); 486 static int 487 vmeprobe_mycb(bh, arg) 488 void *bh, *arg; 489 { 490 struct vmeprobe_myarg *a = arg; 491 492 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 493 return (!a->res); 494 } 495 496 int 497 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 498 void *cookie; 499 vme_addr_t addr; 500 vme_size_t len; 501 vme_am_t mod; 502 vme_datasize_t datasize; 503 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 504 void *arg; 505 { 506 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 507 bus_type_t iospace; 508 bus_addr_t paddr; 509 bus_size_t size; 510 struct vmeprobe_myarg myarg; 511 int res, i; 512 513 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 514 return (EINVAL); 515 516 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 517 518 if (callback) { 519 myarg.cb = callback; 520 myarg.cbarg = arg; 521 myarg.tag = sc->sc_bustag; 522 myarg.res = 0; 523 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 524 0, vmeprobe_mycb, &myarg); 525 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 526 } 527 528 for (i = 0; i < len / size; i++) { 529 myarg.res = 0; 530 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 531 0, 0, 0); 532 if (res == 0) 533 return (EIO); 534 paddr += size; 535 } 536 return (0); 537 } 538 539 int 540 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 541 void *cookie; 542 vme_addr_t addr; 543 vme_size_t size; 544 vme_am_t mod; 545 vme_datasize_t datasize; 546 bus_space_tag_t *tp; 547 bus_space_handle_t *hp; 548 vme_mapresc_t *rp; 549 { 550 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 551 bus_type_t iospace; 552 bus_addr_t paddr; 553 int error; 554 555 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 556 if (error != 0) 557 return (error); 558 559 *tp = sc->sc_bustag; 560 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 561 } 562 563 int 564 sparc_vme_mmap_cookie(addr, mod, hp) 565 vme_addr_t addr; 566 vme_am_t mod; 567 bus_space_handle_t *hp; 568 { 569 struct sparcvme_softc *sc = sparcvme_sc; 570 bus_type_t iospace; 571 bus_addr_t paddr; 572 int error; 573 574 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 575 if (error != 0) 576 return (error); 577 578 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 579 } 580 581 #if defined(SUN4M) 582 void 583 sparc_vme4m_barrier(t, h, offset, size, flags) 584 bus_space_tag_t t; 585 bus_space_handle_t h; 586 bus_size_t offset; 587 bus_size_t size; 588 int flags; 589 { 590 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 591 592 /* Read async fault status to flush write-buffers */ 593 (*(volatile int *)&vbp->vmebus_afsr); 594 } 595 #endif 596 597 598 599 /* 600 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 601 */ 602 static int vme_ipl_to_pil[] = { 603 0, 604 2, 605 3, 606 5, 607 7, 608 9, 609 11, 610 13 611 }; 612 613 614 /* 615 * All VME device interrupts go through vmeintr(). This function reads 616 * the VME vector from the bus, then dispatches the device interrupt 617 * handler. All handlers for devices that map to the same Processor 618 * Interrupt Level (according to the table above) are on a linked list 619 * of `sparc_vme_intr_handle' structures. The head of which is passed 620 * down as the argument to `vmeintr(void *arg)'. 621 */ 622 struct sparc_vme_intr_handle { 623 struct intrhand ih; 624 struct sparc_vme_intr_handle *next; 625 int vec; /* VME interrupt vector */ 626 int pri; /* VME interrupt priority */ 627 struct sparcvme_softc *sc;/*XXX*/ 628 }; 629 630 #if defined(SUN4) 631 int 632 vmeintr4(arg) 633 void *arg; 634 { 635 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 636 int level, vec; 637 int i = 0; 638 639 level = (ihp->pri << 1) | 1; 640 641 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 642 643 if (vec == -1) { 644 printf("vme: spurious interrupt\n"); 645 return 1; /* XXX - pretend we handled it, for now */ 646 } 647 648 for (; ihp; ihp = ihp->next) 649 if (ihp->vec == vec && ihp->ih.ih_fun) 650 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 651 return (i); 652 } 653 #endif 654 655 #if defined(SUN4M) 656 int 657 vmeintr4m(arg) 658 void *arg; 659 { 660 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 661 int level, vec; 662 int i = 0; 663 664 level = (ihp->pri << 1) | 1; 665 666 #if 0 667 int pending; 668 669 /* Flush VME <=> Sbus write buffers */ 670 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 671 672 pending = *((int*)ICR_SI_PEND); 673 if ((pending & SINTR_VME(ihp->pri)) == 0) { 674 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 675 ihp->pri, pending); 676 return (0); 677 } 678 #endif 679 #if 0 680 /* Why gives this a bus timeout sometimes? */ 681 vec = ihp->sc->sc_vec->vmebusvec[level]; 682 #else 683 /* so, arrange to catch the fault... */ 684 { 685 extern struct user *proc0paddr; 686 extern int fkbyte __P((caddr_t, struct pcb *)); 687 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 688 struct pcb *xpcb; 689 u_long saveonfault; 690 int s; 691 692 s = splhigh(); 693 if (curproc == NULL) 694 xpcb = (struct pcb *)proc0paddr; 695 else 696 xpcb = &curproc->p_addr->u_pcb; 697 698 saveonfault = (u_long)xpcb->pcb_onfault; 699 vec = fkbyte(addr, xpcb); 700 xpcb->pcb_onfault = (caddr_t)saveonfault; 701 702 splx(s); 703 } 704 #endif 705 706 if (vec == -1) { 707 printf("vme: spurious interrupt: "); 708 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 709 *((int*)ICR_SI_PEND), 710 ihp->sc->sc_reg->vmebus_afsr, 711 ihp->sc->sc_reg->vmebus_afar); 712 return (1); /* XXX - pretend we handled it, for now */ 713 } 714 715 for (; ihp; ihp = ihp->next) 716 if (ihp->vec == vec && ihp->ih.ih_fun) 717 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 718 return (i); 719 } 720 #endif 721 722 int 723 sparc_vme_intr_map(cookie, level, vec, ihp) 724 void *cookie; 725 int level; 726 int vec; 727 vme_intr_handle_t *ihp; 728 { 729 struct sparc_vme_intr_handle *ih; 730 731 ih = (vme_intr_handle_t) 732 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 733 ih->pri = level; 734 ih->vec = vec; 735 ih->sc = cookie;/*XXX*/ 736 *ihp = ih; 737 return (0); 738 } 739 740 void * 741 sparc_vme_intr_establish(cookie, vih, pri, func, arg) 742 void *cookie; 743 vme_intr_handle_t vih; 744 int pri; 745 int (*func) __P((void *)); 746 void *arg; 747 { 748 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 749 struct sparc_vme_intr_handle *svih = 750 (struct sparc_vme_intr_handle *)vih; 751 struct intrhand *ih; 752 int level; 753 754 /* XXX pri == svih->pri ??? */ 755 756 /* Translate VME priority to processor IPL */ 757 level = vme_ipl_to_pil[svih->pri]; 758 759 svih->ih.ih_fun = func; 760 svih->ih.ih_arg = arg; 761 svih->next = NULL; 762 763 /* ensure the interrupt subsystem will call us at this level */ 764 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 765 if (ih->ih_fun == sc->sc_vmeintr) 766 break; 767 768 if (ih == NULL) { 769 ih = (struct intrhand *) 770 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 771 if (ih == NULL) 772 panic("vme_addirq"); 773 bzero(ih, sizeof *ih); 774 ih->ih_fun = sc->sc_vmeintr; 775 ih->ih_arg = vih; 776 intr_establish(level, ih); 777 } else { 778 svih->next = (vme_intr_handle_t)ih->ih_arg; 779 ih->ih_arg = vih; 780 } 781 return (NULL); 782 } 783 784 void 785 sparc_vme_unmap(cookie, resc) 786 void * cookie; 787 vme_mapresc_t resc; 788 { 789 /* Not implemented */ 790 panic("sparc_vme_unmap"); 791 } 792 793 void 794 sparc_vme_intr_disestablish(cookie, a) 795 void *cookie; 796 void *a; 797 { 798 /* Not implemented */ 799 panic("sparc_vme_intr_disestablish"); 800 } 801 802 803 804 /* 805 * VME DMA functions. 806 */ 807 808 #if defined(SUN4) 809 int 810 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 811 bus_dma_tag_t t; 812 bus_dmamap_t map; 813 void *buf; 814 bus_size_t buflen; 815 struct proc *p; 816 int flags; 817 { 818 bus_addr_t dvmaddr; 819 bus_size_t sgsize; 820 vaddr_t vaddr; 821 pmap_t pmap; 822 int pagesz = PAGE_SIZE; 823 int error; 824 825 error = extent_alloc(vme_dvmamap, round_page(buflen), NBPG, 826 map->_dm_boundary, 827 (flags & BUS_DMA_NOWAIT) == 0 828 ? EX_WAITOK 829 : EX_NOWAIT, 830 (u_long *)&dvmaddr); 831 if (error != 0) 832 return (error); 833 834 vaddr = (vaddr_t)buf; 835 map->dm_mapsize = buflen; 836 map->dm_nsegs = 1; 837 map->dm_segs[0].ds_addr = dvmaddr + (vaddr & PGOFSET); 838 map->dm_segs[0].ds_len = buflen; 839 840 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 841 842 for (; buflen > 0; ) { 843 paddr_t pa; 844 /* 845 * Get the physical address for this page. 846 */ 847 (void) pmap_extract(pmap, vaddr, &pa); 848 849 /* 850 * Compute the segment size, and adjust counts. 851 */ 852 sgsize = pagesz - ((u_long)vaddr & (pagesz - 1)); 853 if (buflen < sgsize) 854 sgsize = buflen; 855 856 #ifdef notyet 857 if (have_iocache) 858 curaddr |= PG_IOC; 859 #endif 860 pmap_enter(pmap_kernel(), dvmaddr, 861 (pa & ~(pagesz-1)) | PMAP_NC, 862 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 863 864 dvmaddr += pagesz; 865 vaddr += sgsize; 866 buflen -= sgsize; 867 } 868 869 /* Adjust DVMA address to VME view */ 870 map->dm_segs[0].ds_addr -= VME4_DVMA_BASE; 871 return (0); 872 } 873 874 void 875 sparc_vme4_dmamap_unload(t, map) 876 bus_dma_tag_t t; 877 bus_dmamap_t map; 878 { 879 bus_dma_segment_t *segs = map->dm_segs; 880 int nsegs = map->dm_nsegs; 881 bus_addr_t dva; 882 bus_size_t len; 883 int i; 884 885 for (i = 0; i < nsegs; i++) { 886 /* Go from VME to CPU view */ 887 dva = segs[i].ds_addr + VME4_DVMA_BASE; 888 889 dva &= ~PGOFSET; 890 len = round_page(segs[i].ds_len); 891 892 /* Remove double-mapping in DVMA space */ 893 pmap_remove(pmap_kernel(), dva, dva + len); 894 895 /* Release DVMA space */ 896 if (extent_free(vme_dvmamap, dva, len, EX_NOWAIT) != 0) 897 printf("warning: %ld of DVMA space lost\n", len); 898 } 899 900 /* Mark the mappings as invalid. */ 901 map->dm_mapsize = 0; 902 map->dm_nsegs = 0; 903 } 904 905 void 906 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 907 bus_dma_tag_t t; 908 bus_dmamap_t map; 909 bus_addr_t offset; 910 bus_size_t len; 911 int ops; 912 { 913 914 /* 915 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 916 * Currently the cache is flushed in bus_dma_load()... 917 */ 918 } 919 #endif /* SUN4 */ 920 921 #if defined(SUN4M) 922 static int 923 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 924 bus_dma_tag_t t; 925 bus_size_t size; 926 int nsegments; 927 bus_size_t maxsegsz; 928 bus_size_t boundary; 929 int flags; 930 bus_dmamap_t *dmamp; 931 { 932 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 933 int error; 934 935 /* XXX - todo: allocate DVMA addresses from assigned ranges: 936 upper 8MB for A32 space; upper 1MB for A24 space */ 937 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 938 boundary, flags, dmamp); 939 if (error != 0) 940 return (error); 941 942 #if 0 943 /* VME DVMA addresses must always be 8K aligned */ 944 (*dmamp)->_dm_align = 8192; 945 #endif 946 947 return (0); 948 } 949 950 int 951 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 952 bus_dma_tag_t t; 953 bus_dmamap_t map; 954 void *buf; 955 bus_size_t buflen; 956 struct proc *p; 957 int flags; 958 { 959 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 960 volatile u_int32_t *ioctags; 961 int error; 962 963 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 964 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 965 if (error != 0) 966 return (error); 967 968 /* allocate IO cache entries for this range */ 969 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 970 for (;buflen > 0;) { 971 *ioctags = VME_IOC_IC | VME_IOC_W; 972 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 973 buflen -= VME_IOC_PAGESZ; 974 } 975 return (0); 976 } 977 978 979 void 980 sparc_vme4m_dmamap_unload(t, map) 981 bus_dma_tag_t t; 982 bus_dmamap_t map; 983 { 984 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 985 volatile u_int32_t *flushregs; 986 int len; 987 988 /* Flush VME IO cache */ 989 len = map->dm_segs[0].ds_len; 990 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 991 for (;len > 0;) { 992 *flushregs = 0; 993 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 994 len -= VME_IOC_PAGESZ; 995 } 996 /* Read a tag to synchronize the IOC flushes */ 997 (*sc->sc_ioctags); 998 999 bus_dmamap_unload(sc->sc_dmatag, map); 1000 } 1001 1002 void 1003 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1004 bus_dma_tag_t t; 1005 bus_dmamap_t map; 1006 bus_addr_t offset; 1007 bus_size_t len; 1008 int ops; 1009 { 1010 1011 /* 1012 * XXX Should perform cache flushes as necessary. 1013 */ 1014 } 1015 #endif /* SUN4M */ 1016 1017 int 1018 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1019 bus_dma_tag_t t; 1020 bus_dma_segment_t *segs; 1021 int nsegs; 1022 size_t size; 1023 caddr_t *kvap; 1024 int flags; 1025 { 1026 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1027 1028 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1029 } 1030
Indexes created Wed Sep 24 05:09:52 GMT 2025