vme_machdep.c revision 1.26
1 /* $NetBSD: vme_machdep.c,v 1.26 2000/06/25 13:07:34 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/errno.h> 45 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/syslog.h> 49 50 #include <vm/vm.h> 51 52 #define _SPARC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 #include <sparc/sparc/iommuvar.h> 55 #include <machine/autoconf.h> 56 #include <machine/pmap.h> 57 #include <machine/oldmon.h> 58 #include <machine/cpu.h> 59 #include <machine/ctlreg.h> 60 61 #include <dev/vme/vmereg.h> 62 #include <dev/vme/vmevar.h> 63 64 #include <sparc/sparc/asm.h> 65 #include <sparc/sparc/vaddrs.h> 66 #include <sparc/sparc/cpuvar.h> 67 #include <sparc/dev/vmereg.h> 68 69 struct sparcvme_softc { 70 struct device sc_dev; /* base device */ 71 bus_space_tag_t sc_bustag; 72 bus_dma_tag_t sc_dmatag; 73 struct vmebusreg *sc_reg; /* VME control registers */ 74 struct vmebusvec *sc_vec; /* VME interrupt vector */ 75 struct rom_range *sc_range; /* ROM range property */ 76 int sc_nrange; 77 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 78 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 79 int (*sc_vmeintr) __P((void *)); 80 }; 81 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 82 83 /* autoconfiguration driver */ 84 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 85 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 86 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 87 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 88 #if defined(SUN4) 89 int vmeintr4 __P((void *)); 90 #endif 91 #if defined(SUN4M) 92 int vmeintr4m __P((void *)); 93 static int sparc_vme_error __P((void)); 94 #endif 95 96 97 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 98 vme_am_t, vme_datasize_t, 99 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 100 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 101 vme_datasize_t, vme_swap_t, 102 bus_space_tag_t *, bus_space_handle_t *, 103 vme_mapresc_t *)); 104 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 105 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 106 static const struct evcnt *sparc_vme_intr_evcnt __P((void *, 107 vme_intr_handle_t)); 108 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 109 int (*) __P((void *)), void *)); 110 static void sparc_vme_intr_disestablish __P((void *, void *)); 111 112 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 113 vme_addr_t, bus_type_t *, bus_addr_t *)); 114 #if defined(SUN4M) 115 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 116 bus_size_t, bus_size_t, int)); 117 118 #endif 119 120 /* 121 * DMA functions. 122 */ 123 static void sparc_vct_dmamap_destroy __P((void *, bus_dmamap_t)); 124 125 #if defined(SUN4) 126 static int sparc_vct4_dmamap_create __P((void *, vme_size_t, vme_am_t, 127 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 128 int, bus_dmamap_t *)); 129 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 130 bus_size_t, struct proc *, int)); 131 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 132 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 133 bus_addr_t, bus_size_t, int)); 134 #endif 135 136 #if defined(SUN4M) 137 static int sparc_vct4m_dmamap_create __P((void *, vme_size_t, vme_am_t, 138 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 139 int, bus_dmamap_t *)); 140 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 141 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 142 143 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 144 bus_size_t, struct proc *, int)); 145 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 146 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 147 bus_addr_t, bus_size_t, int)); 148 #endif 149 150 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 151 int, size_t, caddr_t *, int)); 152 #if 0 153 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 154 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 155 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 156 bus_dma_segment_t *, int, int, int, int)); 157 #endif 158 159 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 160 161 struct cfattach vme_mainbus_ca = { 162 sizeof(struct sparcvme_softc), vmematch_mainbus, vmeattach_mainbus 163 }; 164 165 struct cfattach vme_iommu_ca = { 166 sizeof(struct sparcvme_softc), vmematch_iommu, vmeattach_iommu 167 }; 168 169 int (*vmeerr_handler) __P((void)); 170 171 #define VMEMOD_D32 0x40 /* ??? */ 172 173 /* If the PROM does not provide the `ranges' property, we make up our own */ 174 struct rom_range vmebus_translations[] = { 175 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 176 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 177 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 178 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 179 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 180 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 181 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 182 #undef _DS 183 }; 184 185 /* 186 * DMA on sun4 VME devices use the last MB of virtual space, which 187 * is mapped by hardware onto the first MB of VME space. 188 */ 189 struct extent *vme_dvmamap; 190 191 struct sparc_bus_space_tag sparc_vme_bus_tag = { 192 NULL, /* cookie */ 193 NULL, /* parent bus tag */ 194 NULL, /* bus_map */ 195 NULL, /* bus_unmap */ 196 NULL, /* bus_subregion */ 197 NULL /* barrier */ 198 }; 199 200 struct vme_chipset_tag sparc_vme_chipset_tag = { 201 NULL, 202 sparc_vme_map, 203 sparc_vme_unmap, 204 sparc_vme_probe, 205 sparc_vme_intr_map, 206 sparc_vme_intr_evcnt, 207 sparc_vme_intr_establish, 208 sparc_vme_intr_disestablish, 209 0, 0, 0 /* bus specific DMA stuff */ 210 }; 211 212 213 #if defined(SUN4) 214 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 215 NULL, /* cookie */ 216 _bus_dmamap_create, 217 _bus_dmamap_destroy, 218 sparc_vme4_dmamap_load, 219 _bus_dmamap_load_mbuf, 220 _bus_dmamap_load_uio, 221 _bus_dmamap_load_raw, 222 sparc_vme4_dmamap_unload, 223 sparc_vme4_dmamap_sync, 224 225 _bus_dmamem_alloc, 226 _bus_dmamem_free, 227 sparc_vme_dmamem_map, 228 _bus_dmamem_unmap, 229 _bus_dmamem_mmap 230 }; 231 #endif 232 233 #if defined(SUN4M) 234 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 235 NULL, /* cookie */ 236 sparc_vme4m_dmamap_create, 237 _bus_dmamap_destroy, 238 sparc_vme4m_dmamap_load, 239 _bus_dmamap_load_mbuf, 240 _bus_dmamap_load_uio, 241 _bus_dmamap_load_raw, 242 sparc_vme4m_dmamap_unload, 243 sparc_vme4m_dmamap_sync, 244 245 _bus_dmamem_alloc, 246 _bus_dmamem_free, 247 sparc_vme_dmamem_map, 248 _bus_dmamem_unmap, 249 _bus_dmamem_mmap 250 }; 251 #endif 252 253 254 int 255 vmematch_mainbus(parent, cf, aux) 256 struct device *parent; 257 struct cfdata *cf; 258 void *aux; 259 { 260 struct mainbus_attach_args *ma = aux; 261 262 if (!CPU_ISSUN4) 263 return (0); 264 265 return (strcmp("vme", ma->ma_name) == 0); 266 } 267 268 int 269 vmematch_iommu(parent, cf, aux) 270 struct device *parent; 271 struct cfdata *cf; 272 void *aux; 273 { 274 struct iommu_attach_args *ia = aux; 275 276 return (strcmp("vme", ia->iom_name) == 0); 277 } 278 279 280 void 281 vmeattach_mainbus(parent, self, aux) 282 struct device *parent, *self; 283 void *aux; 284 { 285 #if defined(SUN4) 286 struct mainbus_attach_args *ma = aux; 287 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 288 struct vmebus_attach_args vba; 289 290 if (self->dv_unit > 0) { 291 printf(" unsupported\n"); 292 return; 293 } 294 295 sc->sc_bustag = ma->ma_bustag; 296 sc->sc_dmatag = ma->ma_dmatag; 297 298 /* VME interrupt entry point */ 299 sc->sc_vmeintr = vmeintr4; 300 301 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 302 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 303 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 304 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 305 306 #if 0 307 sparc_vme_bus_tag.parent = ma->ma_bustag; 308 vba.vba_bustag = &sparc_vme_bus_tag; 309 #endif 310 vba.va_vct = &sparc_vme_chipset_tag; 311 vba.va_bdt = &sparc_vme4_dma_tag; 312 vba.va_slaveconfig = 0; 313 314 /* Fall back to our own `range' construction */ 315 sc->sc_range = vmebus_translations; 316 sc->sc_nrange = 317 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 318 319 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 320 M_DEVBUF, 0, 0, EX_NOWAIT); 321 if (vme_dvmamap == NULL) 322 panic("vme: unable to allocate DVMA map"); 323 324 printf("\n"); 325 (void)config_found(self, &vba, 0); 326 327 #endif 328 return; 329 } 330 331 /* sun4m vmebus */ 332 void 333 vmeattach_iommu(parent, self, aux) 334 struct device *parent, *self; 335 void *aux; 336 { 337 #if defined(SUN4M) 338 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 339 struct iommu_attach_args *ia = aux; 340 struct vmebus_attach_args vba; 341 bus_space_handle_t bh; 342 int node; 343 int cline; 344 345 if (self->dv_unit > 0) { 346 printf(" unsupported\n"); 347 return; 348 } 349 350 sc->sc_bustag = ia->iom_bustag; 351 sc->sc_dmatag = ia->iom_dmatag; 352 353 /* VME interrupt entry point */ 354 sc->sc_vmeintr = vmeintr4m; 355 356 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 357 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4m_dmamap_create; 358 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 359 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 360 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 361 362 #if 0 363 vba.vba_bustag = &sparc_vme_bus_tag; 364 #endif 365 vba.va_vct = &sparc_vme_chipset_tag; 366 vba.va_bdt = &sparc_vme4m_dma_tag; 367 vba.va_slaveconfig = 0; 368 369 node = ia->iom_node; 370 371 /* 372 * Map VME control space 373 */ 374 if (ia->iom_nreg < 2) { 375 printf("%s: only %d register sets\n", self->dv_xname, 376 ia->iom_nreg); 377 return; 378 } 379 380 if (bus_space_map2(ia->iom_bustag, 381 (bus_type_t)ia->iom_reg[0].ior_iospace, 382 (bus_addr_t)ia->iom_reg[0].ior_pa, 383 (bus_size_t)ia->iom_reg[0].ior_size, 384 BUS_SPACE_MAP_LINEAR, 385 0, &bh) != 0) { 386 panic("%s: can't map vmebusreg", self->dv_xname); 387 } 388 sc->sc_reg = (struct vmebusreg *)bh; 389 390 if (bus_space_map2(ia->iom_bustag, 391 (bus_type_t)ia->iom_reg[1].ior_iospace, 392 (bus_addr_t)ia->iom_reg[1].ior_pa, 393 (bus_size_t)ia->iom_reg[1].ior_size, 394 BUS_SPACE_MAP_LINEAR, 395 0, &bh) != 0) { 396 panic("%s: can't map vmebusvec", self->dv_xname); 397 } 398 sc->sc_vec = (struct vmebusvec *)bh; 399 400 /* 401 * Map VME IO cache tags and flush control. 402 */ 403 if (bus_space_map2(ia->iom_bustag, 404 (bus_type_t)ia->iom_reg[1].ior_iospace, 405 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 406 VME_IOC_SIZE, 407 BUS_SPACE_MAP_LINEAR, 408 0, &bh) != 0) { 409 panic("%s: can't map IOC tags", self->dv_xname); 410 } 411 sc->sc_ioctags = (u_int32_t *)bh; 412 413 if (bus_space_map2(ia->iom_bustag, 414 (bus_type_t)ia->iom_reg[1].ior_iospace, 415 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 416 VME_IOC_SIZE, 417 BUS_SPACE_MAP_LINEAR, 418 0, &bh) != 0) { 419 panic("%s: can't map IOC flush registers", self->dv_xname); 420 } 421 sc->sc_iocflush = (u_int32_t *)bh; 422 423 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 424 425 /* 426 * Get "range" property. 427 */ 428 if (getprop(node, "ranges", sizeof(struct rom_range), 429 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 430 panic("%s: can't get ranges property", self->dv_xname); 431 } 432 433 sparcvme_sc = sc; 434 vmeerr_handler = sparc_vme_error; 435 436 /* 437 * Invalidate all IO-cache entries. 438 */ 439 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 440 sc->sc_ioctags[--cline] = 0; 441 } 442 443 /* Enable IO-cache */ 444 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 445 446 printf(": version 0x%x\n", 447 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 448 449 (void)config_found(self, &vba, 0); 450 #endif 451 } 452 453 #if defined(SUN4M) 454 static int 455 sparc_vme_error() 456 { 457 struct sparcvme_softc *sc = sparcvme_sc; 458 u_int32_t afsr, afpa; 459 char bits[64]; 460 461 afsr = sc->sc_reg->vmebus_afsr; 462 afpa = sc->sc_reg->vmebus_afar; 463 printf("VME error:\n\tAFSR %s\n", 464 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 465 printf("\taddress: 0x%x%x\n", afsr, afpa); 466 return (0); 467 } 468 #endif 469 470 int 471 vmebus_translate(sc, mod, addr, btp, bap) 472 struct sparcvme_softc *sc; 473 vme_am_t mod; 474 vme_addr_t addr; 475 bus_type_t *btp; 476 bus_addr_t *bap; 477 { 478 int i; 479 480 for (i = 0; i < sc->sc_nrange; i++) { 481 482 if (sc->sc_range[i].cspace != mod) 483 continue; 484 485 /* We've found the connection to the parent bus */ 486 *bap = sc->sc_range[i].poffset + addr; 487 *btp = sc->sc_range[i].pspace; 488 return (0); 489 } 490 return (ENOENT); 491 } 492 493 struct vmeprobe_myarg { 494 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 495 void *cbarg; 496 bus_space_tag_t tag; 497 int res; /* backwards */ 498 }; 499 500 static int vmeprobe_mycb __P((void *, void *)); 501 static int 502 vmeprobe_mycb(bh, arg) 503 void *bh, *arg; 504 { 505 struct vmeprobe_myarg *a = arg; 506 507 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 508 return (!a->res); 509 } 510 511 int 512 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 513 void *cookie; 514 vme_addr_t addr; 515 vme_size_t len; 516 vme_am_t mod; 517 vme_datasize_t datasize; 518 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 519 void *arg; 520 { 521 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 522 bus_type_t iospace; 523 bus_addr_t paddr; 524 bus_size_t size; 525 struct vmeprobe_myarg myarg; 526 int res, i; 527 528 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 529 return (EINVAL); 530 531 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 532 533 if (callback) { 534 myarg.cb = callback; 535 myarg.cbarg = arg; 536 myarg.tag = sc->sc_bustag; 537 myarg.res = 0; 538 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 539 0, vmeprobe_mycb, &myarg); 540 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 541 } 542 543 for (i = 0; i < len / size; i++) { 544 myarg.res = 0; 545 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 546 0, 0, 0); 547 if (res == 0) 548 return (EIO); 549 paddr += size; 550 } 551 return (0); 552 } 553 554 int 555 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 556 void *cookie; 557 vme_addr_t addr; 558 vme_size_t size; 559 vme_am_t mod; 560 vme_datasize_t datasize; 561 vme_swap_t swap; 562 bus_space_tag_t *tp; 563 bus_space_handle_t *hp; 564 vme_mapresc_t *rp; 565 { 566 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 567 bus_type_t iospace; 568 bus_addr_t paddr; 569 int error; 570 571 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 572 if (error != 0) 573 return (error); 574 575 *tp = sc->sc_bustag; 576 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 577 } 578 579 int 580 sparc_vme_mmap_cookie(addr, mod, hp) 581 vme_addr_t addr; 582 vme_am_t mod; 583 bus_space_handle_t *hp; 584 { 585 struct sparcvme_softc *sc = sparcvme_sc; 586 bus_type_t iospace; 587 bus_addr_t paddr; 588 int error; 589 590 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 591 if (error != 0) 592 return (error); 593 594 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 595 } 596 597 #if defined(SUN4M) 598 void 599 sparc_vme4m_barrier(t, h, offset, size, flags) 600 bus_space_tag_t t; 601 bus_space_handle_t h; 602 bus_size_t offset; 603 bus_size_t size; 604 int flags; 605 { 606 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 607 608 /* Read async fault status to flush write-buffers */ 609 (*(volatile int *)&vbp->vmebus_afsr); 610 } 611 #endif 612 613 614 615 /* 616 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 617 */ 618 static int vme_ipl_to_pil[] = { 619 0, 620 2, 621 3, 622 5, 623 7, 624 9, 625 11, 626 13 627 }; 628 629 630 /* 631 * All VME device interrupts go through vmeintr(). This function reads 632 * the VME vector from the bus, then dispatches the device interrupt 633 * handler. All handlers for devices that map to the same Processor 634 * Interrupt Level (according to the table above) are on a linked list 635 * of `sparc_vme_intr_handle' structures. The head of which is passed 636 * down as the argument to `vmeintr(void *arg)'. 637 */ 638 struct sparc_vme_intr_handle { 639 struct intrhand ih; 640 struct sparc_vme_intr_handle *next; 641 int vec; /* VME interrupt vector */ 642 int pri; /* VME interrupt priority */ 643 struct sparcvme_softc *sc;/*XXX*/ 644 }; 645 646 #if defined(SUN4) 647 int 648 vmeintr4(arg) 649 void *arg; 650 { 651 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 652 int level, vec; 653 int i = 0; 654 655 level = (ihp->pri << 1) | 1; 656 657 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 658 659 if (vec == -1) { 660 printf("vme: spurious interrupt\n"); 661 return 1; /* XXX - pretend we handled it, for now */ 662 } 663 664 for (; ihp; ihp = ihp->next) 665 if (ihp->vec == vec && ihp->ih.ih_fun) 666 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 667 return (i); 668 } 669 #endif 670 671 #if defined(SUN4M) 672 int 673 vmeintr4m(arg) 674 void *arg; 675 { 676 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 677 int level, vec; 678 int i = 0; 679 680 level = (ihp->pri << 1) | 1; 681 682 #if 0 683 int pending; 684 685 /* Flush VME <=> Sbus write buffers */ 686 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 687 688 pending = *((int*)ICR_SI_PEND); 689 if ((pending & SINTR_VME(ihp->pri)) == 0) { 690 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 691 ihp->pri, pending); 692 return (0); 693 } 694 #endif 695 #if 0 696 /* Why gives this a bus timeout sometimes? */ 697 vec = ihp->sc->sc_vec->vmebusvec[level]; 698 #else 699 /* so, arrange to catch the fault... */ 700 { 701 extern struct user *proc0paddr; 702 extern int fkbyte __P((caddr_t, struct pcb *)); 703 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 704 struct pcb *xpcb; 705 u_long saveonfault; 706 int s; 707 708 s = splhigh(); 709 if (curproc == NULL) 710 xpcb = (struct pcb *)proc0paddr; 711 else 712 xpcb = &curproc->p_addr->u_pcb; 713 714 saveonfault = (u_long)xpcb->pcb_onfault; 715 vec = fkbyte(addr, xpcb); 716 xpcb->pcb_onfault = (caddr_t)saveonfault; 717 718 splx(s); 719 } 720 #endif 721 722 if (vec == -1) { 723 printf("vme: spurious interrupt: "); 724 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 725 *((int*)ICR_SI_PEND), 726 ihp->sc->sc_reg->vmebus_afsr, 727 ihp->sc->sc_reg->vmebus_afar); 728 return (1); /* XXX - pretend we handled it, for now */ 729 } 730 731 for (; ihp; ihp = ihp->next) 732 if (ihp->vec == vec && ihp->ih.ih_fun) 733 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 734 return (i); 735 } 736 #endif 737 738 int 739 sparc_vme_intr_map(cookie, level, vec, ihp) 740 void *cookie; 741 int level; 742 int vec; 743 vme_intr_handle_t *ihp; 744 { 745 struct sparc_vme_intr_handle *ih; 746 747 ih = (vme_intr_handle_t) 748 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 749 ih->pri = level; 750 ih->vec = vec; 751 ih->sc = cookie;/*XXX*/ 752 *ihp = ih; 753 return (0); 754 } 755 756 const struct evcnt * 757 sparc_vme_intr_evcnt(cookie, vih) 758 void *cookie; 759 vme_intr_handle_t vih; 760 { 761 762 /* XXX for now, no evcnt parent reported */ 763 return NULL; 764 } 765 766 void * 767 sparc_vme_intr_establish(cookie, vih, pri, func, arg) 768 void *cookie; 769 vme_intr_handle_t vih; 770 int pri; 771 int (*func) __P((void *)); 772 void *arg; 773 { 774 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 775 struct sparc_vme_intr_handle *svih = 776 (struct sparc_vme_intr_handle *)vih; 777 struct intrhand *ih; 778 int level; 779 780 /* XXX pri == svih->pri ??? */ 781 782 /* Translate VME priority to processor IPL */ 783 level = vme_ipl_to_pil[svih->pri]; 784 785 svih->ih.ih_fun = func; 786 svih->ih.ih_arg = arg; 787 svih->next = NULL; 788 789 /* ensure the interrupt subsystem will call us at this level */ 790 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 791 if (ih->ih_fun == sc->sc_vmeintr) 792 break; 793 794 if (ih == NULL) { 795 ih = (struct intrhand *) 796 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 797 if (ih == NULL) 798 panic("vme_addirq"); 799 bzero(ih, sizeof *ih); 800 ih->ih_fun = sc->sc_vmeintr; 801 ih->ih_arg = vih; 802 intr_establish(level, ih); 803 } else { 804 svih->next = (vme_intr_handle_t)ih->ih_arg; 805 ih->ih_arg = vih; 806 } 807 return (NULL); 808 } 809 810 void 811 sparc_vme_unmap(cookie, resc) 812 void * cookie; 813 vme_mapresc_t resc; 814 { 815 /* Not implemented */ 816 panic("sparc_vme_unmap"); 817 } 818 819 void 820 sparc_vme_intr_disestablish(cookie, a) 821 void *cookie; 822 void *a; 823 { 824 /* Not implemented */ 825 panic("sparc_vme_intr_disestablish"); 826 } 827 828 829 830 /* 831 * VME DMA functions. 832 */ 833 834 static void 835 sparc_vct_dmamap_destroy(cookie, map) 836 void *cookie; 837 bus_dmamap_t map; 838 { 839 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 840 bus_dmamap_destroy(sc->sc_dmatag, map); 841 } 842 843 #if defined(SUN4) 844 static int 845 sparc_vct4_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 846 boundary, flags, dmamp) 847 void *cookie; 848 vme_size_t size; 849 vme_am_t am; 850 vme_datasize_t datasize; 851 vme_swap_t swap; 852 int nsegments; 853 vme_size_t maxsegsz; 854 vme_addr_t boundary; 855 int flags; 856 bus_dmamap_t *dmamp; 857 { 858 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 859 860 /* Allocate a base map through parent bus ops */ 861 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 862 boundary, flags, dmamp)); 863 } 864 865 int 866 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 867 bus_dma_tag_t t; 868 bus_dmamap_t map; 869 void *buf; 870 bus_size_t buflen; 871 struct proc *p; 872 int flags; 873 { 874 bus_addr_t dva; 875 bus_size_t sgsize; 876 vaddr_t va, voff; 877 pmap_t pmap; 878 int pagesz = PAGE_SIZE; 879 int error; 880 881 cpuinfo.cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 882 883 va = (vaddr_t)buf; 884 voff = va & (pagesz - 1); 885 va &= -pagesz; 886 887 /* 888 * Allocate an integral number of pages from DVMA space 889 * covering the passed buffer. 890 */ 891 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 892 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 893 map->_dm_boundary, 894 (flags & BUS_DMA_NOWAIT) == 0 895 ? EX_WAITOK 896 : EX_NOWAIT, 897 (u_long *)&dva); 898 if (error != 0) 899 return (error); 900 901 map->dm_mapsize = buflen; 902 map->dm_nsegs = 1; 903 /* Adjust DVMA address to VME view */ 904 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 905 map->dm_segs[0].ds_len = buflen; 906 map->dm_segs[0]._ds_sgsize = sgsize; 907 908 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 909 910 for (; sgsize != 0; ) { 911 paddr_t pa; 912 /* 913 * Get the physical address for this page. 914 */ 915 (void) pmap_extract(pmap, va, &pa); 916 917 #ifdef notyet 918 if (have_iocache) 919 pa |= PG_IOC; 920 #endif 921 pmap_enter(pmap_kernel(), dva, 922 pa | PMAP_NC, 923 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 924 925 dva += pagesz; 926 va += pagesz; 927 sgsize -= pagesz; 928 } 929 930 return (0); 931 } 932 933 void 934 sparc_vme4_dmamap_unload(t, map) 935 bus_dma_tag_t t; 936 bus_dmamap_t map; 937 { 938 bus_dma_segment_t *segs = map->dm_segs; 939 int nsegs = map->dm_nsegs; 940 bus_addr_t dva; 941 bus_size_t len; 942 int i, s, error; 943 944 for (i = 0; i < nsegs; i++) { 945 /* Go from VME to CPU view */ 946 dva = segs[i].ds_addr + VME4_DVMA_BASE; 947 dva &= -PAGE_SIZE; 948 len = segs[i]._ds_sgsize; 949 950 /* Remove double-mapping in DVMA space */ 951 pmap_remove(pmap_kernel(), dva, dva + len); 952 953 /* Release DVMA space */ 954 s = splhigh(); 955 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 956 splx(s); 957 if (error != 0) 958 printf("warning: %ld of DVMA space lost\n", len); 959 } 960 961 /* Mark the mappings as invalid. */ 962 map->dm_mapsize = 0; 963 map->dm_nsegs = 0; 964 } 965 966 void 967 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 968 bus_dma_tag_t t; 969 bus_dmamap_t map; 970 bus_addr_t offset; 971 bus_size_t len; 972 int ops; 973 { 974 975 /* 976 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 977 * Currently the cache is flushed in bus_dma_load()... 978 */ 979 } 980 #endif /* SUN4 */ 981 982 #if defined(SUN4M) 983 static int 984 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 985 bus_dma_tag_t t; 986 bus_size_t size; 987 int nsegments; 988 bus_size_t maxsegsz; 989 bus_size_t boundary; 990 int flags; 991 bus_dmamap_t *dmamp; 992 { 993 994 printf("sparc_vme4m_dmamap_create: please use `vme_dmamap_create'\n"); 995 return (EINVAL); 996 } 997 998 static int 999 sparc_vct4m_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 1000 boundary, flags, dmamp) 1001 void *cookie; 1002 vme_size_t size; 1003 vme_am_t am; 1004 vme_datasize_t datasize; 1005 vme_swap_t swap; 1006 int nsegments; 1007 vme_size_t maxsegsz; 1008 vme_addr_t boundary; 1009 int flags; 1010 bus_dmamap_t *dmamp; 1011 { 1012 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 1013 bus_dmamap_t map; 1014 int error; 1015 1016 /* Allocate a base map through parent bus ops */ 1017 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1018 boundary, flags, &map); 1019 if (error != 0) 1020 return (error); 1021 1022 /* 1023 * Each I/O cache line maps to a 8K section of VME DVMA space, so 1024 * we must ensure that DVMA alloctions are always 8K aligned. 1025 */ 1026 map->_dm_align = VME_IOC_PAGESZ; 1027 1028 /* Set map region based on Address Modifier */ 1029 switch ((am & VME_AM_ADRSIZEMASK)) { 1030 case VME_AM_A16: 1031 case VME_AM_A24: 1032 /* 1 MB of DVMA space */ 1033 map->_dm_ex_start = 0xff800000; 1034 map->_dm_ex_end = 0xff900000; 1035 break; 1036 case VME_AM_A32: 1037 /* 8 MB of DVMA space */ 1038 map->_dm_ex_start = 0xff800000; 1039 map->_dm_ex_end = IOMMU_DVMA_END; 1040 break; 1041 } 1042 1043 *dmamp = map; 1044 return (0); 1045 } 1046 1047 int 1048 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 1049 bus_dma_tag_t t; 1050 bus_dmamap_t map; 1051 void *buf; 1052 bus_size_t buflen; 1053 struct proc *p; 1054 int flags; 1055 { 1056 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1057 volatile u_int32_t *ioctags; 1058 int error; 1059 1060 /* Round request to a multiple of the I/O cache size */ 1061 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 1062 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1063 if (error != 0) 1064 return (error); 1065 1066 /* Allocate I/O cache entries for this range */ 1067 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1068 while (buflen > 0) { 1069 *ioctags = VME_IOC_IC | VME_IOC_W; 1070 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1071 buflen -= VME_IOC_PAGESZ; 1072 } 1073 return (0); 1074 } 1075 1076 1077 void 1078 sparc_vme4m_dmamap_unload(t, map) 1079 bus_dma_tag_t t; 1080 bus_dmamap_t map; 1081 { 1082 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1083 volatile u_int32_t *flushregs; 1084 int len; 1085 1086 /* Flush VME I/O cache */ 1087 len = map->dm_segs[0]._ds_sgsize; 1088 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1089 while (len > 0) { 1090 *flushregs = 0; 1091 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1092 len -= VME_IOC_PAGESZ; 1093 } 1094 1095 /* 1096 * Start a read from `tag space' which will not complete until 1097 * all cache flushes have finished 1098 */ 1099 (*sc->sc_ioctags); 1100 1101 bus_dmamap_unload(sc->sc_dmatag, map); 1102 } 1103 1104 void 1105 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 1106 bus_dma_tag_t t; 1107 bus_dmamap_t map; 1108 bus_addr_t offset; 1109 bus_size_t len; 1110 int ops; 1111 { 1112 1113 /* 1114 * XXX Should perform cache flushes as necessary. 1115 */ 1116 } 1117 #endif /* SUN4M */ 1118 1119 int 1120 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1121 bus_dma_tag_t t; 1122 bus_dma_segment_t *segs; 1123 int nsegs; 1124 size_t size; 1125 caddr_t *kvap; 1126 int flags; 1127 { 1128 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1129 1130 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1131 } 1132
Indexes created Wed Sep 24 05:09:52 GMT 2025