vme_machdep.c revision 1.28
1 /* $NetBSD: vme_machdep.c,v 1.28 2000/06/27 09:05:23 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/errno.h> 45 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/syslog.h> 49 50 #include <vm/vm.h> 51 52 #define _SPARC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 #include <sparc/sparc/iommuvar.h> 55 #include <machine/autoconf.h> 56 #include <machine/pmap.h> 57 #include <machine/oldmon.h> 58 #include <machine/cpu.h> 59 #include <machine/ctlreg.h> 60 61 #include <dev/vme/vmereg.h> 62 #include <dev/vme/vmevar.h> 63 64 #include <sparc/sparc/asm.h> 65 #include <sparc/sparc/vaddrs.h> 66 #include <sparc/sparc/cpuvar.h> 67 #include <sparc/dev/vmereg.h> 68 69 struct sparcvme_softc { 70 struct device sc_dev; /* base device */ 71 bus_space_tag_t sc_bustag; 72 bus_dma_tag_t sc_dmatag; 73 struct vmebusreg *sc_reg; /* VME control registers */ 74 struct vmebusvec *sc_vec; /* VME interrupt vector */ 75 struct rom_range *sc_range; /* ROM range property */ 76 int sc_nrange; 77 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 78 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 79 int (*sc_vmeintr) __P((void *)); 80 }; 81 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 82 83 /* autoconfiguration driver */ 84 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 85 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 86 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 87 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 88 #if defined(SUN4) 89 int vmeintr4 __P((void *)); 90 #endif 91 #if defined(SUN4M) 92 int vmeintr4m __P((void *)); 93 static int sparc_vme_error __P((void)); 94 #endif 95 96 97 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 98 vme_am_t, vme_datasize_t, 99 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 100 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 101 vme_datasize_t, vme_swap_t, 102 bus_space_tag_t *, bus_space_handle_t *, 103 vme_mapresc_t *)); 104 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 105 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 106 static const struct evcnt *sparc_vme_intr_evcnt __P((void *, 107 vme_intr_handle_t)); 108 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 109 int (*) __P((void *)), void *)); 110 static void sparc_vme_intr_disestablish __P((void *, void *)); 111 112 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 113 vme_addr_t, bus_type_t *, bus_addr_t *)); 114 #if defined(SUN4M) 115 static void sparc_vme_iommu_barrier __P(( bus_space_tag_t, bus_space_handle_t, 116 bus_size_t, bus_size_t, int)); 117 118 #endif 119 120 /* 121 * DMA functions. 122 */ 123 static void sparc_vct_dmamap_destroy __P((void *, bus_dmamap_t)); 124 125 #if defined(SUN4) 126 static int sparc_vct4_dmamap_create __P((void *, vme_size_t, vme_am_t, 127 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 128 int, bus_dmamap_t *)); 129 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 130 bus_size_t, struct proc *, int)); 131 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 132 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 133 bus_addr_t, bus_size_t, int)); 134 #endif 135 136 #if defined(SUN4M) 137 static int sparc_vct_iommu_dmamap_create __P((void *, vme_size_t, vme_am_t, 138 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 139 int, bus_dmamap_t *)); 140 static int sparc_vme_iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, 141 int, bus_size_t, bus_size_t, int, bus_dmamap_t *)); 142 143 static int sparc_vme_iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, 144 void *, bus_size_t, struct proc *, int)); 145 static void sparc_vme_iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 146 static void sparc_vme_iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 147 bus_addr_t, bus_size_t, int)); 148 #endif 149 150 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 151 int, size_t, caddr_t *, int)); 152 #if 0 153 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 154 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 155 static paddr_t sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 156 bus_dma_segment_t *, int, off_t, int, int)); 157 #endif 158 159 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 160 161 struct cfattach vme_mainbus_ca = { 162 sizeof(struct sparcvme_softc), vmematch_mainbus, vmeattach_mainbus 163 }; 164 165 struct cfattach vme_iommu_ca = { 166 sizeof(struct sparcvme_softc), vmematch_iommu, vmeattach_iommu 167 }; 168 169 int (*vmeerr_handler) __P((void)); 170 171 #define VMEMOD_D32 0x40 /* ??? */ 172 173 /* If the PROM does not provide the `ranges' property, we make up our own */ 174 struct rom_range vmebus_translations[] = { 175 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 176 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 177 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 178 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 179 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 180 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 181 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 182 #undef _DS 183 }; 184 185 /* 186 * The VME bus logic on sun4 machines maps DMA requests in the first MB 187 * of VME space to the last MB of DVMA space. `vme_dvmamap' is used 188 * for DVMA space allocations. The DMA addresses returned by 189 * bus_dmamap_load*() must be relocated by -VME4_DVMA_BASE. 190 */ 191 struct extent *vme_dvmamap; 192 193 /* 194 * The VME hardware on the sun4m IOMMU maps the first 8MB of 32-bit 195 * VME space to the last 8MB of DVMA space and the first 1MB of 196 * 24-bit VME space to the first 1MB of the last 8MB of DVMA space 197 * (thus 24-bit VME space overlaps the first 1MB of of 32-bit space). 198 * The following constants define subregions in the IOMMU DVMA map 199 * for VME DVMA allocations. The DMA addresses returned by 200 * bus_dmamap_load*() must be relocated by -VME_IOMMU_DVMA_BASE. 201 */ 202 #define VME_IOMMU_DVMA_BASE 0xff800000 203 #define VME_IOMMU_DVMA_AM24_BASE VME_IOMMU_DVMA_BASE 204 #define VME_IOMMU_DVMA_AM24_END 0xff900000 205 #define VME_IOMMU_DVMA_AM32_BASE VME_IOMMU_DVMA_BASE 206 #define VME_IOMMU_DVMA_AM32_END IOMMU_DVMA_END 207 208 struct sparc_bus_space_tag sparc_vme_bus_tag = { 209 NULL, /* cookie */ 210 NULL, /* parent bus tag */ 211 NULL, /* bus_map */ 212 NULL, /* bus_unmap */ 213 NULL, /* bus_subregion */ 214 NULL /* barrier */ 215 }; 216 217 struct vme_chipset_tag sparc_vme_chipset_tag = { 218 NULL, 219 sparc_vme_map, 220 sparc_vme_unmap, 221 sparc_vme_probe, 222 sparc_vme_intr_map, 223 sparc_vme_intr_evcnt, 224 sparc_vme_intr_establish, 225 sparc_vme_intr_disestablish, 226 0, 0, 0 /* bus specific DMA stuff */ 227 }; 228 229 230 #if defined(SUN4) 231 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 232 NULL, /* cookie */ 233 _bus_dmamap_create, 234 _bus_dmamap_destroy, 235 sparc_vme4_dmamap_load, 236 _bus_dmamap_load_mbuf, 237 _bus_dmamap_load_uio, 238 _bus_dmamap_load_raw, 239 sparc_vme4_dmamap_unload, 240 sparc_vme4_dmamap_sync, 241 242 _bus_dmamem_alloc, 243 _bus_dmamem_free, 244 sparc_vme_dmamem_map, 245 _bus_dmamem_unmap, 246 _bus_dmamem_mmap 247 }; 248 #endif 249 250 #if defined(SUN4M) 251 struct sparc_bus_dma_tag sparc_vme_iommu_dma_tag = { 252 NULL, /* cookie */ 253 sparc_vme_iommu_dmamap_create, 254 _bus_dmamap_destroy, 255 sparc_vme_iommu_dmamap_load, 256 _bus_dmamap_load_mbuf, 257 _bus_dmamap_load_uio, 258 _bus_dmamap_load_raw, 259 sparc_vme_iommu_dmamap_unload, 260 sparc_vme_iommu_dmamap_sync, 261 262 _bus_dmamem_alloc, 263 _bus_dmamem_free, 264 sparc_vme_dmamem_map, 265 _bus_dmamem_unmap, 266 _bus_dmamem_mmap 267 }; 268 #endif 269 270 271 int 272 vmematch_mainbus(parent, cf, aux) 273 struct device *parent; 274 struct cfdata *cf; 275 void *aux; 276 { 277 struct mainbus_attach_args *ma = aux; 278 279 if (!CPU_ISSUN4) 280 return (0); 281 282 return (strcmp("vme", ma->ma_name) == 0); 283 } 284 285 int 286 vmematch_iommu(parent, cf, aux) 287 struct device *parent; 288 struct cfdata *cf; 289 void *aux; 290 { 291 struct iommu_attach_args *ia = aux; 292 293 return (strcmp("vme", ia->iom_name) == 0); 294 } 295 296 297 void 298 vmeattach_mainbus(parent, self, aux) 299 struct device *parent, *self; 300 void *aux; 301 { 302 #if defined(SUN4) 303 struct mainbus_attach_args *ma = aux; 304 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 305 struct vmebus_attach_args vba; 306 307 if (self->dv_unit > 0) { 308 printf(" unsupported\n"); 309 return; 310 } 311 312 sc->sc_bustag = ma->ma_bustag; 313 sc->sc_dmatag = ma->ma_dmatag; 314 315 /* VME interrupt entry point */ 316 sc->sc_vmeintr = vmeintr4; 317 318 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 319 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 320 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 321 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 322 323 #if 0 324 sparc_vme_bus_tag.parent = ma->ma_bustag; 325 vba.vba_bustag = &sparc_vme_bus_tag; 326 #endif 327 vba.va_vct = &sparc_vme_chipset_tag; 328 vba.va_bdt = &sparc_vme4_dma_tag; 329 vba.va_slaveconfig = 0; 330 331 /* Fall back to our own `range' construction */ 332 sc->sc_range = vmebus_translations; 333 sc->sc_nrange = 334 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 335 336 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 337 M_DEVBUF, 0, 0, EX_NOWAIT); 338 if (vme_dvmamap == NULL) 339 panic("vme: unable to allocate DVMA map"); 340 341 printf("\n"); 342 (void)config_found(self, &vba, 0); 343 344 #endif 345 return; 346 } 347 348 /* sun4m vmebus */ 349 void 350 vmeattach_iommu(parent, self, aux) 351 struct device *parent, *self; 352 void *aux; 353 { 354 #if defined(SUN4M) 355 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 356 struct iommu_attach_args *ia = aux; 357 struct vmebus_attach_args vba; 358 bus_space_handle_t bh; 359 int node; 360 int cline; 361 362 if (self->dv_unit > 0) { 363 printf(" unsupported\n"); 364 return; 365 } 366 367 sc->sc_bustag = ia->iom_bustag; 368 sc->sc_dmatag = ia->iom_dmatag; 369 370 /* VME interrupt entry point */ 371 sc->sc_vmeintr = vmeintr4m; 372 373 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 374 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct_iommu_dmamap_create; 375 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 376 /*XXX*/ sparc_vme_iommu_dma_tag._cookie = self; 377 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme_iommu_barrier; 378 379 #if 0 380 vba.vba_bustag = &sparc_vme_bus_tag; 381 #endif 382 vba.va_vct = &sparc_vme_chipset_tag; 383 vba.va_bdt = &sparc_vme_iommu_dma_tag; 384 vba.va_slaveconfig = 0; 385 386 node = ia->iom_node; 387 388 /* 389 * Map VME control space 390 */ 391 if (ia->iom_nreg < 2) { 392 printf("%s: only %d register sets\n", self->dv_xname, 393 ia->iom_nreg); 394 return; 395 } 396 397 if (bus_space_map2(ia->iom_bustag, 398 (bus_type_t)ia->iom_reg[0].ior_iospace, 399 (bus_addr_t)ia->iom_reg[0].ior_pa, 400 (bus_size_t)ia->iom_reg[0].ior_size, 401 BUS_SPACE_MAP_LINEAR, 402 0, &bh) != 0) { 403 panic("%s: can't map vmebusreg", self->dv_xname); 404 } 405 sc->sc_reg = (struct vmebusreg *)bh; 406 407 if (bus_space_map2(ia->iom_bustag, 408 (bus_type_t)ia->iom_reg[1].ior_iospace, 409 (bus_addr_t)ia->iom_reg[1].ior_pa, 410 (bus_size_t)ia->iom_reg[1].ior_size, 411 BUS_SPACE_MAP_LINEAR, 412 0, &bh) != 0) { 413 panic("%s: can't map vmebusvec", self->dv_xname); 414 } 415 sc->sc_vec = (struct vmebusvec *)bh; 416 417 /* 418 * Map VME IO cache tags and flush control. 419 */ 420 if (bus_space_map2(ia->iom_bustag, 421 (bus_type_t)ia->iom_reg[1].ior_iospace, 422 (bus_addr_t)ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET, 423 VME_IOC_SIZE, 424 BUS_SPACE_MAP_LINEAR, 425 0, &bh) != 0) { 426 panic("%s: can't map IOC tags", self->dv_xname); 427 } 428 sc->sc_ioctags = (u_int32_t *)bh; 429 430 if (bus_space_map2(ia->iom_bustag, 431 (bus_type_t)ia->iom_reg[1].ior_iospace, 432 (bus_addr_t)ia->iom_reg[1].ior_pa+VME_IOC_FLUSHOFFSET, 433 VME_IOC_SIZE, 434 BUS_SPACE_MAP_LINEAR, 435 0, &bh) != 0) { 436 panic("%s: can't map IOC flush registers", self->dv_xname); 437 } 438 sc->sc_iocflush = (u_int32_t *)bh; 439 440 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 441 442 /* 443 * Get "range" property. 444 */ 445 if (getprop(node, "ranges", sizeof(struct rom_range), 446 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 447 panic("%s: can't get ranges property", self->dv_xname); 448 } 449 450 sparcvme_sc = sc; 451 vmeerr_handler = sparc_vme_error; 452 453 /* 454 * Invalidate all IO-cache entries. 455 */ 456 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 457 sc->sc_ioctags[--cline] = 0; 458 } 459 460 /* Enable IO-cache */ 461 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 462 463 printf(": version 0x%x\n", 464 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 465 466 (void)config_found(self, &vba, 0); 467 #endif 468 } 469 470 #if defined(SUN4M) 471 static int 472 sparc_vme_error() 473 { 474 struct sparcvme_softc *sc = sparcvme_sc; 475 u_int32_t afsr, afpa; 476 char bits[64]; 477 478 afsr = sc->sc_reg->vmebus_afsr; 479 afpa = sc->sc_reg->vmebus_afar; 480 printf("VME error:\n\tAFSR %s\n", 481 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 482 printf("\taddress: 0x%x%x\n", afsr, afpa); 483 return (0); 484 } 485 #endif 486 487 int 488 vmebus_translate(sc, mod, addr, btp, bap) 489 struct sparcvme_softc *sc; 490 vme_am_t mod; 491 vme_addr_t addr; 492 bus_type_t *btp; 493 bus_addr_t *bap; 494 { 495 int i; 496 497 for (i = 0; i < sc->sc_nrange; i++) { 498 499 if (sc->sc_range[i].cspace != mod) 500 continue; 501 502 /* We've found the connection to the parent bus */ 503 *bap = sc->sc_range[i].poffset + addr; 504 *btp = sc->sc_range[i].pspace; 505 return (0); 506 } 507 return (ENOENT); 508 } 509 510 struct vmeprobe_myarg { 511 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 512 void *cbarg; 513 bus_space_tag_t tag; 514 int res; /* backwards */ 515 }; 516 517 static int vmeprobe_mycb __P((void *, void *)); 518 static int 519 vmeprobe_mycb(bh, arg) 520 void *bh, *arg; 521 { 522 struct vmeprobe_myarg *a = arg; 523 524 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 525 return (!a->res); 526 } 527 528 int 529 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 530 void *cookie; 531 vme_addr_t addr; 532 vme_size_t len; 533 vme_am_t mod; 534 vme_datasize_t datasize; 535 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 536 void *arg; 537 { 538 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 539 bus_type_t iospace; 540 bus_addr_t paddr; 541 bus_size_t size; 542 struct vmeprobe_myarg myarg; 543 int res, i; 544 545 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 546 return (EINVAL); 547 548 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 549 550 if (callback) { 551 myarg.cb = callback; 552 myarg.cbarg = arg; 553 myarg.tag = sc->sc_bustag; 554 myarg.res = 0; 555 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 556 0, vmeprobe_mycb, &myarg); 557 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 558 } 559 560 for (i = 0; i < len / size; i++) { 561 myarg.res = 0; 562 res = bus_space_probe(sc->sc_bustag, iospace, paddr, size, 0, 563 0, 0, 0); 564 if (res == 0) 565 return (EIO); 566 paddr += size; 567 } 568 return (0); 569 } 570 571 int 572 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 573 void *cookie; 574 vme_addr_t addr; 575 vme_size_t size; 576 vme_am_t mod; 577 vme_datasize_t datasize; 578 vme_swap_t swap; 579 bus_space_tag_t *tp; 580 bus_space_handle_t *hp; 581 vme_mapresc_t *rp; 582 { 583 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 584 bus_type_t iospace; 585 bus_addr_t paddr; 586 int error; 587 588 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 589 if (error != 0) 590 return (error); 591 592 *tp = sc->sc_bustag; 593 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 594 } 595 596 int 597 sparc_vme_mmap_cookie(addr, mod, hp) 598 vme_addr_t addr; 599 vme_am_t mod; 600 bus_space_handle_t *hp; 601 { 602 struct sparcvme_softc *sc = sparcvme_sc; 603 bus_type_t iospace; 604 bus_addr_t paddr; 605 int error; 606 607 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 608 if (error != 0) 609 return (error); 610 611 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 612 } 613 614 #if defined(SUN4M) 615 void 616 sparc_vme_iommu_barrier(t, h, offset, size, flags) 617 bus_space_tag_t t; 618 bus_space_handle_t h; 619 bus_size_t offset; 620 bus_size_t size; 621 int flags; 622 { 623 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 624 625 /* Read async fault status to flush write-buffers */ 626 (*(volatile int *)&vbp->vmebus_afsr); 627 } 628 #endif 629 630 631 632 /* 633 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 634 */ 635 static int vme_ipl_to_pil[] = { 636 0, 637 2, 638 3, 639 5, 640 7, 641 9, 642 11, 643 13 644 }; 645 646 647 /* 648 * All VME device interrupts go through vmeintr(). This function reads 649 * the VME vector from the bus, then dispatches the device interrupt 650 * handler. All handlers for devices that map to the same Processor 651 * Interrupt Level (according to the table above) are on a linked list 652 * of `sparc_vme_intr_handle' structures. The head of which is passed 653 * down as the argument to `vmeintr(void *arg)'. 654 */ 655 struct sparc_vme_intr_handle { 656 struct intrhand ih; 657 struct sparc_vme_intr_handle *next; 658 int vec; /* VME interrupt vector */ 659 int pri; /* VME interrupt priority */ 660 struct sparcvme_softc *sc;/*XXX*/ 661 }; 662 663 #if defined(SUN4) 664 int 665 vmeintr4(arg) 666 void *arg; 667 { 668 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 669 int level, vec; 670 int i = 0; 671 672 level = (ihp->pri << 1) | 1; 673 674 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 675 676 if (vec == -1) { 677 printf("vme: spurious interrupt\n"); 678 return 1; /* XXX - pretend we handled it, for now */ 679 } 680 681 for (; ihp; ihp = ihp->next) 682 if (ihp->vec == vec && ihp->ih.ih_fun) 683 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 684 return (i); 685 } 686 #endif 687 688 #if defined(SUN4M) 689 int 690 vmeintr4m(arg) 691 void *arg; 692 { 693 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 694 int level, vec; 695 int i = 0; 696 697 level = (ihp->pri << 1) | 1; 698 699 #if 0 700 int pending; 701 702 /* Flush VME <=> Sbus write buffers */ 703 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 704 705 pending = *((int*)ICR_SI_PEND); 706 if ((pending & SINTR_VME(ihp->pri)) == 0) { 707 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 708 ihp->pri, pending); 709 return (0); 710 } 711 #endif 712 #if 0 713 /* Why gives this a bus timeout sometimes? */ 714 vec = ihp->sc->sc_vec->vmebusvec[level]; 715 #else 716 /* so, arrange to catch the fault... */ 717 { 718 extern struct user *proc0paddr; 719 extern int fkbyte __P((caddr_t, struct pcb *)); 720 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 721 struct pcb *xpcb; 722 u_long saveonfault; 723 int s; 724 725 s = splhigh(); 726 if (curproc == NULL) 727 xpcb = (struct pcb *)proc0paddr; 728 else 729 xpcb = &curproc->p_addr->u_pcb; 730 731 saveonfault = (u_long)xpcb->pcb_onfault; 732 vec = fkbyte(addr, xpcb); 733 xpcb->pcb_onfault = (caddr_t)saveonfault; 734 735 splx(s); 736 } 737 #endif 738 739 if (vec == -1) { 740 printf("vme: spurious interrupt: "); 741 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 742 *((int*)ICR_SI_PEND), 743 ihp->sc->sc_reg->vmebus_afsr, 744 ihp->sc->sc_reg->vmebus_afar); 745 return (1); /* XXX - pretend we handled it, for now */ 746 } 747 748 for (; ihp; ihp = ihp->next) 749 if (ihp->vec == vec && ihp->ih.ih_fun) 750 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 751 return (i); 752 } 753 #endif 754 755 int 756 sparc_vme_intr_map(cookie, level, vec, ihp) 757 void *cookie; 758 int level; 759 int vec; 760 vme_intr_handle_t *ihp; 761 { 762 struct sparc_vme_intr_handle *ih; 763 764 ih = (vme_intr_handle_t) 765 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 766 ih->pri = level; 767 ih->vec = vec; 768 ih->sc = cookie;/*XXX*/ 769 *ihp = ih; 770 return (0); 771 } 772 773 const struct evcnt * 774 sparc_vme_intr_evcnt(cookie, vih) 775 void *cookie; 776 vme_intr_handle_t vih; 777 { 778 779 /* XXX for now, no evcnt parent reported */ 780 return NULL; 781 } 782 783 void * 784 sparc_vme_intr_establish(cookie, vih, pri, func, arg) 785 void *cookie; 786 vme_intr_handle_t vih; 787 int pri; 788 int (*func) __P((void *)); 789 void *arg; 790 { 791 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 792 struct sparc_vme_intr_handle *svih = 793 (struct sparc_vme_intr_handle *)vih; 794 struct intrhand *ih; 795 int level; 796 797 /* XXX pri == svih->pri ??? */ 798 799 /* Translate VME priority to processor IPL */ 800 level = vme_ipl_to_pil[svih->pri]; 801 802 svih->ih.ih_fun = func; 803 svih->ih.ih_arg = arg; 804 svih->next = NULL; 805 806 /* ensure the interrupt subsystem will call us at this level */ 807 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 808 if (ih->ih_fun == sc->sc_vmeintr) 809 break; 810 811 if (ih == NULL) { 812 ih = (struct intrhand *) 813 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 814 if (ih == NULL) 815 panic("vme_addirq"); 816 bzero(ih, sizeof *ih); 817 ih->ih_fun = sc->sc_vmeintr; 818 ih->ih_arg = vih; 819 intr_establish(level, ih); 820 } else { 821 svih->next = (vme_intr_handle_t)ih->ih_arg; 822 ih->ih_arg = vih; 823 } 824 return (NULL); 825 } 826 827 void 828 sparc_vme_unmap(cookie, resc) 829 void * cookie; 830 vme_mapresc_t resc; 831 { 832 /* Not implemented */ 833 panic("sparc_vme_unmap"); 834 } 835 836 void 837 sparc_vme_intr_disestablish(cookie, a) 838 void *cookie; 839 void *a; 840 { 841 /* Not implemented */ 842 panic("sparc_vme_intr_disestablish"); 843 } 844 845 846 847 /* 848 * VME DMA functions. 849 */ 850 851 static void 852 sparc_vct_dmamap_destroy(cookie, map) 853 void *cookie; 854 bus_dmamap_t map; 855 { 856 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 857 bus_dmamap_destroy(sc->sc_dmatag, map); 858 } 859 860 #if defined(SUN4) 861 static int 862 sparc_vct4_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 863 boundary, flags, dmamp) 864 void *cookie; 865 vme_size_t size; 866 vme_am_t am; 867 vme_datasize_t datasize; 868 vme_swap_t swap; 869 int nsegments; 870 vme_size_t maxsegsz; 871 vme_addr_t boundary; 872 int flags; 873 bus_dmamap_t *dmamp; 874 { 875 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 876 877 /* Allocate a base map through parent bus ops */ 878 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 879 boundary, flags, dmamp)); 880 } 881 882 int 883 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 884 bus_dma_tag_t t; 885 bus_dmamap_t map; 886 void *buf; 887 bus_size_t buflen; 888 struct proc *p; 889 int flags; 890 { 891 bus_addr_t dva; 892 bus_size_t sgsize; 893 vaddr_t va, voff; 894 pmap_t pmap; 895 int pagesz = PAGE_SIZE; 896 int error; 897 898 cpuinfo.cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 899 900 va = (vaddr_t)buf; 901 voff = va & (pagesz - 1); 902 va &= -pagesz; 903 904 /* 905 * Allocate an integral number of pages from DVMA space 906 * covering the passed buffer. 907 */ 908 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 909 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 910 map->_dm_boundary, 911 (flags & BUS_DMA_NOWAIT) == 0 912 ? EX_WAITOK 913 : EX_NOWAIT, 914 (u_long *)&dva); 915 if (error != 0) 916 return (error); 917 918 map->dm_mapsize = buflen; 919 map->dm_nsegs = 1; 920 /* Adjust DVMA address to VME view */ 921 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 922 map->dm_segs[0].ds_len = buflen; 923 map->dm_segs[0]._ds_sgsize = sgsize; 924 925 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 926 927 for (; sgsize != 0; ) { 928 paddr_t pa; 929 /* 930 * Get the physical address for this page. 931 */ 932 (void) pmap_extract(pmap, va, &pa); 933 934 #ifdef notyet 935 if (have_iocache) 936 pa |= PG_IOC; 937 #endif 938 pmap_enter(pmap_kernel(), dva, 939 pa | PMAP_NC, 940 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 941 942 dva += pagesz; 943 va += pagesz; 944 sgsize -= pagesz; 945 } 946 947 return (0); 948 } 949 950 void 951 sparc_vme4_dmamap_unload(t, map) 952 bus_dma_tag_t t; 953 bus_dmamap_t map; 954 { 955 bus_dma_segment_t *segs = map->dm_segs; 956 int nsegs = map->dm_nsegs; 957 bus_addr_t dva; 958 bus_size_t len; 959 int i, s, error; 960 961 for (i = 0; i < nsegs; i++) { 962 /* Go from VME to CPU view */ 963 dva = segs[i].ds_addr + VME4_DVMA_BASE; 964 dva &= -PAGE_SIZE; 965 len = segs[i]._ds_sgsize; 966 967 /* Remove double-mapping in DVMA space */ 968 pmap_remove(pmap_kernel(), dva, dva + len); 969 970 /* Release DVMA space */ 971 s = splhigh(); 972 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 973 splx(s); 974 if (error != 0) 975 printf("warning: %ld of DVMA space lost\n", len); 976 } 977 978 /* Mark the mappings as invalid. */ 979 map->dm_mapsize = 0; 980 map->dm_nsegs = 0; 981 } 982 983 void 984 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 985 bus_dma_tag_t t; 986 bus_dmamap_t map; 987 bus_addr_t offset; 988 bus_size_t len; 989 int ops; 990 { 991 992 /* 993 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 994 * Currently the cache is flushed in bus_dma_load()... 995 */ 996 } 997 #endif /* SUN4 */ 998 999 #if defined(SUN4M) 1000 static int 1001 sparc_vme_iommu_dmamap_create (t, size, nsegments, maxsegsz, 1002 boundary, flags, dmamp) 1003 bus_dma_tag_t t; 1004 bus_size_t size; 1005 int nsegments; 1006 bus_size_t maxsegsz; 1007 bus_size_t boundary; 1008 int flags; 1009 bus_dmamap_t *dmamp; 1010 { 1011 1012 printf("sparc_vme_dmamap_create: please use `vme_dmamap_create'\n"); 1013 return (EINVAL); 1014 } 1015 1016 static int 1017 sparc_vct_iommu_dmamap_create(cookie, size, am, datasize, swap, nsegments, 1018 maxsegsz, boundary, flags, dmamp) 1019 void *cookie; 1020 vme_size_t size; 1021 vme_am_t am; 1022 vme_datasize_t datasize; 1023 vme_swap_t swap; 1024 int nsegments; 1025 vme_size_t maxsegsz; 1026 vme_addr_t boundary; 1027 int flags; 1028 bus_dmamap_t *dmamp; 1029 { 1030 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 1031 bus_dmamap_t map; 1032 int error; 1033 1034 /* Allocate a base map through parent bus ops */ 1035 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1036 boundary, flags, &map); 1037 if (error != 0) 1038 return (error); 1039 1040 /* 1041 * Each I/O cache line maps to a 8K section of VME DVMA space, so 1042 * we must ensure that DVMA alloctions are always 8K aligned. 1043 */ 1044 map->_dm_align = VME_IOC_PAGESZ; 1045 1046 /* Set map region based on Address Modifier */ 1047 switch ((am & VME_AM_ADRSIZEMASK)) { 1048 case VME_AM_A16: 1049 case VME_AM_A24: 1050 /* 1 MB of DVMA space */ 1051 map->_dm_ex_start = VME_IOMMU_DVMA_AM24_BASE; 1052 map->_dm_ex_end = VME_IOMMU_DVMA_AM24_END; 1053 break; 1054 case VME_AM_A32: 1055 /* 8 MB of DVMA space */ 1056 map->_dm_ex_start = VME_IOMMU_DVMA_AM32_BASE; 1057 map->_dm_ex_end = VME_IOMMU_DVMA_AM32_END; 1058 break; 1059 } 1060 1061 *dmamp = map; 1062 return (0); 1063 } 1064 1065 int 1066 sparc_vme_iommu_dmamap_load(t, map, buf, buflen, p, flags) 1067 bus_dma_tag_t t; 1068 bus_dmamap_t map; 1069 void *buf; 1070 bus_size_t buflen; 1071 struct proc *p; 1072 int flags; 1073 { 1074 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1075 volatile u_int32_t *ioctags; 1076 int error; 1077 1078 /* Round request to a multiple of the I/O cache size */ 1079 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 1080 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1081 if (error != 0) 1082 return (error); 1083 1084 /* Allocate I/O cache entries for this range */ 1085 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1086 while (buflen > 0) { 1087 *ioctags = VME_IOC_IC | VME_IOC_W; 1088 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1089 buflen -= VME_IOC_PAGESZ; 1090 } 1091 1092 /* 1093 * Adjust DVMA address to VME view. 1094 * Note: the DVMA base address is the same for all 1095 * VME address spaces. 1096 */ 1097 map->dm_segs[0].ds_addr -= VME_IOMMU_DVMA_BASE; 1098 return (0); 1099 } 1100 1101 1102 void 1103 sparc_vme_iommu_dmamap_unload(t, map) 1104 bus_dma_tag_t t; 1105 bus_dmamap_t map; 1106 { 1107 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1108 volatile u_int32_t *flushregs; 1109 int len; 1110 1111 /* Go from VME to CPU view */ 1112 map->dm_segs[0].ds_addr += VME_IOMMU_DVMA_BASE; 1113 1114 /* Flush VME I/O cache */ 1115 len = map->dm_segs[0]._ds_sgsize; 1116 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1117 while (len > 0) { 1118 *flushregs = 0; 1119 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1120 len -= VME_IOC_PAGESZ; 1121 } 1122 1123 /* 1124 * Start a read from `tag space' which will not complete until 1125 * all cache flushes have finished 1126 */ 1127 (*sc->sc_ioctags); 1128 1129 bus_dmamap_unload(sc->sc_dmatag, map); 1130 } 1131 1132 void 1133 sparc_vme_iommu_dmamap_sync(t, map, offset, len, ops) 1134 bus_dma_tag_t t; 1135 bus_dmamap_t map; 1136 bus_addr_t offset; 1137 bus_size_t len; 1138 int ops; 1139 { 1140 1141 /* 1142 * XXX Should perform cache flushes as necessary. 1143 */ 1144 } 1145 #endif /* SUN4M */ 1146 1147 int 1148 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1149 bus_dma_tag_t t; 1150 bus_dma_segment_t *segs; 1151 int nsegs; 1152 size_t size; 1153 caddr_t *kvap; 1154 int flags; 1155 { 1156 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1157 1158 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1159 } 1160
Indexes created Thu Sep 25 16:09:42 GMT 2025