vme_machdep.c revision 1.35
1 /* $NetBSD: vme_machdep.c,v 1.35 2002/03/11 16:27:02 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/errno.h> 45 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/syslog.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #define _SPARC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 #include <sparc/sparc/iommuvar.h> 55 #include <machine/autoconf.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmereg.h> 61 #include <dev/vme/vmevar.h> 62 63 #include <sparc/sparc/asm.h> 64 #include <sparc/sparc/vaddrs.h> 65 #include <sparc/sparc/cpuvar.h> 66 #include <sparc/dev/vmereg.h> 67 68 struct sparcvme_softc { 69 struct device sc_dev; /* base device */ 70 bus_space_tag_t sc_bustag; 71 bus_dma_tag_t sc_dmatag; 72 struct vmebusreg *sc_reg; /* VME control registers */ 73 struct vmebusvec *sc_vec; /* VME interrupt vector */ 74 struct rom_range *sc_range; /* ROM range property */ 75 int sc_nrange; 76 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 77 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 78 int (*sc_vmeintr) __P((void *)); 79 }; 80 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 static int sparc_vme_error __P((void)); 93 #endif 94 95 96 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 97 vme_am_t, vme_datasize_t, 98 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 99 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 100 vme_datasize_t, vme_swap_t, 101 bus_space_tag_t *, bus_space_handle_t *, 102 vme_mapresc_t *)); 103 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 104 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 105 static const struct evcnt *sparc_vme_intr_evcnt __P((void *, 106 vme_intr_handle_t)); 107 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 108 int (*) __P((void *)), void *)); 109 static void sparc_vme_intr_disestablish __P((void *, void *)); 110 111 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 112 vme_addr_t, bus_addr_t *)); 113 #if defined(SUN4M) 114 static void sparc_vme_iommu_barrier __P(( bus_space_tag_t, bus_space_handle_t, 115 bus_size_t, bus_size_t, int)); 116 117 #endif 118 119 /* 120 * DMA functions. 121 */ 122 static void sparc_vct_dmamap_destroy __P((void *, bus_dmamap_t)); 123 124 #if defined(SUN4) 125 static int sparc_vct4_dmamap_create __P((void *, vme_size_t, vme_am_t, 126 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 127 int, bus_dmamap_t *)); 128 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 129 bus_size_t, struct proc *, int)); 130 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 131 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 132 bus_addr_t, bus_size_t, int)); 133 #endif 134 135 #if defined(SUN4M) 136 static int sparc_vct_iommu_dmamap_create __P((void *, vme_size_t, vme_am_t, 137 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 138 int, bus_dmamap_t *)); 139 static int sparc_vme_iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, 140 int, bus_size_t, bus_size_t, int, bus_dmamap_t *)); 141 142 static int sparc_vme_iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, 143 void *, bus_size_t, struct proc *, int)); 144 static void sparc_vme_iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 145 static void sparc_vme_iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 146 bus_addr_t, bus_size_t, int)); 147 #endif 148 149 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 150 int, size_t, caddr_t *, int)); 151 #if 0 152 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 153 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 154 static paddr_t sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 155 bus_dma_segment_t *, int, off_t, int, int)); 156 #endif 157 158 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 159 160 struct cfattach vme_mainbus_ca = { 161 sizeof(struct sparcvme_softc), vmematch_mainbus, vmeattach_mainbus 162 }; 163 164 struct cfattach vme_iommu_ca = { 165 sizeof(struct sparcvme_softc), vmematch_iommu, vmeattach_iommu 166 }; 167 168 int (*vmeerr_handler) __P((void)); 169 170 #define VMEMOD_D32 0x40 /* ??? */ 171 172 /* If the PROM does not provide the `ranges' property, we make up our own */ 173 struct rom_range vmebus_translations[] = { 174 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 175 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 176 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 177 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 178 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 179 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 180 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 181 #undef _DS 182 }; 183 184 /* 185 * The VME bus logic on sun4 machines maps DMA requests in the first MB 186 * of VME space to the last MB of DVMA space. `vme_dvmamap' is used 187 * for DVMA space allocations. The DMA addresses returned by 188 * bus_dmamap_load*() must be relocated by -VME4_DVMA_BASE. 189 */ 190 struct extent *vme_dvmamap; 191 192 /* 193 * The VME hardware on the sun4m IOMMU maps the first 8MB of 32-bit 194 * VME space to the last 8MB of DVMA space and the first 1MB of 195 * 24-bit VME space to the first 1MB of the last 8MB of DVMA space 196 * (thus 24-bit VME space overlaps the first 1MB of of 32-bit space). 197 * The following constants define subregions in the IOMMU DVMA map 198 * for VME DVMA allocations. The DMA addresses returned by 199 * bus_dmamap_load*() must be relocated by -VME_IOMMU_DVMA_BASE. 200 */ 201 #define VME_IOMMU_DVMA_BASE 0xff800000 202 #define VME_IOMMU_DVMA_AM24_BASE VME_IOMMU_DVMA_BASE 203 #define VME_IOMMU_DVMA_AM24_END 0xff900000 204 #define VME_IOMMU_DVMA_AM32_BASE VME_IOMMU_DVMA_BASE 205 #define VME_IOMMU_DVMA_AM32_END IOMMU_DVMA_END 206 207 struct sparc_bus_space_tag sparc_vme_bus_tag = { 208 NULL, /* cookie */ 209 NULL, /* parent bus tag */ 210 NULL, /* bus_map */ 211 NULL, /* bus_unmap */ 212 NULL, /* bus_subregion */ 213 NULL /* barrier */ 214 }; 215 216 struct vme_chipset_tag sparc_vme_chipset_tag = { 217 NULL, 218 sparc_vme_map, 219 sparc_vme_unmap, 220 sparc_vme_probe, 221 sparc_vme_intr_map, 222 sparc_vme_intr_evcnt, 223 sparc_vme_intr_establish, 224 sparc_vme_intr_disestablish, 225 0, 0, 0 /* bus specific DMA stuff */ 226 }; 227 228 229 #if defined(SUN4) 230 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 231 NULL, /* cookie */ 232 _bus_dmamap_create, 233 _bus_dmamap_destroy, 234 sparc_vme4_dmamap_load, 235 _bus_dmamap_load_mbuf, 236 _bus_dmamap_load_uio, 237 _bus_dmamap_load_raw, 238 sparc_vme4_dmamap_unload, 239 sparc_vme4_dmamap_sync, 240 241 _bus_dmamem_alloc, 242 _bus_dmamem_free, 243 sparc_vme_dmamem_map, 244 _bus_dmamem_unmap, 245 _bus_dmamem_mmap 246 }; 247 #endif 248 249 #if defined(SUN4M) 250 struct sparc_bus_dma_tag sparc_vme_iommu_dma_tag = { 251 NULL, /* cookie */ 252 sparc_vme_iommu_dmamap_create, 253 _bus_dmamap_destroy, 254 sparc_vme_iommu_dmamap_load, 255 _bus_dmamap_load_mbuf, 256 _bus_dmamap_load_uio, 257 _bus_dmamap_load_raw, 258 sparc_vme_iommu_dmamap_unload, 259 sparc_vme_iommu_dmamap_sync, 260 261 _bus_dmamem_alloc, 262 _bus_dmamem_free, 263 sparc_vme_dmamem_map, 264 _bus_dmamem_unmap, 265 _bus_dmamem_mmap 266 }; 267 #endif 268 269 270 int 271 vmematch_mainbus(parent, cf, aux) 272 struct device *parent; 273 struct cfdata *cf; 274 void *aux; 275 { 276 struct mainbus_attach_args *ma = aux; 277 278 if (!CPU_ISSUN4) 279 return (0); 280 281 return (strcmp("vme", ma->ma_name) == 0); 282 } 283 284 int 285 vmematch_iommu(parent, cf, aux) 286 struct device *parent; 287 struct cfdata *cf; 288 void *aux; 289 { 290 struct iommu_attach_args *ia = aux; 291 292 return (strcmp("vme", ia->iom_name) == 0); 293 } 294 295 296 void 297 vmeattach_mainbus(parent, self, aux) 298 struct device *parent, *self; 299 void *aux; 300 { 301 #if defined(SUN4) 302 struct mainbus_attach_args *ma = aux; 303 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 304 struct vmebus_attach_args vba; 305 306 if (self->dv_unit > 0) { 307 printf(" unsupported\n"); 308 return; 309 } 310 311 sc->sc_bustag = ma->ma_bustag; 312 sc->sc_dmatag = ma->ma_dmatag; 313 314 /* VME interrupt entry point */ 315 sc->sc_vmeintr = vmeintr4; 316 317 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 318 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 319 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 320 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 321 322 #if 0 323 sparc_vme_bus_tag.parent = ma->ma_bustag; 324 vba.vba_bustag = &sparc_vme_bus_tag; 325 #endif 326 vba.va_vct = &sparc_vme_chipset_tag; 327 vba.va_bdt = &sparc_vme4_dma_tag; 328 vba.va_slaveconfig = 0; 329 330 /* Fall back to our own `range' construction */ 331 sc->sc_range = vmebus_translations; 332 sc->sc_nrange = 333 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 334 335 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 336 M_DEVBUF, 0, 0, EX_NOWAIT); 337 if (vme_dvmamap == NULL) 338 panic("vme: unable to allocate DVMA map"); 339 340 printf("\n"); 341 (void)config_found(self, &vba, 0); 342 343 #endif 344 return; 345 } 346 347 /* sun4m vmebus */ 348 void 349 vmeattach_iommu(parent, self, aux) 350 struct device *parent, *self; 351 void *aux; 352 { 353 #if defined(SUN4M) 354 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 355 struct iommu_attach_args *ia = aux; 356 struct vmebus_attach_args vba; 357 bus_space_handle_t bh; 358 int node; 359 int cline; 360 361 if (self->dv_unit > 0) { 362 printf(" unsupported\n"); 363 return; 364 } 365 366 sc->sc_bustag = ia->iom_bustag; 367 sc->sc_dmatag = ia->iom_dmatag; 368 369 /* VME interrupt entry point */ 370 sc->sc_vmeintr = vmeintr4m; 371 372 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 373 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct_iommu_dmamap_create; 374 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 375 /*XXX*/ sparc_vme_iommu_dma_tag._cookie = self; 376 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme_iommu_barrier; 377 378 #if 0 379 vba.vba_bustag = &sparc_vme_bus_tag; 380 #endif 381 vba.va_vct = &sparc_vme_chipset_tag; 382 vba.va_bdt = &sparc_vme_iommu_dma_tag; 383 vba.va_slaveconfig = 0; 384 385 node = ia->iom_node; 386 387 /* 388 * Map VME control space 389 */ 390 if (ia->iom_nreg < 2) { 391 printf("%s: only %d register sets\n", self->dv_xname, 392 ia->iom_nreg); 393 return; 394 } 395 396 if (bus_space_map(ia->iom_bustag, 397 (bus_addr_t) BUS_ADDR(ia->iom_reg[0].ior_iospace, 398 ia->iom_reg[0].ior_pa), 399 (bus_size_t)ia->iom_reg[0].ior_size, 400 BUS_SPACE_MAP_LINEAR, 401 &bh) != 0) { 402 panic("%s: can't map vmebusreg", self->dv_xname); 403 } 404 sc->sc_reg = (struct vmebusreg *)bh; 405 406 if (bus_space_map(ia->iom_bustag, 407 (bus_addr_t) BUS_ADDR(ia->iom_reg[1].ior_iospace, 408 ia->iom_reg[1].ior_pa), 409 (bus_size_t)ia->iom_reg[1].ior_size, 410 BUS_SPACE_MAP_LINEAR, 411 &bh) != 0) { 412 panic("%s: can't map vmebusvec", self->dv_xname); 413 } 414 sc->sc_vec = (struct vmebusvec *)bh; 415 416 /* 417 * Map VME IO cache tags and flush control. 418 */ 419 if (bus_space_map(ia->iom_bustag, 420 (bus_addr_t) BUS_ADDR( 421 ia->iom_reg[1].ior_iospace, 422 ia->iom_reg[1].ior_pa + VME_IOC_TAGOFFSET), 423 VME_IOC_SIZE, 424 BUS_SPACE_MAP_LINEAR, 425 &bh) != 0) { 426 panic("%s: can't map IOC tags", self->dv_xname); 427 } 428 sc->sc_ioctags = (u_int32_t *)bh; 429 430 if (bus_space_map(ia->iom_bustag, 431 (bus_addr_t) BUS_ADDR( 432 ia->iom_reg[1].ior_iospace, 433 ia->iom_reg[1].ior_pa + VME_IOC_FLUSHOFFSET), 434 VME_IOC_SIZE, 435 BUS_SPACE_MAP_LINEAR, 436 &bh) != 0) { 437 panic("%s: can't map IOC flush registers", self->dv_xname); 438 } 439 sc->sc_iocflush = (u_int32_t *)bh; 440 441 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 442 443 /* 444 * Get "range" property. 445 */ 446 if (PROM_getprop(node, "ranges", sizeof(struct rom_range), 447 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 448 panic("%s: can't get ranges property", self->dv_xname); 449 } 450 451 sparcvme_sc = sc; 452 vmeerr_handler = sparc_vme_error; 453 454 /* 455 * Invalidate all IO-cache entries. 456 */ 457 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 458 sc->sc_ioctags[--cline] = 0; 459 } 460 461 /* Enable IO-cache */ 462 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 463 464 printf(": version 0x%x\n", 465 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 466 467 (void)config_found(self, &vba, 0); 468 #endif 469 } 470 471 #if defined(SUN4M) 472 static int 473 sparc_vme_error() 474 { 475 struct sparcvme_softc *sc = sparcvme_sc; 476 u_int32_t afsr, afpa; 477 char bits[64]; 478 479 afsr = sc->sc_reg->vmebus_afsr; 480 afpa = sc->sc_reg->vmebus_afar; 481 printf("VME error:\n\tAFSR %s\n", 482 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 483 printf("\taddress: 0x%x%x\n", afsr, afpa); 484 return (0); 485 } 486 #endif 487 488 int 489 vmebus_translate(sc, mod, addr, bap) 490 struct sparcvme_softc *sc; 491 vme_am_t mod; 492 vme_addr_t addr; 493 bus_addr_t *bap; 494 { 495 int i; 496 497 for (i = 0; i < sc->sc_nrange; i++) { 498 struct rom_range *rp = &sc->sc_range[i]; 499 500 if (rp->cspace != mod) 501 continue; 502 503 /* We've found the connection to the parent bus */ 504 *bap = BUS_ADDR(rp->pspace, rp->poffset + addr); 505 return (0); 506 } 507 return (ENOENT); 508 } 509 510 struct vmeprobe_myarg { 511 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 512 void *cbarg; 513 bus_space_tag_t tag; 514 int res; /* backwards */ 515 }; 516 517 static int vmeprobe_mycb __P((void *, void *)); 518 static int 519 vmeprobe_mycb(bh, arg) 520 void *bh, *arg; 521 { 522 struct vmeprobe_myarg *a = arg; 523 524 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 525 return (!a->res); 526 } 527 528 int 529 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 530 void *cookie; 531 vme_addr_t addr; 532 vme_size_t len; 533 vme_am_t mod; 534 vme_datasize_t datasize; 535 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 536 void *arg; 537 { 538 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 539 bus_addr_t paddr; 540 bus_size_t size; 541 struct vmeprobe_myarg myarg; 542 int res, i; 543 544 if (vmebus_translate(sc, mod, addr, &paddr) != 0) 545 return (EINVAL); 546 547 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 548 549 if (callback) { 550 myarg.cb = callback; 551 myarg.cbarg = arg; 552 myarg.tag = sc->sc_bustag; 553 myarg.res = 0; 554 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 555 0, vmeprobe_mycb, &myarg); 556 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 557 } 558 559 for (i = 0; i < len / size; i++) { 560 myarg.res = 0; 561 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 562 0, 0, 0); 563 if (res == 0) 564 return (EIO); 565 paddr += size; 566 } 567 return (0); 568 } 569 570 int 571 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 572 void *cookie; 573 vme_addr_t addr; 574 vme_size_t size; 575 vme_am_t mod; 576 vme_datasize_t datasize; 577 vme_swap_t swap; 578 bus_space_tag_t *tp; 579 bus_space_handle_t *hp; 580 vme_mapresc_t *rp; 581 { 582 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 583 bus_addr_t paddr; 584 int error; 585 586 error = vmebus_translate(sc, mod, addr, &paddr); 587 if (error != 0) 588 return (error); 589 590 *tp = sc->sc_bustag; 591 return (bus_space_map(sc->sc_bustag, paddr, size, 0, hp)); 592 } 593 594 int 595 sparc_vme_mmap_cookie(addr, mod, hp) 596 vme_addr_t addr; 597 vme_am_t mod; 598 bus_space_handle_t *hp; 599 { 600 struct sparcvme_softc *sc = sparcvme_sc; 601 bus_addr_t paddr; 602 int error; 603 604 error = vmebus_translate(sc, mod, addr, &paddr); 605 if (error != 0) 606 return (error); 607 608 return (bus_space_mmap(sc->sc_bustag, paddr, 0, 609 0/*prot is ignored*/, 0)); 610 } 611 612 #if defined(SUN4M) 613 void 614 sparc_vme_iommu_barrier(t, h, offset, size, flags) 615 bus_space_tag_t t; 616 bus_space_handle_t h; 617 bus_size_t offset; 618 bus_size_t size; 619 int flags; 620 { 621 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 622 623 /* Read async fault status to flush write-buffers */ 624 (*(volatile int *)&vbp->vmebus_afsr); 625 } 626 #endif 627 628 629 630 /* 631 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 632 */ 633 static int vme_ipl_to_pil[] = { 634 0, 635 2, 636 3, 637 5, 638 7, 639 9, 640 11, 641 13 642 }; 643 644 645 /* 646 * All VME device interrupts go through vmeintr(). This function reads 647 * the VME vector from the bus, then dispatches the device interrupt 648 * handler. All handlers for devices that map to the same Processor 649 * Interrupt Level (according to the table above) are on a linked list 650 * of `sparc_vme_intr_handle' structures. The head of which is passed 651 * down as the argument to `vmeintr(void *arg)'. 652 */ 653 struct sparc_vme_intr_handle { 654 struct intrhand ih; 655 struct sparc_vme_intr_handle *next; 656 int vec; /* VME interrupt vector */ 657 int pri; /* VME interrupt priority */ 658 struct sparcvme_softc *sc;/*XXX*/ 659 }; 660 661 #if defined(SUN4) 662 int 663 vmeintr4(arg) 664 void *arg; 665 { 666 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 667 int level, vec; 668 int rv = 0; 669 670 level = (ihp->pri << 1) | 1; 671 672 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 673 674 if (vec == -1) { 675 #ifdef DEBUG 676 /* 677 * This seems to happen only with the i82586 based 678 * `ie1' boards. 679 */ 680 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 681 #endif 682 return (1); /* XXX - pretend we handled it, for now */ 683 } 684 685 for (; ihp; ihp = ihp->next) 686 if (ihp->vec == vec && ihp->ih.ih_fun) 687 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 688 689 return (rv); 690 } 691 #endif 692 693 #if defined(SUN4M) 694 int 695 vmeintr4m(arg) 696 void *arg; 697 { 698 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 699 int level, vec; 700 int rv = 0; 701 702 level = (ihp->pri << 1) | 1; 703 704 #if 0 705 int pending; 706 707 /* Flush VME <=> Sbus write buffers */ 708 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 709 710 pending = *((int*)ICR_SI_PEND); 711 if ((pending & SINTR_VME(ihp->pri)) == 0) { 712 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 713 ihp->pri, pending); 714 return (0); 715 } 716 #endif 717 #if 0 718 /* Why gives this a bus timeout sometimes? */ 719 vec = ihp->sc->sc_vec->vmebusvec[level]; 720 #else 721 /* so, arrange to catch the fault... */ 722 { 723 extern struct user *proc0paddr; 724 extern int fkbyte __P((caddr_t, struct pcb *)); 725 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 726 struct pcb *xpcb; 727 u_long saveonfault; 728 int s; 729 730 s = splhigh(); 731 if (curproc == NULL) 732 xpcb = (struct pcb *)proc0paddr; 733 else 734 xpcb = &curproc->p_addr->u_pcb; 735 736 saveonfault = (u_long)xpcb->pcb_onfault; 737 vec = fkbyte(addr, xpcb); 738 xpcb->pcb_onfault = (caddr_t)saveonfault; 739 740 splx(s); 741 } 742 #endif 743 744 if (vec == -1) { 745 #ifdef DEBUG 746 /* 747 * This seems to happen only with the i82586 based 748 * `ie1' boards. 749 */ 750 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 751 printf(" ICR_SI_PEND=0x%x; VME AFSR=0x%x; VME AFAR=0x%x\n", 752 *((int*)ICR_SI_PEND), 753 ihp->sc->sc_reg->vmebus_afsr, 754 ihp->sc->sc_reg->vmebus_afar); 755 #endif 756 return (1); /* XXX - pretend we handled it, for now */ 757 } 758 759 for (; ihp; ihp = ihp->next) 760 if (ihp->vec == vec && ihp->ih.ih_fun) 761 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 762 763 return (rv); 764 } 765 #endif 766 767 int 768 sparc_vme_intr_map(cookie, level, vec, ihp) 769 void *cookie; 770 int level; 771 int vec; 772 vme_intr_handle_t *ihp; 773 { 774 struct sparc_vme_intr_handle *ih; 775 776 ih = (vme_intr_handle_t) 777 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 778 ih->pri = level; 779 ih->vec = vec; 780 ih->sc = cookie;/*XXX*/ 781 *ihp = ih; 782 return (0); 783 } 784 785 const struct evcnt * 786 sparc_vme_intr_evcnt(cookie, vih) 787 void *cookie; 788 vme_intr_handle_t vih; 789 { 790 791 /* XXX for now, no evcnt parent reported */ 792 return NULL; 793 } 794 795 void * 796 sparc_vme_intr_establish(cookie, vih, pri, func, arg) 797 void *cookie; 798 vme_intr_handle_t vih; 799 int pri; 800 int (*func) __P((void *)); 801 void *arg; 802 { 803 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 804 struct sparc_vme_intr_handle *svih = 805 (struct sparc_vme_intr_handle *)vih; 806 struct intrhand *ih; 807 int level; 808 809 /* XXX pri == svih->pri ??? */ 810 811 /* Translate VME priority to processor IPL */ 812 level = vme_ipl_to_pil[svih->pri]; 813 814 svih->ih.ih_fun = func; 815 svih->ih.ih_arg = arg; 816 svih->next = NULL; 817 818 /* ensure the interrupt subsystem will call us at this level */ 819 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 820 if (ih->ih_fun == sc->sc_vmeintr) 821 break; 822 823 if (ih == NULL) { 824 ih = (struct intrhand *) 825 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 826 if (ih == NULL) 827 panic("vme_addirq"); 828 bzero(ih, sizeof *ih); 829 ih->ih_fun = sc->sc_vmeintr; 830 ih->ih_arg = vih; 831 intr_establish(level, ih); 832 } else { 833 svih->next = (vme_intr_handle_t)ih->ih_arg; 834 ih->ih_arg = vih; 835 } 836 return (NULL); 837 } 838 839 void 840 sparc_vme_unmap(cookie, resc) 841 void * cookie; 842 vme_mapresc_t resc; 843 { 844 /* Not implemented */ 845 panic("sparc_vme_unmap"); 846 } 847 848 void 849 sparc_vme_intr_disestablish(cookie, a) 850 void *cookie; 851 void *a; 852 { 853 /* Not implemented */ 854 panic("sparc_vme_intr_disestablish"); 855 } 856 857 858 859 /* 860 * VME DMA functions. 861 */ 862 863 static void 864 sparc_vct_dmamap_destroy(cookie, map) 865 void *cookie; 866 bus_dmamap_t map; 867 { 868 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 869 bus_dmamap_destroy(sc->sc_dmatag, map); 870 } 871 872 #if defined(SUN4) 873 static int 874 sparc_vct4_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 875 boundary, flags, dmamp) 876 void *cookie; 877 vme_size_t size; 878 vme_am_t am; 879 vme_datasize_t datasize; 880 vme_swap_t swap; 881 int nsegments; 882 vme_size_t maxsegsz; 883 vme_addr_t boundary; 884 int flags; 885 bus_dmamap_t *dmamp; 886 { 887 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 888 889 /* Allocate a base map through parent bus ops */ 890 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 891 boundary, flags, dmamp)); 892 } 893 894 int 895 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 896 bus_dma_tag_t t; 897 bus_dmamap_t map; 898 void *buf; 899 bus_size_t buflen; 900 struct proc *p; 901 int flags; 902 { 903 bus_addr_t dva; 904 bus_size_t sgsize; 905 vaddr_t va, voff; 906 pmap_t pmap; 907 int pagesz = PAGE_SIZE; 908 int error; 909 910 cpuinfo.cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 911 912 va = (vaddr_t)buf; 913 voff = va & (pagesz - 1); 914 va &= -pagesz; 915 916 /* 917 * Allocate an integral number of pages from DVMA space 918 * covering the passed buffer. 919 */ 920 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 921 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 922 map->_dm_boundary, 923 (flags & BUS_DMA_NOWAIT) == 0 924 ? EX_WAITOK 925 : EX_NOWAIT, 926 (u_long *)&dva); 927 if (error != 0) 928 return (error); 929 930 map->dm_mapsize = buflen; 931 map->dm_nsegs = 1; 932 /* Adjust DVMA address to VME view */ 933 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 934 map->dm_segs[0].ds_len = buflen; 935 map->dm_segs[0]._ds_sgsize = sgsize; 936 937 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 938 939 for (; sgsize != 0; ) { 940 paddr_t pa; 941 /* 942 * Get the physical address for this page. 943 */ 944 (void) pmap_extract(pmap, va, &pa); 945 946 #ifdef notyet 947 if (have_iocache) 948 pa |= PG_IOC; 949 #endif 950 pmap_enter(pmap_kernel(), dva, 951 pa | PMAP_NC, 952 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 953 954 dva += pagesz; 955 va += pagesz; 956 sgsize -= pagesz; 957 } 958 pmap_update(pmap_kernel()); 959 960 return (0); 961 } 962 963 void 964 sparc_vme4_dmamap_unload(t, map) 965 bus_dma_tag_t t; 966 bus_dmamap_t map; 967 { 968 bus_dma_segment_t *segs = map->dm_segs; 969 int nsegs = map->dm_nsegs; 970 bus_addr_t dva; 971 bus_size_t len; 972 int i, s, error; 973 974 for (i = 0; i < nsegs; i++) { 975 /* Go from VME to CPU view */ 976 dva = segs[i].ds_addr + VME4_DVMA_BASE; 977 dva &= -PAGE_SIZE; 978 len = segs[i]._ds_sgsize; 979 980 /* Remove double-mapping in DVMA space */ 981 pmap_remove(pmap_kernel(), dva, dva + len); 982 983 /* Release DVMA space */ 984 s = splhigh(); 985 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 986 splx(s); 987 if (error != 0) 988 printf("warning: %ld of DVMA space lost\n", len); 989 } 990 pmap_update(pmap_kernel()); 991 992 /* Mark the mappings as invalid. */ 993 map->dm_mapsize = 0; 994 map->dm_nsegs = 0; 995 } 996 997 void 998 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 999 bus_dma_tag_t t; 1000 bus_dmamap_t map; 1001 bus_addr_t offset; 1002 bus_size_t len; 1003 int ops; 1004 { 1005 1006 /* 1007 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 1008 * Currently the cache is flushed in bus_dma_load()... 1009 */ 1010 } 1011 #endif /* SUN4 */ 1012 1013 #if defined(SUN4M) 1014 static int 1015 sparc_vme_iommu_dmamap_create (t, size, nsegments, maxsegsz, 1016 boundary, flags, dmamp) 1017 bus_dma_tag_t t; 1018 bus_size_t size; 1019 int nsegments; 1020 bus_size_t maxsegsz; 1021 bus_size_t boundary; 1022 int flags; 1023 bus_dmamap_t *dmamp; 1024 { 1025 1026 printf("sparc_vme_dmamap_create: please use `vme_dmamap_create'\n"); 1027 return (EINVAL); 1028 } 1029 1030 static int 1031 sparc_vct_iommu_dmamap_create(cookie, size, am, datasize, swap, nsegments, 1032 maxsegsz, boundary, flags, dmamp) 1033 void *cookie; 1034 vme_size_t size; 1035 vme_am_t am; 1036 vme_datasize_t datasize; 1037 vme_swap_t swap; 1038 int nsegments; 1039 vme_size_t maxsegsz; 1040 vme_addr_t boundary; 1041 int flags; 1042 bus_dmamap_t *dmamp; 1043 { 1044 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 1045 bus_dmamap_t map; 1046 int error; 1047 1048 /* Allocate a base map through parent bus ops */ 1049 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1050 boundary, flags, &map); 1051 if (error != 0) 1052 return (error); 1053 1054 /* 1055 * Each I/O cache line maps to a 8K section of VME DVMA space, so 1056 * we must ensure that DVMA alloctions are always 8K aligned. 1057 */ 1058 map->_dm_align = VME_IOC_PAGESZ; 1059 1060 /* Set map region based on Address Modifier */ 1061 switch ((am & VME_AM_ADRSIZEMASK)) { 1062 case VME_AM_A16: 1063 case VME_AM_A24: 1064 /* 1 MB of DVMA space */ 1065 map->_dm_ex_start = VME_IOMMU_DVMA_AM24_BASE; 1066 map->_dm_ex_end = VME_IOMMU_DVMA_AM24_END; 1067 break; 1068 case VME_AM_A32: 1069 /* 8 MB of DVMA space */ 1070 map->_dm_ex_start = VME_IOMMU_DVMA_AM32_BASE; 1071 map->_dm_ex_end = VME_IOMMU_DVMA_AM32_END; 1072 break; 1073 } 1074 1075 *dmamp = map; 1076 return (0); 1077 } 1078 1079 int 1080 sparc_vme_iommu_dmamap_load(t, map, buf, buflen, p, flags) 1081 bus_dma_tag_t t; 1082 bus_dmamap_t map; 1083 void *buf; 1084 bus_size_t buflen; 1085 struct proc *p; 1086 int flags; 1087 { 1088 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1089 volatile u_int32_t *ioctags; 1090 int error; 1091 1092 /* Round request to a multiple of the I/O cache size */ 1093 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 1094 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1095 if (error != 0) 1096 return (error); 1097 1098 /* Allocate I/O cache entries for this range */ 1099 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1100 while (buflen > 0) { 1101 *ioctags = VME_IOC_IC | VME_IOC_W; 1102 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1103 buflen -= VME_IOC_PAGESZ; 1104 } 1105 1106 /* 1107 * Adjust DVMA address to VME view. 1108 * Note: the DVMA base address is the same for all 1109 * VME address spaces. 1110 */ 1111 map->dm_segs[0].ds_addr -= VME_IOMMU_DVMA_BASE; 1112 return (0); 1113 } 1114 1115 1116 void 1117 sparc_vme_iommu_dmamap_unload(t, map) 1118 bus_dma_tag_t t; 1119 bus_dmamap_t map; 1120 { 1121 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1122 volatile u_int32_t *flushregs; 1123 int len; 1124 1125 /* Go from VME to CPU view */ 1126 map->dm_segs[0].ds_addr += VME_IOMMU_DVMA_BASE; 1127 1128 /* Flush VME I/O cache */ 1129 len = map->dm_segs[0]._ds_sgsize; 1130 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1131 while (len > 0) { 1132 *flushregs = 0; 1133 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1134 len -= VME_IOC_PAGESZ; 1135 } 1136 1137 /* 1138 * Start a read from `tag space' which will not complete until 1139 * all cache flushes have finished 1140 */ 1141 (*sc->sc_ioctags); 1142 1143 bus_dmamap_unload(sc->sc_dmatag, map); 1144 } 1145 1146 void 1147 sparc_vme_iommu_dmamap_sync(t, map, offset, len, ops) 1148 bus_dma_tag_t t; 1149 bus_dmamap_t map; 1150 bus_addr_t offset; 1151 bus_size_t len; 1152 int ops; 1153 { 1154 1155 /* 1156 * XXX Should perform cache flushes as necessary. 1157 */ 1158 } 1159 #endif /* SUN4M */ 1160 1161 int 1162 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1163 bus_dma_tag_t t; 1164 bus_dma_segment_t *segs; 1165 int nsegs; 1166 size_t size; 1167 caddr_t *kvap; 1168 int flags; 1169 { 1170 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1171 1172 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1173 } 1174
Indexes created Tue Sep 23 14:10:03 GMT 2025