vme_machdep.c revision 1.43
1 /* $NetBSD: vme_machdep.c,v 1.43 2002/12/28 01:33:00 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/systm.h> 42 #include <sys/device.h> 43 #include <sys/malloc.h> 44 #include <sys/errno.h> 45 46 #include <sys/proc.h> 47 #include <sys/user.h> 48 #include <sys/syslog.h> 49 50 #include <uvm/uvm_extern.h> 51 52 #define _SPARC_BUS_DMA_PRIVATE 53 #include <machine/bus.h> 54 #include <sparc/sparc/iommuvar.h> 55 #include <machine/autoconf.h> 56 #include <machine/oldmon.h> 57 #include <machine/cpu.h> 58 #include <machine/ctlreg.h> 59 60 #include <dev/vme/vmereg.h> 61 #include <dev/vme/vmevar.h> 62 63 #include <sparc/sparc/asm.h> 64 #include <sparc/sparc/vaddrs.h> 65 #include <sparc/sparc/cpuvar.h> 66 #include <sparc/dev/vmereg.h> 67 68 struct sparcvme_softc { 69 struct device sc_dev; /* base device */ 70 bus_space_tag_t sc_bustag; 71 bus_dma_tag_t sc_dmatag; 72 struct vmebusreg *sc_reg; /* VME control registers */ 73 struct vmebusvec *sc_vec; /* VME interrupt vector */ 74 struct rom_range *sc_range; /* ROM range property */ 75 int sc_nrange; 76 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 77 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 78 int (*sc_vmeintr) __P((void *)); 79 }; 80 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 81 82 /* autoconfiguration driver */ 83 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 84 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 85 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 86 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 87 #if defined(SUN4) 88 int vmeintr4 __P((void *)); 89 #endif 90 #if defined(SUN4M) 91 int vmeintr4m __P((void *)); 92 static int sparc_vme_error __P((void)); 93 #endif 94 95 96 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 97 vme_am_t, vme_datasize_t, 98 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 99 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 100 vme_datasize_t, vme_swap_t, 101 bus_space_tag_t *, bus_space_handle_t *, 102 vme_mapresc_t *)); 103 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 104 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 105 static const struct evcnt *sparc_vme_intr_evcnt __P((void *, 106 vme_intr_handle_t)); 107 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 108 int (*) __P((void *)), void *)); 109 static void sparc_vme_intr_disestablish __P((void *, void *)); 110 111 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 112 vme_addr_t, bus_addr_t *)); 113 #if defined(SUN4M) 114 static void sparc_vme_iommu_barrier __P(( bus_space_tag_t, bus_space_handle_t, 115 bus_size_t, bus_size_t, int)); 116 117 #endif 118 119 /* 120 * DMA functions. 121 */ 122 static void sparc_vct_dmamap_destroy __P((void *, bus_dmamap_t)); 123 124 #if defined(SUN4) 125 static int sparc_vct4_dmamap_create __P((void *, vme_size_t, vme_am_t, 126 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 127 int, bus_dmamap_t *)); 128 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 129 bus_size_t, struct proc *, int)); 130 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 131 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 132 bus_addr_t, bus_size_t, int)); 133 #endif 134 135 #if defined(SUN4M) 136 static int sparc_vct_iommu_dmamap_create __P((void *, vme_size_t, vme_am_t, 137 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 138 int, bus_dmamap_t *)); 139 static int sparc_vme_iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, 140 int, bus_size_t, bus_size_t, int, bus_dmamap_t *)); 141 142 static int sparc_vme_iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, 143 void *, bus_size_t, struct proc *, int)); 144 static void sparc_vme_iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 145 static void sparc_vme_iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 146 bus_addr_t, bus_size_t, int)); 147 #endif 148 149 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 150 int, size_t, caddr_t *, int)); 151 #if 0 152 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 153 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 154 static paddr_t sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 155 bus_dma_segment_t *, int, off_t, int, int)); 156 #endif 157 158 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 159 160 CFATTACH_DECL(vme_mainbus, sizeof(struct sparcvme_softc), 161 vmematch_mainbus, vmeattach_mainbus, NULL, NULL); 162 163 CFATTACH_DECL(vme_iommu, sizeof(struct sparcvme_softc), 164 vmematch_iommu, vmeattach_iommu, NULL, NULL); 165 166 int (*vmeerr_handler) __P((void)); 167 168 #define VMEMOD_D32 0x40 /* ??? */ 169 170 /* If the PROM does not provide the `ranges' property, we make up our own */ 171 struct rom_range vmebus_translations[] = { 172 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 173 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 174 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 175 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 176 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 177 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 178 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 179 #undef _DS 180 }; 181 182 /* 183 * The VME bus logic on sun4 machines maps DMA requests in the first MB 184 * of VME space to the last MB of DVMA space. `vme_dvmamap' is used 185 * for DVMA space allocations. The DMA addresses returned by 186 * bus_dmamap_load*() must be relocated by -VME4_DVMA_BASE. 187 */ 188 struct extent *vme_dvmamap; 189 190 /* 191 * The VME hardware on the sun4m IOMMU maps the first 8MB of 32-bit 192 * VME space to the last 8MB of DVMA space and the first 1MB of 193 * 24-bit VME space to the first 1MB of the last 8MB of DVMA space 194 * (thus 24-bit VME space overlaps the first 1MB of of 32-bit space). 195 * The following constants define subregions in the IOMMU DVMA map 196 * for VME DVMA allocations. The DMA addresses returned by 197 * bus_dmamap_load*() must be relocated by -VME_IOMMU_DVMA_BASE. 198 */ 199 #define VME_IOMMU_DVMA_BASE 0xff800000 200 #define VME_IOMMU_DVMA_AM24_BASE VME_IOMMU_DVMA_BASE 201 #define VME_IOMMU_DVMA_AM24_END 0xff900000 202 #define VME_IOMMU_DVMA_AM32_BASE VME_IOMMU_DVMA_BASE 203 #define VME_IOMMU_DVMA_AM32_END IOMMU_DVMA_END 204 205 struct sparc_bus_space_tag sparc_vme_bus_tag = { 206 NULL, /* cookie */ 207 NULL, /* parent bus tag */ 208 NULL, /* ranges */ 209 0, /* nranges */ 210 NULL, /* bus_map */ 211 NULL, /* bus_unmap */ 212 NULL, /* bus_subregion */ 213 NULL, /* barrier */ 214 NULL, /* mmap */ 215 NULL /* intr_establish */ 216 }; 217 218 struct vme_chipset_tag sparc_vme_chipset_tag = { 219 NULL, 220 sparc_vme_map, 221 sparc_vme_unmap, 222 sparc_vme_probe, 223 sparc_vme_intr_map, 224 sparc_vme_intr_evcnt, 225 sparc_vme_intr_establish, 226 sparc_vme_intr_disestablish, 227 0, 0, 0 /* bus specific DMA stuff */ 228 }; 229 230 231 #if defined(SUN4) 232 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 233 NULL, /* cookie */ 234 _bus_dmamap_create, 235 _bus_dmamap_destroy, 236 sparc_vme4_dmamap_load, 237 _bus_dmamap_load_mbuf, 238 _bus_dmamap_load_uio, 239 _bus_dmamap_load_raw, 240 sparc_vme4_dmamap_unload, 241 sparc_vme4_dmamap_sync, 242 243 _bus_dmamem_alloc, 244 _bus_dmamem_free, 245 sparc_vme_dmamem_map, 246 _bus_dmamem_unmap, 247 _bus_dmamem_mmap 248 }; 249 #endif 250 251 #if defined(SUN4M) 252 struct sparc_bus_dma_tag sparc_vme_iommu_dma_tag = { 253 NULL, /* cookie */ 254 sparc_vme_iommu_dmamap_create, 255 _bus_dmamap_destroy, 256 sparc_vme_iommu_dmamap_load, 257 _bus_dmamap_load_mbuf, 258 _bus_dmamap_load_uio, 259 _bus_dmamap_load_raw, 260 sparc_vme_iommu_dmamap_unload, 261 sparc_vme_iommu_dmamap_sync, 262 263 _bus_dmamem_alloc, 264 _bus_dmamem_free, 265 sparc_vme_dmamem_map, 266 _bus_dmamem_unmap, 267 _bus_dmamem_mmap 268 }; 269 #endif 270 271 272 int 273 vmematch_mainbus(parent, cf, aux) 274 struct device *parent; 275 struct cfdata *cf; 276 void *aux; 277 { 278 struct mainbus_attach_args *ma = aux; 279 280 if (!CPU_ISSUN4) 281 return (0); 282 283 return (strcmp("vme", ma->ma_name) == 0); 284 } 285 286 int 287 vmematch_iommu(parent, cf, aux) 288 struct device *parent; 289 struct cfdata *cf; 290 void *aux; 291 { 292 struct iommu_attach_args *ia = aux; 293 294 return (strcmp("vme", ia->iom_name) == 0); 295 } 296 297 298 void 299 vmeattach_mainbus(parent, self, aux) 300 struct device *parent, *self; 301 void *aux; 302 { 303 #if defined(SUN4) 304 struct mainbus_attach_args *ma = aux; 305 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 306 struct vmebus_attach_args vba; 307 308 if (self->dv_unit > 0) { 309 printf(" unsupported\n"); 310 return; 311 } 312 313 sc->sc_bustag = ma->ma_bustag; 314 sc->sc_dmatag = ma->ma_dmatag; 315 316 /* VME interrupt entry point */ 317 sc->sc_vmeintr = vmeintr4; 318 319 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 320 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 321 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 322 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 323 324 #if 0 325 sparc_vme_bus_tag.parent = ma->ma_bustag; 326 vba.vba_bustag = &sparc_vme_bus_tag; 327 #endif 328 vba.va_vct = &sparc_vme_chipset_tag; 329 vba.va_bdt = &sparc_vme4_dma_tag; 330 vba.va_slaveconfig = 0; 331 332 /* Fall back to our own `range' construction */ 333 sc->sc_range = vmebus_translations; 334 sc->sc_nrange = 335 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 336 337 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 338 M_DEVBUF, 0, 0, EX_NOWAIT); 339 if (vme_dvmamap == NULL) 340 panic("vme: unable to allocate DVMA map"); 341 342 printf("\n"); 343 (void)config_found(self, &vba, 0); 344 345 #endif 346 return; 347 } 348 349 /* sun4m vmebus */ 350 void 351 vmeattach_iommu(parent, self, aux) 352 struct device *parent, *self; 353 void *aux; 354 { 355 #if defined(SUN4M) 356 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 357 struct iommu_attach_args *ia = aux; 358 struct vmebus_attach_args vba; 359 bus_space_handle_t bh; 360 int node; 361 int cline; 362 363 if (self->dv_unit > 0) { 364 printf(" unsupported\n"); 365 return; 366 } 367 368 sc->sc_bustag = ia->iom_bustag; 369 sc->sc_dmatag = ia->iom_dmatag; 370 371 /* VME interrupt entry point */ 372 sc->sc_vmeintr = vmeintr4m; 373 374 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 375 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct_iommu_dmamap_create; 376 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 377 /*XXX*/ sparc_vme_iommu_dma_tag._cookie = self; 378 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme_iommu_barrier; 379 380 #if 0 381 vba.vba_bustag = &sparc_vme_bus_tag; 382 #endif 383 vba.va_vct = &sparc_vme_chipset_tag; 384 vba.va_bdt = &sparc_vme_iommu_dma_tag; 385 vba.va_slaveconfig = 0; 386 387 node = ia->iom_node; 388 389 /* 390 * Map VME control space 391 */ 392 if (ia->iom_nreg < 2) { 393 printf("%s: only %d register sets\n", self->dv_xname, 394 ia->iom_nreg); 395 return; 396 } 397 398 if (bus_space_map(ia->iom_bustag, 399 (bus_addr_t) BUS_ADDR(ia->iom_reg[0].oa_space, 400 ia->iom_reg[0].oa_base), 401 (bus_size_t)ia->iom_reg[0].oa_size, 402 BUS_SPACE_MAP_LINEAR, 403 &bh) != 0) { 404 panic("%s: can't map vmebusreg", self->dv_xname); 405 } 406 sc->sc_reg = (struct vmebusreg *)bh; 407 408 if (bus_space_map(ia->iom_bustag, 409 (bus_addr_t) BUS_ADDR(ia->iom_reg[1].oa_space, 410 ia->iom_reg[1].oa_base), 411 (bus_size_t)ia->iom_reg[1].oa_size, 412 BUS_SPACE_MAP_LINEAR, 413 &bh) != 0) { 414 panic("%s: can't map vmebusvec", self->dv_xname); 415 } 416 sc->sc_vec = (struct vmebusvec *)bh; 417 418 /* 419 * Map VME IO cache tags and flush control. 420 */ 421 if (bus_space_map(ia->iom_bustag, 422 (bus_addr_t) BUS_ADDR( 423 ia->iom_reg[1].oa_space, 424 ia->iom_reg[1].oa_base + VME_IOC_TAGOFFSET), 425 VME_IOC_SIZE, 426 BUS_SPACE_MAP_LINEAR, 427 &bh) != 0) { 428 panic("%s: can't map IOC tags", self->dv_xname); 429 } 430 sc->sc_ioctags = (u_int32_t *)bh; 431 432 if (bus_space_map(ia->iom_bustag, 433 (bus_addr_t) BUS_ADDR( 434 ia->iom_reg[1].oa_space, 435 ia->iom_reg[1].oa_base + VME_IOC_FLUSHOFFSET), 436 VME_IOC_SIZE, 437 BUS_SPACE_MAP_LINEAR, 438 &bh) != 0) { 439 panic("%s: can't map IOC flush registers", self->dv_xname); 440 } 441 sc->sc_iocflush = (u_int32_t *)bh; 442 443 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 444 445 /* 446 * Get "range" property. 447 */ 448 if (PROM_getprop(node, "ranges", sizeof(struct rom_range), 449 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 450 panic("%s: can't get ranges property", self->dv_xname); 451 } 452 453 sparcvme_sc = sc; 454 vmeerr_handler = sparc_vme_error; 455 456 /* 457 * Invalidate all IO-cache entries. 458 */ 459 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 460 sc->sc_ioctags[--cline] = 0; 461 } 462 463 /* Enable IO-cache */ 464 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 465 466 printf(": version 0x%x\n", 467 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 468 469 (void)config_found(self, &vba, 0); 470 #endif 471 } 472 473 #if defined(SUN4M) 474 static int 475 sparc_vme_error() 476 { 477 struct sparcvme_softc *sc = sparcvme_sc; 478 u_int32_t afsr, afpa; 479 char bits[64]; 480 481 afsr = sc->sc_reg->vmebus_afsr; 482 afpa = sc->sc_reg->vmebus_afar; 483 printf("VME error:\n\tAFSR %s\n", 484 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 485 printf("\taddress: 0x%x%x\n", afsr, afpa); 486 return (0); 487 } 488 #endif 489 490 int 491 vmebus_translate(sc, mod, addr, bap) 492 struct sparcvme_softc *sc; 493 vme_am_t mod; 494 vme_addr_t addr; 495 bus_addr_t *bap; 496 { 497 int i; 498 499 for (i = 0; i < sc->sc_nrange; i++) { 500 struct rom_range *rp = &sc->sc_range[i]; 501 502 if (rp->cspace != mod) 503 continue; 504 505 /* We've found the connection to the parent bus */ 506 *bap = BUS_ADDR(rp->pspace, rp->poffset + addr); 507 return (0); 508 } 509 return (ENOENT); 510 } 511 512 struct vmeprobe_myarg { 513 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 514 void *cbarg; 515 bus_space_tag_t tag; 516 int res; /* backwards */ 517 }; 518 519 static int vmeprobe_mycb __P((void *, void *)); 520 static int 521 vmeprobe_mycb(bh, arg) 522 void *bh, *arg; 523 { 524 struct vmeprobe_myarg *a = arg; 525 526 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 527 return (!a->res); 528 } 529 530 int 531 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 532 void *cookie; 533 vme_addr_t addr; 534 vme_size_t len; 535 vme_am_t mod; 536 vme_datasize_t datasize; 537 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 538 void *arg; 539 { 540 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 541 bus_addr_t paddr; 542 bus_size_t size; 543 struct vmeprobe_myarg myarg; 544 int res, i; 545 546 if (vmebus_translate(sc, mod, addr, &paddr) != 0) 547 return (EINVAL); 548 549 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 550 551 if (callback) { 552 myarg.cb = callback; 553 myarg.cbarg = arg; 554 myarg.tag = sc->sc_bustag; 555 myarg.res = 0; 556 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 557 0, vmeprobe_mycb, &myarg); 558 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 559 } 560 561 for (i = 0; i < len / size; i++) { 562 myarg.res = 0; 563 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 564 0, 0, 0); 565 if (res == 0) 566 return (EIO); 567 paddr += size; 568 } 569 return (0); 570 } 571 572 int 573 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 574 void *cookie; 575 vme_addr_t addr; 576 vme_size_t size; 577 vme_am_t mod; 578 vme_datasize_t datasize; 579 vme_swap_t swap; 580 bus_space_tag_t *tp; 581 bus_space_handle_t *hp; 582 vme_mapresc_t *rp; 583 { 584 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 585 bus_addr_t paddr; 586 int error; 587 588 error = vmebus_translate(sc, mod, addr, &paddr); 589 if (error != 0) 590 return (error); 591 592 *tp = sc->sc_bustag; 593 return (bus_space_map(sc->sc_bustag, paddr, size, 0, hp)); 594 } 595 596 int 597 sparc_vme_mmap_cookie(addr, mod, hp) 598 vme_addr_t addr; 599 vme_am_t mod; 600 bus_space_handle_t *hp; 601 { 602 struct sparcvme_softc *sc = sparcvme_sc; 603 bus_addr_t paddr; 604 int error; 605 606 error = vmebus_translate(sc, mod, addr, &paddr); 607 if (error != 0) 608 return (error); 609 610 return (bus_space_mmap(sc->sc_bustag, paddr, 0, 611 0/*prot is ignored*/, 0)); 612 } 613 614 #if defined(SUN4M) 615 void 616 sparc_vme_iommu_barrier(t, h, offset, size, flags) 617 bus_space_tag_t t; 618 bus_space_handle_t h; 619 bus_size_t offset; 620 bus_size_t size; 621 int flags; 622 { 623 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 624 625 /* Read async fault status to flush write-buffers */ 626 (*(volatile int *)&vbp->vmebus_afsr); 627 } 628 #endif 629 630 631 632 /* 633 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 634 */ 635 static int vme_ipl_to_pil[] = { 636 0, 637 2, 638 3, 639 5, 640 7, 641 9, 642 11, 643 13 644 }; 645 646 647 /* 648 * All VME device interrupts go through vmeintr(). This function reads 649 * the VME vector from the bus, then dispatches the device interrupt 650 * handler. All handlers for devices that map to the same Processor 651 * Interrupt Level (according to the table above) are on a linked list 652 * of `sparc_vme_intr_handle' structures. The head of which is passed 653 * down as the argument to `vmeintr(void *arg)'. 654 */ 655 struct sparc_vme_intr_handle { 656 struct intrhand ih; 657 struct sparc_vme_intr_handle *next; 658 int vec; /* VME interrupt vector */ 659 int pri; /* VME interrupt priority */ 660 struct sparcvme_softc *sc;/*XXX*/ 661 }; 662 663 #if defined(SUN4) 664 int 665 vmeintr4(arg) 666 void *arg; 667 { 668 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 669 int level, vec; 670 int rv = 0; 671 672 level = (ihp->pri << 1) | 1; 673 674 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 675 676 if (vec == -1) { 677 #ifdef DEBUG 678 /* 679 * This seems to happen only with the i82586 based 680 * `ie1' boards. 681 */ 682 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 683 #endif 684 return (1); /* XXX - pretend we handled it, for now */ 685 } 686 687 for (; ihp; ihp = ihp->next) 688 if (ihp->vec == vec && ihp->ih.ih_fun) { 689 splx(ihp->ih.ih_classipl); 690 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 691 } 692 693 return (rv); 694 } 695 #endif 696 697 #if defined(SUN4M) 698 int 699 vmeintr4m(arg) 700 void *arg; 701 { 702 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 703 int level, vec; 704 int rv = 0; 705 706 level = (ihp->pri << 1) | 1; 707 708 #if 0 709 int pending; 710 711 /* Flush VME <=> Sbus write buffers */ 712 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 713 714 pending = *((int*)ICR_SI_PEND); 715 if ((pending & SINTR_VME(ihp->pri)) == 0) { 716 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 717 ihp->pri, pending); 718 return (0); 719 } 720 #endif 721 #if 0 722 /* Why gives this a bus timeout sometimes? */ 723 vec = ihp->sc->sc_vec->vmebusvec[level]; 724 #else 725 /* so, arrange to catch the fault... */ 726 { 727 extern struct user *proc0paddr; 728 extern int fkbyte __P((caddr_t, struct pcb *)); 729 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 730 struct pcb *xpcb; 731 u_long saveonfault; 732 int s; 733 734 s = splhigh(); 735 if (curproc == NULL) 736 xpcb = (struct pcb *)proc0paddr; 737 else 738 xpcb = &curproc->p_addr->u_pcb; 739 740 saveonfault = (u_long)xpcb->pcb_onfault; 741 vec = fkbyte(addr, xpcb); 742 xpcb->pcb_onfault = (caddr_t)saveonfault; 743 744 splx(s); 745 } 746 #endif 747 748 if (vec == -1) { 749 #ifdef DEBUG 750 /* 751 * This seems to happen only with the i82586 based 752 * `ie1' boards. 753 */ 754 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 755 printf(" ICR_SI_PEND=0x%x; VME AFSR=0x%x; VME AFAR=0x%x\n", 756 *((int*)ICR_SI_PEND), 757 ihp->sc->sc_reg->vmebus_afsr, 758 ihp->sc->sc_reg->vmebus_afar); 759 #endif 760 return (1); /* XXX - pretend we handled it, for now */ 761 } 762 763 for (; ihp; ihp = ihp->next) 764 if (ihp->vec == vec && ihp->ih.ih_fun) { 765 splx(ihp->ih.ih_classipl); 766 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 767 } 768 769 return (rv); 770 } 771 #endif 772 773 int 774 sparc_vme_intr_map(cookie, level, vec, ihp) 775 void *cookie; 776 int level; 777 int vec; 778 vme_intr_handle_t *ihp; 779 { 780 struct sparc_vme_intr_handle *ih; 781 782 ih = (vme_intr_handle_t) 783 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 784 ih->pri = level; 785 ih->vec = vec; 786 ih->sc = cookie;/*XXX*/ 787 *ihp = ih; 788 return (0); 789 } 790 791 const struct evcnt * 792 sparc_vme_intr_evcnt(cookie, vih) 793 void *cookie; 794 vme_intr_handle_t vih; 795 { 796 797 /* XXX for now, no evcnt parent reported */ 798 return NULL; 799 } 800 801 void * 802 sparc_vme_intr_establish(cookie, vih, level, func, arg) 803 void *cookie; 804 vme_intr_handle_t vih; 805 int level; 806 int (*func) __P((void *)); 807 void *arg; 808 { 809 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 810 struct sparc_vme_intr_handle *svih = 811 (struct sparc_vme_intr_handle *)vih; 812 struct intrhand *ih; 813 int pil; 814 815 /* Translate VME priority to processor IPL */ 816 pil = vme_ipl_to_pil[svih->pri]; 817 818 if (level < pil) 819 panic("vme_intr_establish: class lvl (%d) < pil (%d)\n", 820 level, pil); 821 822 svih->ih.ih_fun = func; 823 svih->ih.ih_arg = arg; 824 svih->ih.ih_classipl = level; /* note: used slightly differently 825 than in intr.c (no shift) */ 826 svih->next = NULL; 827 828 /* ensure the interrupt subsystem will call us at this level */ 829 for (ih = intrhand[pil]; ih != NULL; ih = ih->ih_next) 830 if (ih->ih_fun == sc->sc_vmeintr) 831 break; 832 833 if (ih == NULL) { 834 ih = (struct intrhand *) 835 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 836 if (ih == NULL) 837 panic("vme_addirq"); 838 bzero(ih, sizeof *ih); 839 ih->ih_fun = sc->sc_vmeintr; 840 ih->ih_arg = vih; 841 intr_establish(pil, 0, ih, NULL); 842 } else { 843 svih->next = (vme_intr_handle_t)ih->ih_arg; 844 ih->ih_arg = vih; 845 } 846 return (NULL); 847 } 848 849 void 850 sparc_vme_unmap(cookie, resc) 851 void * cookie; 852 vme_mapresc_t resc; 853 { 854 /* Not implemented */ 855 panic("sparc_vme_unmap"); 856 } 857 858 void 859 sparc_vme_intr_disestablish(cookie, a) 860 void *cookie; 861 void *a; 862 { 863 /* Not implemented */ 864 panic("sparc_vme_intr_disestablish"); 865 } 866 867 868 869 /* 870 * VME DMA functions. 871 */ 872 873 static void 874 sparc_vct_dmamap_destroy(cookie, map) 875 void *cookie; 876 bus_dmamap_t map; 877 { 878 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 879 bus_dmamap_destroy(sc->sc_dmatag, map); 880 } 881 882 #if defined(SUN4) 883 static int 884 sparc_vct4_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 885 boundary, flags, dmamp) 886 void *cookie; 887 vme_size_t size; 888 vme_am_t am; 889 vme_datasize_t datasize; 890 vme_swap_t swap; 891 int nsegments; 892 vme_size_t maxsegsz; 893 vme_addr_t boundary; 894 int flags; 895 bus_dmamap_t *dmamp; 896 { 897 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 898 899 /* Allocate a base map through parent bus ops */ 900 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 901 boundary, flags, dmamp)); 902 } 903 904 int 905 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 906 bus_dma_tag_t t; 907 bus_dmamap_t map; 908 void *buf; 909 bus_size_t buflen; 910 struct proc *p; 911 int flags; 912 { 913 bus_addr_t dva; 914 bus_size_t sgsize; 915 vaddr_t va, voff; 916 pmap_t pmap; 917 int pagesz = PAGE_SIZE; 918 int error; 919 920 cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 921 922 va = (vaddr_t)buf; 923 voff = va & (pagesz - 1); 924 va &= -pagesz; 925 926 /* 927 * Allocate an integral number of pages from DVMA space 928 * covering the passed buffer. 929 */ 930 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 931 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 932 map->_dm_boundary, 933 (flags & BUS_DMA_NOWAIT) == 0 934 ? EX_WAITOK 935 : EX_NOWAIT, 936 (u_long *)&dva); 937 if (error != 0) 938 return (error); 939 940 map->dm_mapsize = buflen; 941 map->dm_nsegs = 1; 942 /* Adjust DVMA address to VME view */ 943 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 944 map->dm_segs[0].ds_len = buflen; 945 map->dm_segs[0]._ds_sgsize = sgsize; 946 947 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 948 949 for (; sgsize != 0; ) { 950 paddr_t pa; 951 /* 952 * Get the physical address for this page. 953 */ 954 (void) pmap_extract(pmap, va, &pa); 955 956 #ifdef notyet 957 if (have_iocache) 958 pa |= PG_IOC; 959 #endif 960 pmap_enter(pmap_kernel(), dva, 961 pa | PMAP_NC, 962 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 963 964 dva += pagesz; 965 va += pagesz; 966 sgsize -= pagesz; 967 } 968 pmap_update(pmap_kernel()); 969 970 return (0); 971 } 972 973 void 974 sparc_vme4_dmamap_unload(t, map) 975 bus_dma_tag_t t; 976 bus_dmamap_t map; 977 { 978 bus_dma_segment_t *segs = map->dm_segs; 979 int nsegs = map->dm_nsegs; 980 bus_addr_t dva; 981 bus_size_t len; 982 int i, s, error; 983 984 for (i = 0; i < nsegs; i++) { 985 /* Go from VME to CPU view */ 986 dva = segs[i].ds_addr + VME4_DVMA_BASE; 987 dva &= -PAGE_SIZE; 988 len = segs[i]._ds_sgsize; 989 990 /* Remove double-mapping in DVMA space */ 991 pmap_remove(pmap_kernel(), dva, dva + len); 992 993 /* Release DVMA space */ 994 s = splhigh(); 995 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 996 splx(s); 997 if (error != 0) 998 printf("warning: %ld of DVMA space lost\n", len); 999 } 1000 pmap_update(pmap_kernel()); 1001 1002 /* Mark the mappings as invalid. */ 1003 map->dm_mapsize = 0; 1004 map->dm_nsegs = 0; 1005 } 1006 1007 void 1008 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 1009 bus_dma_tag_t t; 1010 bus_dmamap_t map; 1011 bus_addr_t offset; 1012 bus_size_t len; 1013 int ops; 1014 { 1015 1016 /* 1017 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 1018 * Currently the cache is flushed in bus_dma_load()... 1019 */ 1020 } 1021 #endif /* SUN4 */ 1022 1023 #if defined(SUN4M) 1024 static int 1025 sparc_vme_iommu_dmamap_create (t, size, nsegments, maxsegsz, 1026 boundary, flags, dmamp) 1027 bus_dma_tag_t t; 1028 bus_size_t size; 1029 int nsegments; 1030 bus_size_t maxsegsz; 1031 bus_size_t boundary; 1032 int flags; 1033 bus_dmamap_t *dmamp; 1034 { 1035 1036 printf("sparc_vme_dmamap_create: please use `vme_dmamap_create'\n"); 1037 return (EINVAL); 1038 } 1039 1040 static int 1041 sparc_vct_iommu_dmamap_create(cookie, size, am, datasize, swap, nsegments, 1042 maxsegsz, boundary, flags, dmamp) 1043 void *cookie; 1044 vme_size_t size; 1045 vme_am_t am; 1046 vme_datasize_t datasize; 1047 vme_swap_t swap; 1048 int nsegments; 1049 vme_size_t maxsegsz; 1050 vme_addr_t boundary; 1051 int flags; 1052 bus_dmamap_t *dmamp; 1053 { 1054 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 1055 bus_dmamap_t map; 1056 int error; 1057 1058 /* Allocate a base map through parent bus ops */ 1059 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1060 boundary, flags, &map); 1061 if (error != 0) 1062 return (error); 1063 1064 /* 1065 * Each I/O cache line maps to a 8K section of VME DVMA space, so 1066 * we must ensure that DVMA alloctions are always 8K aligned. 1067 */ 1068 map->_dm_align = VME_IOC_PAGESZ; 1069 1070 /* Set map region based on Address Modifier */ 1071 switch ((am & VME_AM_ADRSIZEMASK)) { 1072 case VME_AM_A16: 1073 case VME_AM_A24: 1074 /* 1 MB of DVMA space */ 1075 map->_dm_ex_start = VME_IOMMU_DVMA_AM24_BASE; 1076 map->_dm_ex_end = VME_IOMMU_DVMA_AM24_END; 1077 break; 1078 case VME_AM_A32: 1079 /* 8 MB of DVMA space */ 1080 map->_dm_ex_start = VME_IOMMU_DVMA_AM32_BASE; 1081 map->_dm_ex_end = VME_IOMMU_DVMA_AM32_END; 1082 break; 1083 } 1084 1085 *dmamp = map; 1086 return (0); 1087 } 1088 1089 int 1090 sparc_vme_iommu_dmamap_load(t, map, buf, buflen, p, flags) 1091 bus_dma_tag_t t; 1092 bus_dmamap_t map; 1093 void *buf; 1094 bus_size_t buflen; 1095 struct proc *p; 1096 int flags; 1097 { 1098 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1099 volatile u_int32_t *ioctags; 1100 int error; 1101 1102 /* Round request to a multiple of the I/O cache size */ 1103 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 1104 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1105 if (error != 0) 1106 return (error); 1107 1108 /* Allocate I/O cache entries for this range */ 1109 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1110 while (buflen > 0) { 1111 *ioctags = VME_IOC_IC | VME_IOC_W; 1112 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1113 buflen -= VME_IOC_PAGESZ; 1114 } 1115 1116 /* 1117 * Adjust DVMA address to VME view. 1118 * Note: the DVMA base address is the same for all 1119 * VME address spaces. 1120 */ 1121 map->dm_segs[0].ds_addr -= VME_IOMMU_DVMA_BASE; 1122 return (0); 1123 } 1124 1125 1126 void 1127 sparc_vme_iommu_dmamap_unload(t, map) 1128 bus_dma_tag_t t; 1129 bus_dmamap_t map; 1130 { 1131 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1132 volatile u_int32_t *flushregs; 1133 int len; 1134 1135 /* Go from VME to CPU view */ 1136 map->dm_segs[0].ds_addr += VME_IOMMU_DVMA_BASE; 1137 1138 /* Flush VME I/O cache */ 1139 len = map->dm_segs[0]._ds_sgsize; 1140 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1141 while (len > 0) { 1142 *flushregs = 0; 1143 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1144 len -= VME_IOC_PAGESZ; 1145 } 1146 1147 /* 1148 * Start a read from `tag space' which will not complete until 1149 * all cache flushes have finished 1150 */ 1151 (*sc->sc_ioctags); 1152 1153 bus_dmamap_unload(sc->sc_dmatag, map); 1154 } 1155 1156 void 1157 sparc_vme_iommu_dmamap_sync(t, map, offset, len, ops) 1158 bus_dma_tag_t t; 1159 bus_dmamap_t map; 1160 bus_addr_t offset; 1161 bus_size_t len; 1162 int ops; 1163 { 1164 1165 /* 1166 * XXX Should perform cache flushes as necessary. 1167 */ 1168 } 1169 #endif /* SUN4M */ 1170 1171 int 1172 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1173 bus_dma_tag_t t; 1174 bus_dma_segment_t *segs; 1175 int nsegs; 1176 size_t size; 1177 caddr_t *kvap; 1178 int flags; 1179 { 1180 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1181 1182 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1183 } 1184
Indexes created Wed Sep 24 22:09:59 GMT 2025