vme_machdep.c revision 1.46
1 /* $NetBSD: vme_machdep.c,v 1.46 2003/07/15 00:04:57 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: vme_machdep.c,v 1.46 2003/07/15 00:04:57 lukem Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/extent.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/errno.h> 48 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/syslog.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #define _SPARC_BUS_DMA_PRIVATE 56 #include <machine/bus.h> 57 #include <sparc/sparc/iommuvar.h> 58 #include <machine/autoconf.h> 59 #include <machine/oldmon.h> 60 #include <machine/cpu.h> 61 #include <machine/ctlreg.h> 62 63 #include <dev/vme/vmereg.h> 64 #include <dev/vme/vmevar.h> 65 66 #include <sparc/sparc/asm.h> 67 #include <sparc/sparc/vaddrs.h> 68 #include <sparc/sparc/cpuvar.h> 69 #include <sparc/dev/vmereg.h> 70 71 struct sparcvme_softc { 72 struct device sc_dev; /* base device */ 73 bus_space_tag_t sc_bustag; 74 bus_dma_tag_t sc_dmatag; 75 struct vmebusreg *sc_reg; /* VME control registers */ 76 struct vmebusvec *sc_vec; /* VME interrupt vector */ 77 struct rom_range *sc_range; /* ROM range property */ 78 int sc_nrange; 79 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 80 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 81 int (*sc_vmeintr) __P((void *)); 82 }; 83 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 84 85 /* autoconfiguration driver */ 86 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 87 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 88 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 89 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 90 #if defined(SUN4) 91 int vmeintr4 __P((void *)); 92 #endif 93 #if defined(SUN4M) 94 int vmeintr4m __P((void *)); 95 static int sparc_vme_error __P((void)); 96 #endif 97 98 99 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 100 vme_am_t, vme_datasize_t, 101 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 102 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 103 vme_datasize_t, vme_swap_t, 104 bus_space_tag_t *, bus_space_handle_t *, 105 vme_mapresc_t *)); 106 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 107 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 108 static const struct evcnt *sparc_vme_intr_evcnt __P((void *, 109 vme_intr_handle_t)); 110 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 111 int (*) __P((void *)), void *)); 112 static void sparc_vme_intr_disestablish __P((void *, void *)); 113 114 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 115 vme_addr_t, bus_addr_t *)); 116 #if defined(SUN4M) 117 static void sparc_vme_iommu_barrier __P(( bus_space_tag_t, bus_space_handle_t, 118 bus_size_t, bus_size_t, int)); 119 120 #endif 121 122 /* 123 * DMA functions. 124 */ 125 static void sparc_vct_dmamap_destroy __P((void *, bus_dmamap_t)); 126 127 #if defined(SUN4) 128 static int sparc_vct4_dmamap_create __P((void *, vme_size_t, vme_am_t, 129 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 130 int, bus_dmamap_t *)); 131 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 132 bus_size_t, struct proc *, int)); 133 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 134 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 135 bus_addr_t, bus_size_t, int)); 136 #endif 137 138 #if defined(SUN4M) 139 static int sparc_vct_iommu_dmamap_create __P((void *, vme_size_t, vme_am_t, 140 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 141 int, bus_dmamap_t *)); 142 static int sparc_vme_iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, 143 int, bus_size_t, bus_size_t, int, bus_dmamap_t *)); 144 145 static int sparc_vme_iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, 146 void *, bus_size_t, struct proc *, int)); 147 static void sparc_vme_iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 148 static void sparc_vme_iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 149 bus_addr_t, bus_size_t, int)); 150 #endif 151 152 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 153 int, size_t, caddr_t *, int)); 154 #if 0 155 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 156 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 157 static paddr_t sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 158 bus_dma_segment_t *, int, off_t, int, int)); 159 #endif 160 161 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 162 163 CFATTACH_DECL(vme_mainbus, sizeof(struct sparcvme_softc), 164 vmematch_mainbus, vmeattach_mainbus, NULL, NULL); 165 166 CFATTACH_DECL(vme_iommu, sizeof(struct sparcvme_softc), 167 vmematch_iommu, vmeattach_iommu, NULL, NULL); 168 169 int (*vmeerr_handler) __P((void)); 170 171 #define VMEMOD_D32 0x40 /* ??? */ 172 173 /* If the PROM does not provide the `ranges' property, we make up our own */ 174 struct rom_range vmebus_translations[] = { 175 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 176 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 177 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 178 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 179 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 180 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 181 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 182 #undef _DS 183 }; 184 185 /* 186 * The VME bus logic on sun4 machines maps DMA requests in the first MB 187 * of VME space to the last MB of DVMA space. `vme_dvmamap' is used 188 * for DVMA space allocations. The DMA addresses returned by 189 * bus_dmamap_load*() must be relocated by -VME4_DVMA_BASE. 190 */ 191 struct extent *vme_dvmamap; 192 193 /* 194 * The VME hardware on the sun4m IOMMU maps the first 8MB of 32-bit 195 * VME space to the last 8MB of DVMA space and the first 1MB of 196 * 24-bit VME space to the first 1MB of the last 8MB of DVMA space 197 * (thus 24-bit VME space overlaps the first 1MB of of 32-bit space). 198 * The following constants define subregions in the IOMMU DVMA map 199 * for VME DVMA allocations. The DMA addresses returned by 200 * bus_dmamap_load*() must be relocated by -VME_IOMMU_DVMA_BASE. 201 */ 202 #define VME_IOMMU_DVMA_BASE 0xff800000 203 #define VME_IOMMU_DVMA_AM24_BASE VME_IOMMU_DVMA_BASE 204 #define VME_IOMMU_DVMA_AM24_END 0xff900000 205 #define VME_IOMMU_DVMA_AM32_BASE VME_IOMMU_DVMA_BASE 206 #define VME_IOMMU_DVMA_AM32_END IOMMU_DVMA_END 207 208 struct sparc_bus_space_tag sparc_vme_bus_tag = { 209 NULL, /* cookie */ 210 NULL, /* parent bus tag */ 211 NULL, /* ranges */ 212 0, /* nranges */ 213 NULL, /* bus_map */ 214 NULL, /* bus_unmap */ 215 NULL, /* bus_subregion */ 216 NULL, /* barrier */ 217 NULL, /* mmap */ 218 NULL, /* intr_establish */ 219 #if __FULL_SPARC_BUS_SPACE 220 NULL, /* read_1 */ 221 NULL, /* read_2 */ 222 NULL, /* read_4 */ 223 NULL, /* read_8 */ 224 NULL, /* write_1 */ 225 NULL, /* write_2 */ 226 NULL, /* write_4 */ 227 NULL /* write_8 */ 228 #endif 229 }; 230 231 struct vme_chipset_tag sparc_vme_chipset_tag = { 232 NULL, 233 sparc_vme_map, 234 sparc_vme_unmap, 235 sparc_vme_probe, 236 sparc_vme_intr_map, 237 sparc_vme_intr_evcnt, 238 sparc_vme_intr_establish, 239 sparc_vme_intr_disestablish, 240 0, 0, 0 /* bus specific DMA stuff */ 241 }; 242 243 244 #if defined(SUN4) 245 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 246 NULL, /* cookie */ 247 _bus_dmamap_create, 248 _bus_dmamap_destroy, 249 sparc_vme4_dmamap_load, 250 _bus_dmamap_load_mbuf, 251 _bus_dmamap_load_uio, 252 _bus_dmamap_load_raw, 253 sparc_vme4_dmamap_unload, 254 sparc_vme4_dmamap_sync, 255 256 _bus_dmamem_alloc, 257 _bus_dmamem_free, 258 sparc_vme_dmamem_map, 259 _bus_dmamem_unmap, 260 _bus_dmamem_mmap 261 }; 262 #endif 263 264 #if defined(SUN4M) 265 struct sparc_bus_dma_tag sparc_vme_iommu_dma_tag = { 266 NULL, /* cookie */ 267 sparc_vme_iommu_dmamap_create, 268 _bus_dmamap_destroy, 269 sparc_vme_iommu_dmamap_load, 270 _bus_dmamap_load_mbuf, 271 _bus_dmamap_load_uio, 272 _bus_dmamap_load_raw, 273 sparc_vme_iommu_dmamap_unload, 274 sparc_vme_iommu_dmamap_sync, 275 276 _bus_dmamem_alloc, 277 _bus_dmamem_free, 278 sparc_vme_dmamem_map, 279 _bus_dmamem_unmap, 280 _bus_dmamem_mmap 281 }; 282 #endif 283 284 285 int 286 vmematch_mainbus(parent, cf, aux) 287 struct device *parent; 288 struct cfdata *cf; 289 void *aux; 290 { 291 struct mainbus_attach_args *ma = aux; 292 293 if (!CPU_ISSUN4) 294 return (0); 295 296 return (strcmp("vme", ma->ma_name) == 0); 297 } 298 299 int 300 vmematch_iommu(parent, cf, aux) 301 struct device *parent; 302 struct cfdata *cf; 303 void *aux; 304 { 305 struct iommu_attach_args *ia = aux; 306 307 return (strcmp("vme", ia->iom_name) == 0); 308 } 309 310 311 void 312 vmeattach_mainbus(parent, self, aux) 313 struct device *parent, *self; 314 void *aux; 315 { 316 #if defined(SUN4) 317 struct mainbus_attach_args *ma = aux; 318 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 319 struct vmebus_attach_args vba; 320 321 if (self->dv_unit > 0) { 322 printf(" unsupported\n"); 323 return; 324 } 325 326 sc->sc_bustag = ma->ma_bustag; 327 sc->sc_dmatag = ma->ma_dmatag; 328 329 /* VME interrupt entry point */ 330 sc->sc_vmeintr = vmeintr4; 331 332 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 333 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 334 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 335 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 336 337 #if 0 338 sparc_vme_bus_tag.parent = ma->ma_bustag; 339 vba.vba_bustag = &sparc_vme_bus_tag; 340 #endif 341 vba.va_vct = &sparc_vme_chipset_tag; 342 vba.va_bdt = &sparc_vme4_dma_tag; 343 vba.va_slaveconfig = 0; 344 345 /* Fall back to our own `range' construction */ 346 sc->sc_range = vmebus_translations; 347 sc->sc_nrange = 348 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 349 350 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 351 M_DEVBUF, 0, 0, EX_NOWAIT); 352 if (vme_dvmamap == NULL) 353 panic("vme: unable to allocate DVMA map"); 354 355 printf("\n"); 356 (void)config_found(self, &vba, 0); 357 358 #endif 359 return; 360 } 361 362 /* sun4m vmebus */ 363 void 364 vmeattach_iommu(parent, self, aux) 365 struct device *parent, *self; 366 void *aux; 367 { 368 #if defined(SUN4M) 369 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 370 struct iommu_attach_args *ia = aux; 371 struct vmebus_attach_args vba; 372 bus_space_handle_t bh; 373 int node; 374 int cline; 375 376 if (self->dv_unit > 0) { 377 printf(" unsupported\n"); 378 return; 379 } 380 381 sc->sc_bustag = ia->iom_bustag; 382 sc->sc_dmatag = ia->iom_dmatag; 383 384 /* VME interrupt entry point */ 385 sc->sc_vmeintr = vmeintr4m; 386 387 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 388 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct_iommu_dmamap_create; 389 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 390 /*XXX*/ sparc_vme_iommu_dma_tag._cookie = self; 391 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme_iommu_barrier; 392 393 #if 0 394 vba.vba_bustag = &sparc_vme_bus_tag; 395 #endif 396 vba.va_vct = &sparc_vme_chipset_tag; 397 vba.va_bdt = &sparc_vme_iommu_dma_tag; 398 vba.va_slaveconfig = 0; 399 400 node = ia->iom_node; 401 402 /* 403 * Map VME control space 404 */ 405 if (ia->iom_nreg < 2) { 406 printf("%s: only %d register sets\n", self->dv_xname, 407 ia->iom_nreg); 408 return; 409 } 410 411 if (bus_space_map(ia->iom_bustag, 412 (bus_addr_t) BUS_ADDR(ia->iom_reg[0].oa_space, 413 ia->iom_reg[0].oa_base), 414 (bus_size_t)ia->iom_reg[0].oa_size, 415 BUS_SPACE_MAP_LINEAR, 416 &bh) != 0) { 417 panic("%s: can't map vmebusreg", self->dv_xname); 418 } 419 sc->sc_reg = (struct vmebusreg *)bh; 420 421 if (bus_space_map(ia->iom_bustag, 422 (bus_addr_t) BUS_ADDR(ia->iom_reg[1].oa_space, 423 ia->iom_reg[1].oa_base), 424 (bus_size_t)ia->iom_reg[1].oa_size, 425 BUS_SPACE_MAP_LINEAR, 426 &bh) != 0) { 427 panic("%s: can't map vmebusvec", self->dv_xname); 428 } 429 sc->sc_vec = (struct vmebusvec *)bh; 430 431 /* 432 * Map VME IO cache tags and flush control. 433 */ 434 if (bus_space_map(ia->iom_bustag, 435 (bus_addr_t) BUS_ADDR( 436 ia->iom_reg[1].oa_space, 437 ia->iom_reg[1].oa_base + VME_IOC_TAGOFFSET), 438 VME_IOC_SIZE, 439 BUS_SPACE_MAP_LINEAR, 440 &bh) != 0) { 441 panic("%s: can't map IOC tags", self->dv_xname); 442 } 443 sc->sc_ioctags = (u_int32_t *)bh; 444 445 if (bus_space_map(ia->iom_bustag, 446 (bus_addr_t) BUS_ADDR( 447 ia->iom_reg[1].oa_space, 448 ia->iom_reg[1].oa_base + VME_IOC_FLUSHOFFSET), 449 VME_IOC_SIZE, 450 BUS_SPACE_MAP_LINEAR, 451 &bh) != 0) { 452 panic("%s: can't map IOC flush registers", self->dv_xname); 453 } 454 sc->sc_iocflush = (u_int32_t *)bh; 455 456 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 457 458 /* 459 * Get "range" property. 460 */ 461 if (PROM_getprop(node, "ranges", sizeof(struct rom_range), 462 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 463 panic("%s: can't get ranges property", self->dv_xname); 464 } 465 466 sparcvme_sc = sc; 467 vmeerr_handler = sparc_vme_error; 468 469 /* 470 * Invalidate all IO-cache entries. 471 */ 472 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 473 sc->sc_ioctags[--cline] = 0; 474 } 475 476 /* Enable IO-cache */ 477 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 478 479 printf(": version 0x%x\n", 480 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 481 482 (void)config_found(self, &vba, 0); 483 #endif 484 } 485 486 #if defined(SUN4M) 487 static int 488 sparc_vme_error() 489 { 490 struct sparcvme_softc *sc = sparcvme_sc; 491 u_int32_t afsr, afpa; 492 char bits[64]; 493 494 afsr = sc->sc_reg->vmebus_afsr; 495 afpa = sc->sc_reg->vmebus_afar; 496 printf("VME error:\n\tAFSR %s\n", 497 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 498 printf("\taddress: 0x%x%x\n", afsr, afpa); 499 return (0); 500 } 501 #endif 502 503 int 504 vmebus_translate(sc, mod, addr, bap) 505 struct sparcvme_softc *sc; 506 vme_am_t mod; 507 vme_addr_t addr; 508 bus_addr_t *bap; 509 { 510 int i; 511 512 for (i = 0; i < sc->sc_nrange; i++) { 513 struct rom_range *rp = &sc->sc_range[i]; 514 515 if (rp->cspace != mod) 516 continue; 517 518 /* We've found the connection to the parent bus */ 519 *bap = BUS_ADDR(rp->pspace, rp->poffset + addr); 520 return (0); 521 } 522 return (ENOENT); 523 } 524 525 struct vmeprobe_myarg { 526 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 527 void *cbarg; 528 bus_space_tag_t tag; 529 int res; /* backwards */ 530 }; 531 532 static int vmeprobe_mycb __P((void *, void *)); 533 static int 534 vmeprobe_mycb(bh, arg) 535 void *bh, *arg; 536 { 537 struct vmeprobe_myarg *a = arg; 538 539 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 540 return (!a->res); 541 } 542 543 int 544 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 545 void *cookie; 546 vme_addr_t addr; 547 vme_size_t len; 548 vme_am_t mod; 549 vme_datasize_t datasize; 550 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 551 void *arg; 552 { 553 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 554 bus_addr_t paddr; 555 bus_size_t size; 556 struct vmeprobe_myarg myarg; 557 int res, i; 558 559 if (vmebus_translate(sc, mod, addr, &paddr) != 0) 560 return (EINVAL); 561 562 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 563 564 if (callback) { 565 myarg.cb = callback; 566 myarg.cbarg = arg; 567 myarg.tag = sc->sc_bustag; 568 myarg.res = 0; 569 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 570 0, vmeprobe_mycb, &myarg); 571 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 572 } 573 574 for (i = 0; i < len / size; i++) { 575 myarg.res = 0; 576 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 577 0, 0, 0); 578 if (res == 0) 579 return (EIO); 580 paddr += size; 581 } 582 return (0); 583 } 584 585 int 586 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 587 void *cookie; 588 vme_addr_t addr; 589 vme_size_t size; 590 vme_am_t mod; 591 vme_datasize_t datasize; 592 vme_swap_t swap; 593 bus_space_tag_t *tp; 594 bus_space_handle_t *hp; 595 vme_mapresc_t *rp; 596 { 597 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 598 bus_addr_t paddr; 599 int error; 600 601 error = vmebus_translate(sc, mod, addr, &paddr); 602 if (error != 0) 603 return (error); 604 605 *tp = sc->sc_bustag; 606 return (bus_space_map(sc->sc_bustag, paddr, size, 0, hp)); 607 } 608 609 int 610 sparc_vme_mmap_cookie(addr, mod, hp) 611 vme_addr_t addr; 612 vme_am_t mod; 613 bus_space_handle_t *hp; 614 { 615 struct sparcvme_softc *sc = sparcvme_sc; 616 bus_addr_t paddr; 617 int error; 618 619 error = vmebus_translate(sc, mod, addr, &paddr); 620 if (error != 0) 621 return (error); 622 623 return (bus_space_mmap(sc->sc_bustag, paddr, 0, 624 0/*prot is ignored*/, 0)); 625 } 626 627 #if defined(SUN4M) 628 void 629 sparc_vme_iommu_barrier(t, h, offset, size, flags) 630 bus_space_tag_t t; 631 bus_space_handle_t h; 632 bus_size_t offset; 633 bus_size_t size; 634 int flags; 635 { 636 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 637 638 /* Read async fault status to flush write-buffers */ 639 (*(volatile int *)&vbp->vmebus_afsr); 640 } 641 #endif 642 643 644 645 /* 646 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 647 */ 648 static int vme_ipl_to_pil[] = { 649 0, 650 2, 651 3, 652 5, 653 7, 654 9, 655 11, 656 13 657 }; 658 659 660 /* 661 * All VME device interrupts go through vmeintr(). This function reads 662 * the VME vector from the bus, then dispatches the device interrupt 663 * handler. All handlers for devices that map to the same Processor 664 * Interrupt Level (according to the table above) are on a linked list 665 * of `sparc_vme_intr_handle' structures. The head of which is passed 666 * down as the argument to `vmeintr(void *arg)'. 667 */ 668 struct sparc_vme_intr_handle { 669 struct intrhand ih; 670 struct sparc_vme_intr_handle *next; 671 int vec; /* VME interrupt vector */ 672 int pri; /* VME interrupt priority */ 673 struct sparcvme_softc *sc;/*XXX*/ 674 }; 675 676 #if defined(SUN4) 677 int 678 vmeintr4(arg) 679 void *arg; 680 { 681 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 682 int level, vec; 683 int rv = 0; 684 685 level = (ihp->pri << 1) | 1; 686 687 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 688 689 if (vec == -1) { 690 #ifdef DEBUG 691 /* 692 * This seems to happen only with the i82586 based 693 * `ie1' boards. 694 */ 695 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 696 #endif 697 return (1); /* XXX - pretend we handled it, for now */ 698 } 699 700 for (; ihp; ihp = ihp->next) 701 if (ihp->vec == vec && ihp->ih.ih_fun) { 702 splx(ihp->ih.ih_classipl); 703 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 704 } 705 706 return (rv); 707 } 708 #endif 709 710 #if defined(SUN4M) 711 int 712 vmeintr4m(arg) 713 void *arg; 714 { 715 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 716 int level, vec; 717 int rv = 0; 718 719 level = (ihp->pri << 1) | 1; 720 721 #if 0 722 int pending; 723 724 /* Flush VME <=> Sbus write buffers */ 725 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 726 727 pending = *((int*)ICR_SI_PEND); 728 if ((pending & SINTR_VME(ihp->pri)) == 0) { 729 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 730 ihp->pri, pending); 731 return (0); 732 } 733 #endif 734 #if 0 735 /* Why gives this a bus timeout sometimes? */ 736 vec = ihp->sc->sc_vec->vmebusvec[level]; 737 #else 738 /* so, arrange to catch the fault... */ 739 { 740 extern struct user *proc0paddr; 741 extern int fkbyte __P((caddr_t, struct pcb *)); 742 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 743 struct pcb *xpcb; 744 u_long saveonfault; 745 int s; 746 747 s = splhigh(); 748 if (curlwp == NULL) 749 xpcb = (struct pcb *)proc0paddr; 750 else 751 xpcb = &curlwp->l_addr->u_pcb; 752 753 saveonfault = (u_long)xpcb->pcb_onfault; 754 vec = fkbyte(addr, xpcb); 755 xpcb->pcb_onfault = (caddr_t)saveonfault; 756 757 splx(s); 758 } 759 #endif 760 761 if (vec == -1) { 762 #ifdef DEBUG 763 /* 764 * This seems to happen only with the i82586 based 765 * `ie1' boards. 766 */ 767 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 768 printf(" ICR_SI_PEND=0x%x; VME AFSR=0x%x; VME AFAR=0x%x\n", 769 *((int*)ICR_SI_PEND), 770 ihp->sc->sc_reg->vmebus_afsr, 771 ihp->sc->sc_reg->vmebus_afar); 772 #endif 773 return (1); /* XXX - pretend we handled it, for now */ 774 } 775 776 for (; ihp; ihp = ihp->next) 777 if (ihp->vec == vec && ihp->ih.ih_fun) { 778 splx(ihp->ih.ih_classipl); 779 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 780 } 781 782 return (rv); 783 } 784 #endif 785 786 int 787 sparc_vme_intr_map(cookie, level, vec, ihp) 788 void *cookie; 789 int level; 790 int vec; 791 vme_intr_handle_t *ihp; 792 { 793 struct sparc_vme_intr_handle *ih; 794 795 ih = (vme_intr_handle_t) 796 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 797 ih->pri = level; 798 ih->vec = vec; 799 ih->sc = cookie;/*XXX*/ 800 *ihp = ih; 801 return (0); 802 } 803 804 const struct evcnt * 805 sparc_vme_intr_evcnt(cookie, vih) 806 void *cookie; 807 vme_intr_handle_t vih; 808 { 809 810 /* XXX for now, no evcnt parent reported */ 811 return NULL; 812 } 813 814 void * 815 sparc_vme_intr_establish(cookie, vih, level, func, arg) 816 void *cookie; 817 vme_intr_handle_t vih; 818 int level; 819 int (*func) __P((void *)); 820 void *arg; 821 { 822 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 823 struct sparc_vme_intr_handle *svih = 824 (struct sparc_vme_intr_handle *)vih; 825 struct intrhand *ih; 826 int pil; 827 828 /* Translate VME priority to processor IPL */ 829 pil = vme_ipl_to_pil[svih->pri]; 830 831 if (level < pil) 832 panic("vme_intr_establish: class lvl (%d) < pil (%d)\n", 833 level, pil); 834 835 svih->ih.ih_fun = func; 836 svih->ih.ih_arg = arg; 837 svih->ih.ih_classipl = level; /* note: used slightly differently 838 than in intr.c (no shift) */ 839 svih->next = NULL; 840 841 /* ensure the interrupt subsystem will call us at this level */ 842 for (ih = intrhand[pil]; ih != NULL; ih = ih->ih_next) 843 if (ih->ih_fun == sc->sc_vmeintr) 844 break; 845 846 if (ih == NULL) { 847 ih = (struct intrhand *) 848 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 849 if (ih == NULL) 850 panic("vme_addirq"); 851 bzero(ih, sizeof *ih); 852 ih->ih_fun = sc->sc_vmeintr; 853 ih->ih_arg = vih; 854 intr_establish(pil, 0, ih, NULL); 855 } else { 856 svih->next = (vme_intr_handle_t)ih->ih_arg; 857 ih->ih_arg = vih; 858 } 859 return (NULL); 860 } 861 862 void 863 sparc_vme_unmap(cookie, resc) 864 void * cookie; 865 vme_mapresc_t resc; 866 { 867 /* Not implemented */ 868 panic("sparc_vme_unmap"); 869 } 870 871 void 872 sparc_vme_intr_disestablish(cookie, a) 873 void *cookie; 874 void *a; 875 { 876 /* Not implemented */ 877 panic("sparc_vme_intr_disestablish"); 878 } 879 880 881 882 /* 883 * VME DMA functions. 884 */ 885 886 static void 887 sparc_vct_dmamap_destroy(cookie, map) 888 void *cookie; 889 bus_dmamap_t map; 890 { 891 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 892 bus_dmamap_destroy(sc->sc_dmatag, map); 893 } 894 895 #if defined(SUN4) 896 static int 897 sparc_vct4_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 898 boundary, flags, dmamp) 899 void *cookie; 900 vme_size_t size; 901 vme_am_t am; 902 vme_datasize_t datasize; 903 vme_swap_t swap; 904 int nsegments; 905 vme_size_t maxsegsz; 906 vme_addr_t boundary; 907 int flags; 908 bus_dmamap_t *dmamp; 909 { 910 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 911 912 /* Allocate a base map through parent bus ops */ 913 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 914 boundary, flags, dmamp)); 915 } 916 917 int 918 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 919 bus_dma_tag_t t; 920 bus_dmamap_t map; 921 void *buf; 922 bus_size_t buflen; 923 struct proc *p; 924 int flags; 925 { 926 bus_addr_t dva; 927 bus_size_t sgsize; 928 vaddr_t va, voff; 929 pmap_t pmap; 930 int pagesz = PAGE_SIZE; 931 int error; 932 933 cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 934 935 va = (vaddr_t)buf; 936 voff = va & (pagesz - 1); 937 va &= -pagesz; 938 939 /* 940 * Allocate an integral number of pages from DVMA space 941 * covering the passed buffer. 942 */ 943 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 944 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 945 map->_dm_boundary, 946 (flags & BUS_DMA_NOWAIT) == 0 947 ? EX_WAITOK 948 : EX_NOWAIT, 949 (u_long *)&dva); 950 if (error != 0) 951 return (error); 952 953 map->dm_mapsize = buflen; 954 map->dm_nsegs = 1; 955 /* Adjust DVMA address to VME view */ 956 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 957 map->dm_segs[0].ds_len = buflen; 958 map->dm_segs[0]._ds_sgsize = sgsize; 959 960 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 961 962 for (; sgsize != 0; ) { 963 paddr_t pa; 964 /* 965 * Get the physical address for this page. 966 */ 967 (void) pmap_extract(pmap, va, &pa); 968 969 #ifdef notyet 970 if (have_iocache) 971 pa |= PG_IOC; 972 #endif 973 pmap_enter(pmap_kernel(), dva, 974 pa | PMAP_NC, 975 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 976 977 dva += pagesz; 978 va += pagesz; 979 sgsize -= pagesz; 980 } 981 pmap_update(pmap_kernel()); 982 983 return (0); 984 } 985 986 void 987 sparc_vme4_dmamap_unload(t, map) 988 bus_dma_tag_t t; 989 bus_dmamap_t map; 990 { 991 bus_dma_segment_t *segs = map->dm_segs; 992 int nsegs = map->dm_nsegs; 993 bus_addr_t dva; 994 bus_size_t len; 995 int i, s, error; 996 997 for (i = 0; i < nsegs; i++) { 998 /* Go from VME to CPU view */ 999 dva = segs[i].ds_addr + VME4_DVMA_BASE; 1000 dva &= -PAGE_SIZE; 1001 len = segs[i]._ds_sgsize; 1002 1003 /* Remove double-mapping in DVMA space */ 1004 pmap_remove(pmap_kernel(), dva, dva + len); 1005 1006 /* Release DVMA space */ 1007 s = splhigh(); 1008 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 1009 splx(s); 1010 if (error != 0) 1011 printf("warning: %ld of DVMA space lost\n", len); 1012 } 1013 pmap_update(pmap_kernel()); 1014 1015 /* Mark the mappings as invalid. */ 1016 map->dm_mapsize = 0; 1017 map->dm_nsegs = 0; 1018 } 1019 1020 void 1021 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 1022 bus_dma_tag_t t; 1023 bus_dmamap_t map; 1024 bus_addr_t offset; 1025 bus_size_t len; 1026 int ops; 1027 { 1028 1029 /* 1030 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 1031 * Currently the cache is flushed in bus_dma_load()... 1032 */ 1033 } 1034 #endif /* SUN4 */ 1035 1036 #if defined(SUN4M) 1037 static int 1038 sparc_vme_iommu_dmamap_create (t, size, nsegments, maxsegsz, 1039 boundary, flags, dmamp) 1040 bus_dma_tag_t t; 1041 bus_size_t size; 1042 int nsegments; 1043 bus_size_t maxsegsz; 1044 bus_size_t boundary; 1045 int flags; 1046 bus_dmamap_t *dmamp; 1047 { 1048 1049 printf("sparc_vme_dmamap_create: please use `vme_dmamap_create'\n"); 1050 return (EINVAL); 1051 } 1052 1053 static int 1054 sparc_vct_iommu_dmamap_create(cookie, size, am, datasize, swap, nsegments, 1055 maxsegsz, boundary, flags, dmamp) 1056 void *cookie; 1057 vme_size_t size; 1058 vme_am_t am; 1059 vme_datasize_t datasize; 1060 vme_swap_t swap; 1061 int nsegments; 1062 vme_size_t maxsegsz; 1063 vme_addr_t boundary; 1064 int flags; 1065 bus_dmamap_t *dmamp; 1066 { 1067 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 1068 bus_dmamap_t map; 1069 int error; 1070 1071 /* Allocate a base map through parent bus ops */ 1072 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1073 boundary, flags, &map); 1074 if (error != 0) 1075 return (error); 1076 1077 /* 1078 * Each I/O cache line maps to a 8K section of VME DVMA space, so 1079 * we must ensure that DVMA alloctions are always 8K aligned. 1080 */ 1081 map->_dm_align = VME_IOC_PAGESZ; 1082 1083 /* Set map region based on Address Modifier */ 1084 switch ((am & VME_AM_ADRSIZEMASK)) { 1085 case VME_AM_A16: 1086 case VME_AM_A24: 1087 /* 1 MB of DVMA space */ 1088 map->_dm_ex_start = VME_IOMMU_DVMA_AM24_BASE; 1089 map->_dm_ex_end = VME_IOMMU_DVMA_AM24_END; 1090 break; 1091 case VME_AM_A32: 1092 /* 8 MB of DVMA space */ 1093 map->_dm_ex_start = VME_IOMMU_DVMA_AM32_BASE; 1094 map->_dm_ex_end = VME_IOMMU_DVMA_AM32_END; 1095 break; 1096 } 1097 1098 *dmamp = map; 1099 return (0); 1100 } 1101 1102 int 1103 sparc_vme_iommu_dmamap_load(t, map, buf, buflen, p, flags) 1104 bus_dma_tag_t t; 1105 bus_dmamap_t map; 1106 void *buf; 1107 bus_size_t buflen; 1108 struct proc *p; 1109 int flags; 1110 { 1111 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1112 volatile u_int32_t *ioctags; 1113 int error; 1114 1115 /* Round request to a multiple of the I/O cache size */ 1116 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 1117 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1118 if (error != 0) 1119 return (error); 1120 1121 /* Allocate I/O cache entries for this range */ 1122 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1123 while (buflen > 0) { 1124 *ioctags = VME_IOC_IC | VME_IOC_W; 1125 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1126 buflen -= VME_IOC_PAGESZ; 1127 } 1128 1129 /* 1130 * Adjust DVMA address to VME view. 1131 * Note: the DVMA base address is the same for all 1132 * VME address spaces. 1133 */ 1134 map->dm_segs[0].ds_addr -= VME_IOMMU_DVMA_BASE; 1135 return (0); 1136 } 1137 1138 1139 void 1140 sparc_vme_iommu_dmamap_unload(t, map) 1141 bus_dma_tag_t t; 1142 bus_dmamap_t map; 1143 { 1144 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1145 volatile u_int32_t *flushregs; 1146 int len; 1147 1148 /* Go from VME to CPU view */ 1149 map->dm_segs[0].ds_addr += VME_IOMMU_DVMA_BASE; 1150 1151 /* Flush VME I/O cache */ 1152 len = map->dm_segs[0]._ds_sgsize; 1153 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1154 while (len > 0) { 1155 *flushregs = 0; 1156 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1157 len -= VME_IOC_PAGESZ; 1158 } 1159 1160 /* 1161 * Start a read from `tag space' which will not complete until 1162 * all cache flushes have finished 1163 */ 1164 (*sc->sc_ioctags); 1165 1166 bus_dmamap_unload(sc->sc_dmatag, map); 1167 } 1168 1169 void 1170 sparc_vme_iommu_dmamap_sync(t, map, offset, len, ops) 1171 bus_dma_tag_t t; 1172 bus_dmamap_t map; 1173 bus_addr_t offset; 1174 bus_size_t len; 1175 int ops; 1176 { 1177 1178 /* 1179 * XXX Should perform cache flushes as necessary. 1180 */ 1181 } 1182 #endif /* SUN4M */ 1183 1184 int 1185 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1186 bus_dma_tag_t t; 1187 bus_dma_segment_t *segs; 1188 int nsegs; 1189 size_t size; 1190 caddr_t *kvap; 1191 int flags; 1192 { 1193 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1194 1195 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1196 } 1197
Indexes created Wed Sep 24 05:09:52 GMT 2025