vme_machdep.c revision 1.49
1 /* $NetBSD: vme_machdep.c,v 1.49 2004/03/17 17:04:59 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: vme_machdep.c,v 1.49 2004/03/17 17:04:59 pk Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/extent.h> 44 #include <sys/systm.h> 45 #include <sys/device.h> 46 #include <sys/malloc.h> 47 #include <sys/errno.h> 48 49 #include <sys/proc.h> 50 #include <sys/user.h> 51 #include <sys/syslog.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #define _SPARC_BUS_DMA_PRIVATE 56 #include <machine/bus.h> 57 #include <sparc/sparc/iommuvar.h> 58 #include <machine/autoconf.h> 59 #include <machine/oldmon.h> 60 #include <machine/cpu.h> 61 #include <machine/ctlreg.h> 62 63 #include <dev/vme/vmereg.h> 64 #include <dev/vme/vmevar.h> 65 66 #include <sparc/sparc/asm.h> 67 #include <sparc/sparc/vaddrs.h> 68 #include <sparc/sparc/cpuvar.h> 69 #include <sparc/dev/vmereg.h> 70 71 struct sparcvme_softc { 72 struct device sc_dev; /* base device */ 73 bus_space_tag_t sc_bustag; 74 bus_dma_tag_t sc_dmatag; 75 struct vmebusreg *sc_reg; /* VME control registers */ 76 struct vmebusvec *sc_vec; /* VME interrupt vector */ 77 struct rom_range *sc_range; /* ROM range property */ 78 int sc_nrange; 79 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 80 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 81 int (*sc_vmeintr) __P((void *)); 82 }; 83 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 84 85 /* autoconfiguration driver */ 86 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 87 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 88 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 89 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 90 #if defined(SUN4) 91 int vmeintr4 __P((void *)); 92 #endif 93 #if defined(SUN4M) 94 int vmeintr4m __P((void *)); 95 static int sparc_vme_error __P((void)); 96 #endif 97 98 99 static int sparc_vme_probe __P((void *, vme_addr_t, vme_size_t, 100 vme_am_t, vme_datasize_t, 101 int (*) __P((void *, bus_space_tag_t, bus_space_handle_t)), void *)); 102 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_am_t, 103 vme_datasize_t, vme_swap_t, 104 bus_space_tag_t *, bus_space_handle_t *, 105 vme_mapresc_t *)); 106 static void sparc_vme_unmap __P((void *, vme_mapresc_t)); 107 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 108 static const struct evcnt *sparc_vme_intr_evcnt __P((void *, 109 vme_intr_handle_t)); 110 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, int, 111 int (*) __P((void *)), void *)); 112 static void sparc_vme_intr_disestablish __P((void *, void *)); 113 114 static int vmebus_translate __P((struct sparcvme_softc *, vme_am_t, 115 vme_addr_t, bus_addr_t *)); 116 #if defined(SUN4M) 117 static void sparc_vme_iommu_barrier __P(( bus_space_tag_t, bus_space_handle_t, 118 bus_size_t, bus_size_t, int)); 119 120 #endif 121 122 /* 123 * DMA functions. 124 */ 125 #if defined(SUN4) || defined(SUN4M) 126 static void sparc_vct_dmamap_destroy __P((void *, bus_dmamap_t)); 127 #endif 128 129 #if defined(SUN4) 130 static int sparc_vct4_dmamap_create __P((void *, vme_size_t, vme_am_t, 131 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 132 int, bus_dmamap_t *)); 133 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 134 bus_size_t, struct proc *, int)); 135 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 136 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 137 bus_addr_t, bus_size_t, int)); 138 #endif /* SUN4 */ 139 140 #if defined(SUN4M) 141 static int sparc_vct_iommu_dmamap_create __P((void *, vme_size_t, vme_am_t, 142 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 143 int, bus_dmamap_t *)); 144 static int sparc_vme_iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, 145 int, bus_size_t, bus_size_t, int, bus_dmamap_t *)); 146 147 static int sparc_vme_iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, 148 void *, bus_size_t, struct proc *, int)); 149 static void sparc_vme_iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 150 static void sparc_vme_iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 151 bus_addr_t, bus_size_t, int)); 152 #endif /* SUN4M */ 153 154 #if defined(SUN4) || defined(SUN4M) 155 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 156 int, size_t, caddr_t *, int)); 157 #endif 158 159 #if 0 160 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 161 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 162 static paddr_t sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 163 bus_dma_segment_t *, int, off_t, int, int)); 164 #endif 165 166 int sparc_vme_mmap_cookie __P((vme_addr_t, vme_am_t, bus_space_handle_t *)); 167 168 CFATTACH_DECL(vme_mainbus, sizeof(struct sparcvme_softc), 169 vmematch_mainbus, vmeattach_mainbus, NULL, NULL); 170 171 CFATTACH_DECL(vme_iommu, sizeof(struct sparcvme_softc), 172 vmematch_iommu, vmeattach_iommu, NULL, NULL); 173 174 int (*vmeerr_handler) __P((void)); 175 176 #define VMEMOD_D32 0x40 /* ??? */ 177 178 /* If the PROM does not provide the `ranges' property, we make up our own */ 179 struct rom_range vmebus_translations[] = { 180 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 181 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 182 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 183 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 184 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 185 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 186 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 187 #undef _DS 188 }; 189 190 /* 191 * The VME bus logic on sun4 machines maps DMA requests in the first MB 192 * of VME space to the last MB of DVMA space. `vme_dvmamap' is used 193 * for DVMA space allocations. The DMA addresses returned by 194 * bus_dmamap_load*() must be relocated by -VME4_DVMA_BASE. 195 */ 196 struct extent *vme_dvmamap; 197 198 /* 199 * The VME hardware on the sun4m IOMMU maps the first 8MB of 32-bit 200 * VME space to the last 8MB of DVMA space and the first 1MB of 201 * 24-bit VME space to the first 1MB of the last 8MB of DVMA space 202 * (thus 24-bit VME space overlaps the first 1MB of of 32-bit space). 203 * The following constants define subregions in the IOMMU DVMA map 204 * for VME DVMA allocations. The DMA addresses returned by 205 * bus_dmamap_load*() must be relocated by -VME_IOMMU_DVMA_BASE. 206 */ 207 #define VME_IOMMU_DVMA_BASE 0xff800000 208 #define VME_IOMMU_DVMA_AM24_BASE VME_IOMMU_DVMA_BASE 209 #define VME_IOMMU_DVMA_AM24_END 0xff900000 210 #define VME_IOMMU_DVMA_AM32_BASE VME_IOMMU_DVMA_BASE 211 #define VME_IOMMU_DVMA_AM32_END IOMMU_DVMA_END 212 213 struct sparc_bus_space_tag sparc_vme_bus_tag = { 214 NULL, /* cookie */ 215 NULL, /* parent bus tag */ 216 NULL, /* ranges */ 217 0, /* nranges */ 218 NULL, /* bus_map */ 219 NULL, /* bus_unmap */ 220 NULL, /* bus_subregion */ 221 NULL, /* barrier */ 222 NULL, /* mmap */ 223 NULL, /* intr_establish */ 224 #if __FULL_SPARC_BUS_SPACE 225 NULL, /* read_1 */ 226 NULL, /* read_2 */ 227 NULL, /* read_4 */ 228 NULL, /* read_8 */ 229 NULL, /* write_1 */ 230 NULL, /* write_2 */ 231 NULL, /* write_4 */ 232 NULL /* write_8 */ 233 #endif 234 }; 235 236 struct vme_chipset_tag sparc_vme_chipset_tag = { 237 NULL, 238 sparc_vme_map, 239 sparc_vme_unmap, 240 sparc_vme_probe, 241 sparc_vme_intr_map, 242 sparc_vme_intr_evcnt, 243 sparc_vme_intr_establish, 244 sparc_vme_intr_disestablish, 245 0, 0, 0 /* bus specific DMA stuff */ 246 }; 247 248 249 #if defined(SUN4) 250 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 251 NULL, /* cookie */ 252 _bus_dmamap_create, 253 _bus_dmamap_destroy, 254 sparc_vme4_dmamap_load, 255 _bus_dmamap_load_mbuf, 256 _bus_dmamap_load_uio, 257 _bus_dmamap_load_raw, 258 sparc_vme4_dmamap_unload, 259 sparc_vme4_dmamap_sync, 260 261 _bus_dmamem_alloc, 262 _bus_dmamem_free, 263 sparc_vme_dmamem_map, 264 _bus_dmamem_unmap, 265 _bus_dmamem_mmap 266 }; 267 #endif 268 269 #if defined(SUN4M) 270 struct sparc_bus_dma_tag sparc_vme_iommu_dma_tag = { 271 NULL, /* cookie */ 272 sparc_vme_iommu_dmamap_create, 273 _bus_dmamap_destroy, 274 sparc_vme_iommu_dmamap_load, 275 _bus_dmamap_load_mbuf, 276 _bus_dmamap_load_uio, 277 _bus_dmamap_load_raw, 278 sparc_vme_iommu_dmamap_unload, 279 sparc_vme_iommu_dmamap_sync, 280 281 _bus_dmamem_alloc, 282 _bus_dmamem_free, 283 sparc_vme_dmamem_map, 284 _bus_dmamem_unmap, 285 _bus_dmamem_mmap 286 }; 287 #endif 288 289 290 int 291 vmematch_mainbus(parent, cf, aux) 292 struct device *parent; 293 struct cfdata *cf; 294 void *aux; 295 { 296 struct mainbus_attach_args *ma = aux; 297 298 if (!CPU_ISSUN4) 299 return (0); 300 301 return (strcmp("vme", ma->ma_name) == 0); 302 } 303 304 int 305 vmematch_iommu(parent, cf, aux) 306 struct device *parent; 307 struct cfdata *cf; 308 void *aux; 309 { 310 struct iommu_attach_args *ia = aux; 311 312 return (strcmp("vme", ia->iom_name) == 0); 313 } 314 315 316 void 317 vmeattach_mainbus(parent, self, aux) 318 struct device *parent, *self; 319 void *aux; 320 { 321 #if defined(SUN4) 322 struct mainbus_attach_args *ma = aux; 323 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 324 struct vmebus_attach_args vba; 325 326 if (self->dv_unit > 0) { 327 printf(" unsupported\n"); 328 return; 329 } 330 331 sc->sc_bustag = ma->ma_bustag; 332 sc->sc_dmatag = ma->ma_dmatag; 333 334 /* VME interrupt entry point */ 335 sc->sc_vmeintr = vmeintr4; 336 337 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 338 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 339 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 340 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 341 342 #if 0 343 sparc_vme_bus_tag.parent = ma->ma_bustag; 344 vba.vba_bustag = &sparc_vme_bus_tag; 345 #endif 346 vba.va_vct = &sparc_vme_chipset_tag; 347 vba.va_bdt = &sparc_vme4_dma_tag; 348 vba.va_slaveconfig = 0; 349 350 /* Fall back to our own `range' construction */ 351 sc->sc_range = vmebus_translations; 352 sc->sc_nrange = 353 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 354 355 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 356 M_DEVBUF, 0, 0, EX_NOWAIT); 357 if (vme_dvmamap == NULL) 358 panic("vme: unable to allocate DVMA map"); 359 360 printf("\n"); 361 (void)config_found(self, &vba, 0); 362 363 #endif 364 return; 365 } 366 367 /* sun4m vmebus */ 368 void 369 vmeattach_iommu(parent, self, aux) 370 struct device *parent, *self; 371 void *aux; 372 { 373 #if defined(SUN4M) 374 struct sparcvme_softc *sc = (struct sparcvme_softc *)self; 375 struct iommu_attach_args *ia = aux; 376 struct vmebus_attach_args vba; 377 bus_space_handle_t bh; 378 int node; 379 int cline; 380 381 if (self->dv_unit > 0) { 382 printf(" unsupported\n"); 383 return; 384 } 385 386 sc->sc_bustag = ia->iom_bustag; 387 sc->sc_dmatag = ia->iom_dmatag; 388 389 /* VME interrupt entry point */ 390 sc->sc_vmeintr = vmeintr4m; 391 392 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 393 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct_iommu_dmamap_create; 394 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 395 /*XXX*/ sparc_vme_iommu_dma_tag._cookie = self; 396 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme_iommu_barrier; 397 398 #if 0 399 vba.vba_bustag = &sparc_vme_bus_tag; 400 #endif 401 vba.va_vct = &sparc_vme_chipset_tag; 402 vba.va_bdt = &sparc_vme_iommu_dma_tag; 403 vba.va_slaveconfig = 0; 404 405 node = ia->iom_node; 406 407 /* 408 * Map VME control space 409 */ 410 if (ia->iom_nreg < 2) { 411 printf("%s: only %d register sets\n", self->dv_xname, 412 ia->iom_nreg); 413 return; 414 } 415 416 if (bus_space_map(ia->iom_bustag, 417 (bus_addr_t) BUS_ADDR(ia->iom_reg[0].oa_space, 418 ia->iom_reg[0].oa_base), 419 (bus_size_t)ia->iom_reg[0].oa_size, 420 BUS_SPACE_MAP_LINEAR, 421 &bh) != 0) { 422 panic("%s: can't map vmebusreg", self->dv_xname); 423 } 424 sc->sc_reg = (struct vmebusreg *)bh; 425 426 if (bus_space_map(ia->iom_bustag, 427 (bus_addr_t) BUS_ADDR(ia->iom_reg[1].oa_space, 428 ia->iom_reg[1].oa_base), 429 (bus_size_t)ia->iom_reg[1].oa_size, 430 BUS_SPACE_MAP_LINEAR, 431 &bh) != 0) { 432 panic("%s: can't map vmebusvec", self->dv_xname); 433 } 434 sc->sc_vec = (struct vmebusvec *)bh; 435 436 /* 437 * Map VME IO cache tags and flush control. 438 */ 439 if (bus_space_map(ia->iom_bustag, 440 (bus_addr_t) BUS_ADDR( 441 ia->iom_reg[1].oa_space, 442 ia->iom_reg[1].oa_base + VME_IOC_TAGOFFSET), 443 VME_IOC_SIZE, 444 BUS_SPACE_MAP_LINEAR, 445 &bh) != 0) { 446 panic("%s: can't map IOC tags", self->dv_xname); 447 } 448 sc->sc_ioctags = (u_int32_t *)bh; 449 450 if (bus_space_map(ia->iom_bustag, 451 (bus_addr_t) BUS_ADDR( 452 ia->iom_reg[1].oa_space, 453 ia->iom_reg[1].oa_base + VME_IOC_FLUSHOFFSET), 454 VME_IOC_SIZE, 455 BUS_SPACE_MAP_LINEAR, 456 &bh) != 0) { 457 panic("%s: can't map IOC flush registers", self->dv_xname); 458 } 459 sc->sc_iocflush = (u_int32_t *)bh; 460 461 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 462 463 /* 464 * Get "range" property. 465 */ 466 if (prom_getprop(node, "ranges", sizeof(struct rom_range), 467 &sc->sc_nrange, &sc->sc_range) != 0) { 468 panic("%s: can't get ranges property", self->dv_xname); 469 } 470 471 sparcvme_sc = sc; 472 vmeerr_handler = sparc_vme_error; 473 474 /* 475 * Invalidate all IO-cache entries. 476 */ 477 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 478 sc->sc_ioctags[--cline] = 0; 479 } 480 481 /* Enable IO-cache */ 482 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 483 484 printf(": version 0x%x\n", 485 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 486 487 (void)config_found(self, &vba, 0); 488 #endif /* SUN4M */ 489 } 490 491 #if defined(SUN4M) 492 static int 493 sparc_vme_error() 494 { 495 struct sparcvme_softc *sc = sparcvme_sc; 496 u_int32_t afsr, afpa; 497 char bits[64]; 498 499 afsr = sc->sc_reg->vmebus_afsr; 500 afpa = sc->sc_reg->vmebus_afar; 501 printf("VME error:\n\tAFSR %s\n", 502 bitmask_snprintf(afsr, VMEBUS_AFSR_BITS, bits, sizeof(bits))); 503 printf("\taddress: 0x%x%x\n", afsr, afpa); 504 return (0); 505 } 506 #endif 507 508 int 509 vmebus_translate(sc, mod, addr, bap) 510 struct sparcvme_softc *sc; 511 vme_am_t mod; 512 vme_addr_t addr; 513 bus_addr_t *bap; 514 { 515 int i; 516 517 for (i = 0; i < sc->sc_nrange; i++) { 518 struct rom_range *rp = &sc->sc_range[i]; 519 520 if (rp->cspace != mod) 521 continue; 522 523 /* We've found the connection to the parent bus */ 524 *bap = BUS_ADDR(rp->pspace, rp->poffset + addr); 525 return (0); 526 } 527 return (ENOENT); 528 } 529 530 struct vmeprobe_myarg { 531 int (*cb) __P((void *, bus_space_tag_t, bus_space_handle_t)); 532 void *cbarg; 533 bus_space_tag_t tag; 534 int res; /* backwards */ 535 }; 536 537 static int vmeprobe_mycb __P((void *, void *)); 538 static int 539 vmeprobe_mycb(bh, arg) 540 void *bh, *arg; 541 { 542 struct vmeprobe_myarg *a = arg; 543 544 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 545 return (!a->res); 546 } 547 548 int 549 sparc_vme_probe(cookie, addr, len, mod, datasize, callback, arg) 550 void *cookie; 551 vme_addr_t addr; 552 vme_size_t len; 553 vme_am_t mod; 554 vme_datasize_t datasize; 555 int (*callback) __P((void *, bus_space_tag_t, bus_space_handle_t)); 556 void *arg; 557 { 558 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 559 bus_addr_t paddr; 560 bus_size_t size; 561 struct vmeprobe_myarg myarg; 562 int res, i; 563 564 if (vmebus_translate(sc, mod, addr, &paddr) != 0) 565 return (EINVAL); 566 567 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 568 569 if (callback) { 570 myarg.cb = callback; 571 myarg.cbarg = arg; 572 myarg.tag = sc->sc_bustag; 573 myarg.res = 0; 574 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 575 0, vmeprobe_mycb, &myarg); 576 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 577 } 578 579 for (i = 0; i < len / size; i++) { 580 myarg.res = 0; 581 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 582 0, 0, 0); 583 if (res == 0) 584 return (EIO); 585 paddr += size; 586 } 587 return (0); 588 } 589 590 int 591 sparc_vme_map(cookie, addr, size, mod, datasize, swap, tp, hp, rp) 592 void *cookie; 593 vme_addr_t addr; 594 vme_size_t size; 595 vme_am_t mod; 596 vme_datasize_t datasize; 597 vme_swap_t swap; 598 bus_space_tag_t *tp; 599 bus_space_handle_t *hp; 600 vme_mapresc_t *rp; 601 { 602 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 603 bus_addr_t paddr; 604 int error; 605 606 error = vmebus_translate(sc, mod, addr, &paddr); 607 if (error != 0) 608 return (error); 609 610 *tp = sc->sc_bustag; 611 return (bus_space_map(sc->sc_bustag, paddr, size, 0, hp)); 612 } 613 614 int 615 sparc_vme_mmap_cookie(addr, mod, hp) 616 vme_addr_t addr; 617 vme_am_t mod; 618 bus_space_handle_t *hp; 619 { 620 struct sparcvme_softc *sc = sparcvme_sc; 621 bus_addr_t paddr; 622 int error; 623 624 error = vmebus_translate(sc, mod, addr, &paddr); 625 if (error != 0) 626 return (error); 627 628 return (bus_space_mmap(sc->sc_bustag, paddr, 0, 629 0/*prot is ignored*/, 0)); 630 } 631 632 #if defined(SUN4M) 633 void 634 sparc_vme_iommu_barrier(t, h, offset, size, flags) 635 bus_space_tag_t t; 636 bus_space_handle_t h; 637 bus_size_t offset; 638 bus_size_t size; 639 int flags; 640 { 641 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 642 643 /* Read async fault status to flush write-buffers */ 644 (*(volatile int *)&vbp->vmebus_afsr); 645 } 646 #endif 647 648 649 650 /* 651 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 652 */ 653 static int vme_ipl_to_pil[] = { 654 0, 655 2, 656 3, 657 5, 658 7, 659 9, 660 11, 661 13 662 }; 663 664 665 /* 666 * All VME device interrupts go through vmeintr(). This function reads 667 * the VME vector from the bus, then dispatches the device interrupt 668 * handler. All handlers for devices that map to the same Processor 669 * Interrupt Level (according to the table above) are on a linked list 670 * of `sparc_vme_intr_handle' structures. The head of which is passed 671 * down as the argument to `vmeintr(void *arg)'. 672 */ 673 struct sparc_vme_intr_handle { 674 struct intrhand ih; 675 struct sparc_vme_intr_handle *next; 676 int vec; /* VME interrupt vector */ 677 int pri; /* VME interrupt priority */ 678 struct sparcvme_softc *sc;/*XXX*/ 679 }; 680 681 #if defined(SUN4) 682 int 683 vmeintr4(arg) 684 void *arg; 685 { 686 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 687 int level, vec; 688 int rv = 0; 689 690 level = (ihp->pri << 1) | 1; 691 692 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 693 694 if (vec == -1) { 695 #ifdef DEBUG 696 /* 697 * This seems to happen only with the i82586 based 698 * `ie1' boards. 699 */ 700 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 701 #endif 702 return (1); /* XXX - pretend we handled it, for now */ 703 } 704 705 for (; ihp; ihp = ihp->next) 706 if (ihp->vec == vec && ihp->ih.ih_fun) { 707 splx(ihp->ih.ih_classipl); 708 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 709 } 710 711 return (rv); 712 } 713 #endif 714 715 #if defined(SUN4M) 716 int 717 vmeintr4m(arg) 718 void *arg; 719 { 720 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 721 int level, vec; 722 int rv = 0; 723 724 level = (ihp->pri << 1) | 1; 725 726 #if 0 727 int pending; 728 729 /* Flush VME <=> Sbus write buffers */ 730 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 731 732 pending = *((int*)ICR_SI_PEND); 733 if ((pending & SINTR_VME(ihp->pri)) == 0) { 734 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 735 ihp->pri, pending); 736 return (0); 737 } 738 #endif 739 #if 0 740 /* Why gives this a bus timeout sometimes? */ 741 vec = ihp->sc->sc_vec->vmebusvec[level]; 742 #else 743 /* so, arrange to catch the fault... */ 744 { 745 extern struct user *proc0paddr; 746 extern int fkbyte __P((caddr_t, struct pcb *)); 747 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 748 struct pcb *xpcb; 749 u_long saveonfault; 750 int s; 751 752 s = splhigh(); 753 if (curlwp == NULL) 754 xpcb = (struct pcb *)proc0paddr; 755 else 756 xpcb = &curlwp->l_addr->u_pcb; 757 758 saveonfault = (u_long)xpcb->pcb_onfault; 759 vec = fkbyte(addr, xpcb); 760 xpcb->pcb_onfault = (caddr_t)saveonfault; 761 762 splx(s); 763 } 764 #endif 765 766 if (vec == -1) { 767 #ifdef DEBUG 768 /* 769 * This seems to happen only with the i82586 based 770 * `ie1' boards. 771 */ 772 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 773 printf(" ICR_SI_PEND=0x%x; VME AFSR=0x%x; VME AFAR=0x%x\n", 774 *((int*)ICR_SI_PEND), 775 ihp->sc->sc_reg->vmebus_afsr, 776 ihp->sc->sc_reg->vmebus_afar); 777 #endif 778 return (1); /* XXX - pretend we handled it, for now */ 779 } 780 781 for (; ihp; ihp = ihp->next) 782 if (ihp->vec == vec && ihp->ih.ih_fun) { 783 splx(ihp->ih.ih_classipl); 784 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 785 } 786 787 return (rv); 788 } 789 #endif 790 791 int 792 sparc_vme_intr_map(cookie, level, vec, ihp) 793 void *cookie; 794 int level; 795 int vec; 796 vme_intr_handle_t *ihp; 797 { 798 struct sparc_vme_intr_handle *ih; 799 800 ih = (vme_intr_handle_t) 801 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 802 ih->pri = level; 803 ih->vec = vec; 804 ih->sc = cookie;/*XXX*/ 805 *ihp = ih; 806 return (0); 807 } 808 809 const struct evcnt * 810 sparc_vme_intr_evcnt(cookie, vih) 811 void *cookie; 812 vme_intr_handle_t vih; 813 { 814 815 /* XXX for now, no evcnt parent reported */ 816 return NULL; 817 } 818 819 void * 820 sparc_vme_intr_establish(cookie, vih, level, func, arg) 821 void *cookie; 822 vme_intr_handle_t vih; 823 int level; 824 int (*func) __P((void *)); 825 void *arg; 826 { 827 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 828 struct sparc_vme_intr_handle *svih = 829 (struct sparc_vme_intr_handle *)vih; 830 struct intrhand *ih; 831 int pil; 832 833 /* Translate VME priority to processor IPL */ 834 pil = vme_ipl_to_pil[svih->pri]; 835 836 if (level < pil) 837 panic("vme_intr_establish: class lvl (%d) < pil (%d)\n", 838 level, pil); 839 840 svih->ih.ih_fun = func; 841 svih->ih.ih_arg = arg; 842 svih->ih.ih_classipl = level; /* note: used slightly differently 843 than in intr.c (no shift) */ 844 svih->next = NULL; 845 846 /* ensure the interrupt subsystem will call us at this level */ 847 for (ih = intrhand[pil]; ih != NULL; ih = ih->ih_next) 848 if (ih->ih_fun == sc->sc_vmeintr) 849 break; 850 851 if (ih == NULL) { 852 ih = (struct intrhand *) 853 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 854 if (ih == NULL) 855 panic("vme_addirq"); 856 bzero(ih, sizeof *ih); 857 ih->ih_fun = sc->sc_vmeintr; 858 ih->ih_arg = vih; 859 intr_establish(pil, 0, ih, NULL); 860 } else { 861 svih->next = (vme_intr_handle_t)ih->ih_arg; 862 ih->ih_arg = vih; 863 } 864 return (NULL); 865 } 866 867 void 868 sparc_vme_unmap(cookie, resc) 869 void * cookie; 870 vme_mapresc_t resc; 871 { 872 /* Not implemented */ 873 panic("sparc_vme_unmap"); 874 } 875 876 void 877 sparc_vme_intr_disestablish(cookie, a) 878 void *cookie; 879 void *a; 880 { 881 /* Not implemented */ 882 panic("sparc_vme_intr_disestablish"); 883 } 884 885 886 887 /* 888 * VME DMA functions. 889 */ 890 891 #if defined(SUN4) || defined(SUN4M) 892 static void 893 sparc_vct_dmamap_destroy(cookie, map) 894 void *cookie; 895 bus_dmamap_t map; 896 { 897 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 898 bus_dmamap_destroy(sc->sc_dmatag, map); 899 } 900 #endif 901 902 #if defined(SUN4) 903 static int 904 sparc_vct4_dmamap_create(cookie, size, am, datasize, swap, nsegments, maxsegsz, 905 boundary, flags, dmamp) 906 void *cookie; 907 vme_size_t size; 908 vme_am_t am; 909 vme_datasize_t datasize; 910 vme_swap_t swap; 911 int nsegments; 912 vme_size_t maxsegsz; 913 vme_addr_t boundary; 914 int flags; 915 bus_dmamap_t *dmamp; 916 { 917 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 918 919 /* Allocate a base map through parent bus ops */ 920 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 921 boundary, flags, dmamp)); 922 } 923 924 int 925 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 926 bus_dma_tag_t t; 927 bus_dmamap_t map; 928 void *buf; 929 bus_size_t buflen; 930 struct proc *p; 931 int flags; 932 { 933 bus_addr_t dva; 934 bus_size_t sgsize; 935 u_long ldva; 936 vaddr_t va, voff; 937 pmap_t pmap; 938 int pagesz = PAGE_SIZE; 939 int error; 940 941 cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 942 943 va = (vaddr_t)buf; 944 voff = va & (pagesz - 1); 945 va &= -pagesz; 946 947 /* 948 * Allocate an integral number of pages from DVMA space 949 * covering the passed buffer. 950 */ 951 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 952 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 953 map->_dm_boundary, 954 (flags & BUS_DMA_NOWAIT) == 0 955 ? EX_WAITOK 956 : EX_NOWAIT, 957 &ldva); 958 if (error != 0) 959 return (error); 960 dva = (bus_addr_t)ldva; 961 962 map->dm_mapsize = buflen; 963 map->dm_nsegs = 1; 964 /* Adjust DVMA address to VME view */ 965 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 966 map->dm_segs[0].ds_len = buflen; 967 map->dm_segs[0]._ds_sgsize = sgsize; 968 969 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 970 971 for (; sgsize != 0; ) { 972 paddr_t pa; 973 /* 974 * Get the physical address for this page. 975 */ 976 (void) pmap_extract(pmap, va, &pa); 977 978 #ifdef notyet 979 if (have_iocache) 980 pa |= PG_IOC; 981 #endif 982 pmap_enter(pmap_kernel(), dva, 983 pa | PMAP_NC, 984 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 985 986 dva += pagesz; 987 va += pagesz; 988 sgsize -= pagesz; 989 } 990 pmap_update(pmap_kernel()); 991 992 return (0); 993 } 994 995 void 996 sparc_vme4_dmamap_unload(t, map) 997 bus_dma_tag_t t; 998 bus_dmamap_t map; 999 { 1000 bus_dma_segment_t *segs = map->dm_segs; 1001 int nsegs = map->dm_nsegs; 1002 bus_addr_t dva; 1003 bus_size_t len; 1004 int i, s, error; 1005 1006 for (i = 0; i < nsegs; i++) { 1007 /* Go from VME to CPU view */ 1008 dva = segs[i].ds_addr + VME4_DVMA_BASE; 1009 dva &= -PAGE_SIZE; 1010 len = segs[i]._ds_sgsize; 1011 1012 /* Remove double-mapping in DVMA space */ 1013 pmap_remove(pmap_kernel(), dva, dva + len); 1014 1015 /* Release DVMA space */ 1016 s = splhigh(); 1017 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 1018 splx(s); 1019 if (error != 0) 1020 printf("warning: %ld of DVMA space lost\n", len); 1021 } 1022 pmap_update(pmap_kernel()); 1023 1024 /* Mark the mappings as invalid. */ 1025 map->dm_mapsize = 0; 1026 map->dm_nsegs = 0; 1027 } 1028 1029 void 1030 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 1031 bus_dma_tag_t t; 1032 bus_dmamap_t map; 1033 bus_addr_t offset; 1034 bus_size_t len; 1035 int ops; 1036 { 1037 1038 /* 1039 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 1040 * Currently the cache is flushed in bus_dma_load()... 1041 */ 1042 } 1043 #endif /* SUN4 */ 1044 1045 #if defined(SUN4M) 1046 static int 1047 sparc_vme_iommu_dmamap_create (t, size, nsegments, maxsegsz, 1048 boundary, flags, dmamp) 1049 bus_dma_tag_t t; 1050 bus_size_t size; 1051 int nsegments; 1052 bus_size_t maxsegsz; 1053 bus_size_t boundary; 1054 int flags; 1055 bus_dmamap_t *dmamp; 1056 { 1057 1058 printf("sparc_vme_dmamap_create: please use `vme_dmamap_create'\n"); 1059 return (EINVAL); 1060 } 1061 1062 static int 1063 sparc_vct_iommu_dmamap_create(cookie, size, am, datasize, swap, nsegments, 1064 maxsegsz, boundary, flags, dmamp) 1065 void *cookie; 1066 vme_size_t size; 1067 vme_am_t am; 1068 vme_datasize_t datasize; 1069 vme_swap_t swap; 1070 int nsegments; 1071 vme_size_t maxsegsz; 1072 vme_addr_t boundary; 1073 int flags; 1074 bus_dmamap_t *dmamp; 1075 { 1076 struct sparcvme_softc *sc = (struct sparcvme_softc *)cookie; 1077 bus_dmamap_t map; 1078 int error; 1079 1080 /* Allocate a base map through parent bus ops */ 1081 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 1082 boundary, flags, &map); 1083 if (error != 0) 1084 return (error); 1085 1086 /* 1087 * Each I/O cache line maps to a 8K section of VME DVMA space, so 1088 * we must ensure that DVMA alloctions are always 8K aligned. 1089 */ 1090 map->_dm_align = VME_IOC_PAGESZ; 1091 1092 /* Set map region based on Address Modifier */ 1093 switch ((am & VME_AM_ADRSIZEMASK)) { 1094 case VME_AM_A16: 1095 case VME_AM_A24: 1096 /* 1 MB of DVMA space */ 1097 map->_dm_ex_start = VME_IOMMU_DVMA_AM24_BASE; 1098 map->_dm_ex_end = VME_IOMMU_DVMA_AM24_END; 1099 break; 1100 case VME_AM_A32: 1101 /* 8 MB of DVMA space */ 1102 map->_dm_ex_start = VME_IOMMU_DVMA_AM32_BASE; 1103 map->_dm_ex_end = VME_IOMMU_DVMA_AM32_END; 1104 break; 1105 } 1106 1107 *dmamp = map; 1108 return (0); 1109 } 1110 1111 int 1112 sparc_vme_iommu_dmamap_load(t, map, buf, buflen, p, flags) 1113 bus_dma_tag_t t; 1114 bus_dmamap_t map; 1115 void *buf; 1116 bus_size_t buflen; 1117 struct proc *p; 1118 int flags; 1119 { 1120 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1121 volatile u_int32_t *ioctags; 1122 int error; 1123 1124 /* Round request to a multiple of the I/O cache size */ 1125 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 1126 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1127 if (error != 0) 1128 return (error); 1129 1130 /* Allocate I/O cache entries for this range */ 1131 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1132 while (buflen > 0) { 1133 *ioctags = VME_IOC_IC | VME_IOC_W; 1134 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1135 buflen -= VME_IOC_PAGESZ; 1136 } 1137 1138 /* 1139 * Adjust DVMA address to VME view. 1140 * Note: the DVMA base address is the same for all 1141 * VME address spaces. 1142 */ 1143 map->dm_segs[0].ds_addr -= VME_IOMMU_DVMA_BASE; 1144 return (0); 1145 } 1146 1147 1148 void 1149 sparc_vme_iommu_dmamap_unload(t, map) 1150 bus_dma_tag_t t; 1151 bus_dmamap_t map; 1152 { 1153 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1154 volatile u_int32_t *flushregs; 1155 int len; 1156 1157 /* Go from VME to CPU view */ 1158 map->dm_segs[0].ds_addr += VME_IOMMU_DVMA_BASE; 1159 1160 /* Flush VME I/O cache */ 1161 len = map->dm_segs[0]._ds_sgsize; 1162 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1163 while (len > 0) { 1164 *flushregs = 0; 1165 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1166 len -= VME_IOC_PAGESZ; 1167 } 1168 1169 /* 1170 * Start a read from `tag space' which will not complete until 1171 * all cache flushes have finished 1172 */ 1173 (*sc->sc_ioctags); 1174 1175 bus_dmamap_unload(sc->sc_dmatag, map); 1176 } 1177 1178 void 1179 sparc_vme_iommu_dmamap_sync(t, map, offset, len, ops) 1180 bus_dma_tag_t t; 1181 bus_dmamap_t map; 1182 bus_addr_t offset; 1183 bus_size_t len; 1184 int ops; 1185 { 1186 1187 /* 1188 * XXX Should perform cache flushes as necessary. 1189 */ 1190 } 1191 #endif /* SUN4M */ 1192 1193 #if defined(SUN4) || defined(SUN4M) 1194 int 1195 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 1196 bus_dma_tag_t t; 1197 bus_dma_segment_t *segs; 1198 int nsegs; 1199 size_t size; 1200 caddr_t *kvap; 1201 int flags; 1202 { 1203 struct sparcvme_softc *sc = (struct sparcvme_softc *)t->_cookie; 1204 1205 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1206 } 1207 #endif /* SUN4 || SUN4M */ 1208
Indexes created Tue Sep 23 22:09:46 GMT 2025