vme_machdep.c revision 1.70
1 /* $NetBSD: vme_machdep.c,v 1.70 2020/06/14 01:40:05 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: vme_machdep.c,v 1.70 2020/06/14 01:40:05 chs Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/extent.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/malloc.h> 40 #include <sys/errno.h> 41 42 #include <sys/proc.h> 43 #include <sys/syslog.h> 44 45 #include <uvm/uvm_extern.h> 46 47 #define _SPARC_BUS_DMA_PRIVATE 48 #include <sys/bus.h> 49 #include <sparc/sparc/iommuvar.h> 50 #include <machine/autoconf.h> 51 #include <machine/oldmon.h> 52 #include <machine/cpu.h> 53 #include <machine/ctlreg.h> 54 #include <machine/pcb.h> 55 56 #include <dev/vme/vmereg.h> 57 #include <dev/vme/vmevar.h> 58 59 #include <sparc/sparc/asm.h> 60 #include <sparc/sparc/vaddrs.h> 61 #include <sparc/sparc/cpuvar.h> 62 #include <sparc/dev/vmereg.h> 63 64 struct sparcvme_softc { 65 bus_space_tag_t sc_bustag; 66 bus_dma_tag_t sc_dmatag; 67 struct vmebusreg *sc_reg; /* VME control registers */ 68 struct vmebusvec *sc_vec; /* VME interrupt vector */ 69 struct rom_range *sc_range; /* ROM range property */ 70 int sc_nrange; 71 volatile uint32_t *sc_ioctags; /* VME IO-cache tag registers */ 72 volatile uint32_t *sc_iocflush;/* VME IO-cache flush registers */ 73 int (*sc_vmeintr)(void *); 74 }; 75 struct sparcvme_softc *sparcvme_sc;/*XXX*/ 76 77 /* autoconfiguration driver */ 78 static int vmematch_iommu(device_t, cfdata_t, void *); 79 static void vmeattach_iommu(device_t, device_t, void *); 80 static int vmematch_mainbus(device_t, cfdata_t, void *); 81 static void vmeattach_mainbus(device_t, device_t, void *); 82 #if defined(SUN4) 83 int vmeintr4(void *); 84 #endif 85 #if defined(SUN4M) 86 int vmeintr4m(void *); 87 static int sparc_vme_error(void); 88 #endif 89 90 91 static int sparc_vme_probe(void *, vme_addr_t, vme_size_t, 92 vme_am_t, vme_datasize_t, 93 int (*)(void *, 94 bus_space_tag_t, bus_space_handle_t), 95 void *); 96 static int sparc_vme_map(void *, vme_addr_t, vme_size_t, vme_am_t, 97 vme_datasize_t, vme_swap_t, 98 bus_space_tag_t *, bus_space_handle_t *, 99 vme_mapresc_t *); 100 static void sparc_vme_unmap(void *, vme_mapresc_t); 101 static int sparc_vme_intr_map(void *, int, int, vme_intr_handle_t *); 102 static const struct evcnt *sparc_vme_intr_evcnt(void *, vme_intr_handle_t); 103 static void * sparc_vme_intr_establish(void *, vme_intr_handle_t, int, 104 int (*)(void *), void *); 105 static void sparc_vme_intr_disestablish(void *, void *); 106 107 static int vmebus_translate(struct sparcvme_softc *, vme_am_t, 108 vme_addr_t, bus_addr_t *); 109 #ifdef notyet 110 #if defined(SUN4M) 111 static void sparc_vme_iommu_barrier(bus_space_tag_t, bus_space_handle_t, 112 bus_size_t, bus_size_t, int); 113 114 #endif /* SUN4M */ 115 #endif 116 117 /* 118 * DMA functions. 119 */ 120 #if defined(SUN4) || defined(SUN4M) 121 static void sparc_vct_dmamap_destroy(void *, bus_dmamap_t); 122 #endif 123 124 #if defined(SUN4) 125 static int sparc_vct4_dmamap_create(void *, vme_size_t, vme_am_t, 126 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 127 int, bus_dmamap_t *); 128 static int sparc_vme4_dmamap_load(bus_dma_tag_t, bus_dmamap_t, void *, 129 bus_size_t, struct proc *, int); 130 static void sparc_vme4_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 131 static void sparc_vme4_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, 132 bus_addr_t, bus_size_t, int); 133 #endif /* SUN4 */ 134 135 #if defined(SUN4M) 136 static int sparc_vct_iommu_dmamap_create(void *, vme_size_t, vme_am_t, 137 vme_datasize_t, vme_swap_t, int, vme_size_t, vme_addr_t, 138 int, bus_dmamap_t *); 139 static int sparc_vme_iommu_dmamap_create(bus_dma_tag_t, bus_size_t, 140 int, bus_size_t, bus_size_t, int, bus_dmamap_t *); 141 142 static int sparc_vme_iommu_dmamap_load(bus_dma_tag_t, bus_dmamap_t, 143 void *, bus_size_t, struct proc *, int); 144 static void sparc_vme_iommu_dmamap_unload(bus_dma_tag_t, bus_dmamap_t); 145 static void sparc_vme_iommu_dmamap_sync(bus_dma_tag_t, bus_dmamap_t, 146 bus_addr_t, bus_size_t, int); 147 #endif /* SUN4M */ 148 149 #if defined(SUN4) || defined(SUN4M) 150 static int sparc_vme_dmamem_map(bus_dma_tag_t, bus_dma_segment_t *, 151 int, size_t, void **, int); 152 #endif 153 154 #if 0 155 static void sparc_vme_dmamap_destroy(bus_dma_tag_t, bus_dmamap_t); 156 static void sparc_vme_dmamem_unmap(bus_dma_tag_t, void *, size_t); 157 static paddr_t sparc_vme_dmamem_mmap(bus_dma_tag_t, 158 bus_dma_segment_t *, int, off_t, int, int); 159 #endif 160 161 int sparc_vme_mmap_cookie(vme_addr_t, vme_am_t, bus_space_handle_t *); 162 163 CFATTACH_DECL_NEW(vme_mainbus, sizeof(struct sparcvme_softc), 164 vmematch_mainbus, vmeattach_mainbus, NULL, NULL); 165 166 CFATTACH_DECL_NEW(vme_iommu, sizeof(struct sparcvme_softc), 167 vmematch_iommu, vmeattach_iommu, NULL, NULL); 168 169 static int vme_attached; 170 171 extern int (*vmeerr_handler)(void); 172 173 #define VMEMOD_D32 0x40 /* ??? */ 174 175 /* If the PROM does not provide the `ranges' property, we make up our own */ 176 struct rom_range vmebus_translations[] = { 177 #define _DS (VME_AM_MBO | VME_AM_SUPER | VME_AM_DATA) 178 { VME_AM_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 179 { VME_AM_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 180 { VME_AM_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 181 { VME_AM_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 182 { VME_AM_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 183 { VME_AM_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 184 #undef _DS 185 }; 186 187 /* 188 * The VME bus logic on sun4 machines maps DMA requests in the first MB 189 * of VME space to the last MB of DVMA space. `vme_dvmamap' is used 190 * for DVMA space allocations. The DMA addresses returned by 191 * bus_dmamap_load*() must be relocated by -VME4_DVMA_BASE. 192 */ 193 struct extent *vme_dvmamap; 194 195 /* 196 * The VME hardware on the sun4m IOMMU maps the first 8MB of 32-bit 197 * VME space to the last 8MB of DVMA space and the first 1MB of 198 * 24-bit VME space to the first 1MB of the last 8MB of DVMA space 199 * (thus 24-bit VME space overlaps the first 1MB of of 32-bit space). 200 * The following constants define subregions in the IOMMU DVMA map 201 * for VME DVMA allocations. The DMA addresses returned by 202 * bus_dmamap_load*() must be relocated by -VME_IOMMU_DVMA_BASE. 203 */ 204 #define VME_IOMMU_DVMA_BASE 0xff800000 205 #define VME_IOMMU_DVMA_AM24_BASE VME_IOMMU_DVMA_BASE 206 #define VME_IOMMU_DVMA_AM24_END 0xff900000 207 #define VME_IOMMU_DVMA_AM32_BASE VME_IOMMU_DVMA_BASE 208 #define VME_IOMMU_DVMA_AM32_END IOMMU_DVMA_END 209 210 struct vme_chipset_tag sparc_vme_chipset_tag = { 211 NULL, 212 sparc_vme_map, 213 sparc_vme_unmap, 214 sparc_vme_probe, 215 sparc_vme_intr_map, 216 sparc_vme_intr_evcnt, 217 sparc_vme_intr_establish, 218 sparc_vme_intr_disestablish, 219 0, 0, 0 /* bus specific DMA stuff */ 220 }; 221 222 223 #if defined(SUN4) 224 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 225 NULL, /* cookie */ 226 _bus_dmamap_create, 227 _bus_dmamap_destroy, 228 sparc_vme4_dmamap_load, 229 _bus_dmamap_load_mbuf, 230 _bus_dmamap_load_uio, 231 _bus_dmamap_load_raw, 232 sparc_vme4_dmamap_unload, 233 sparc_vme4_dmamap_sync, 234 235 _bus_dmamem_alloc, 236 _bus_dmamem_free, 237 sparc_vme_dmamem_map, 238 _bus_dmamem_unmap, 239 _bus_dmamem_mmap 240 }; 241 #endif 242 243 #if defined(SUN4M) 244 struct sparc_bus_dma_tag sparc_vme_iommu_dma_tag = { 245 NULL, /* cookie */ 246 sparc_vme_iommu_dmamap_create, 247 _bus_dmamap_destroy, 248 sparc_vme_iommu_dmamap_load, 249 _bus_dmamap_load_mbuf, 250 _bus_dmamap_load_uio, 251 _bus_dmamap_load_raw, 252 sparc_vme_iommu_dmamap_unload, 253 sparc_vme_iommu_dmamap_sync, 254 255 _bus_dmamem_alloc, 256 _bus_dmamem_free, 257 sparc_vme_dmamem_map, 258 _bus_dmamem_unmap, 259 _bus_dmamem_mmap 260 }; 261 #endif 262 263 264 static int 265 vmematch_mainbus(device_t parent, cfdata_t cf, void *aux) 266 { 267 struct mainbus_attach_args *ma = aux; 268 269 if (!CPU_ISSUN4 || vme_attached) 270 return (0); 271 272 return (strcmp("vme", ma->ma_name) == 0); 273 } 274 275 static int 276 vmematch_iommu(device_t parent, cfdata_t cf, void *aux) 277 { 278 struct iommu_attach_args *ia = aux; 279 280 if (vme_attached) 281 return 0; 282 283 return (strcmp("vme", ia->iom_name) == 0); 284 } 285 286 287 static void 288 vmeattach_mainbus(device_t parent, device_t self, void *aux) 289 { 290 #if defined(SUN4) 291 struct mainbus_attach_args *ma = aux; 292 struct sparcvme_softc *sc = device_private(self); 293 struct vmebus_attach_args vba; 294 295 vme_attached = 1; 296 297 sc->sc_bustag = ma->ma_bustag; 298 sc->sc_dmatag = ma->ma_dmatag; 299 300 /* VME interrupt entry point */ 301 sc->sc_vmeintr = vmeintr4; 302 303 /*XXX*/ sparc_vme_chipset_tag.cookie = sc; 304 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct4_dmamap_create; 305 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 306 /*XXX*/ sparc_vme4_dma_tag._cookie = sc; 307 308 vba.va_vct = &sparc_vme_chipset_tag; 309 vba.va_bdt = &sparc_vme4_dma_tag; 310 vba.va_slaveconfig = 0; 311 312 /* Fall back to our own `range' construction */ 313 sc->sc_range = vmebus_translations; 314 sc->sc_nrange = 315 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 316 317 vme_dvmamap = extent_create("vmedvma", VME4_DVMA_BASE, VME4_DVMA_END, 318 0, 0, EX_WAITOK); 319 320 printf("\n"); 321 (void)config_found(self, &vba, 0); 322 323 #endif /* SUN4 */ 324 return; 325 } 326 327 /* sun4m vmebus */ 328 static void 329 vmeattach_iommu(device_t parent, device_t self, void *aux) 330 { 331 #if defined(SUN4M) 332 struct sparcvme_softc *sc = device_private(self); 333 struct iommu_attach_args *ia = aux; 334 struct vmebus_attach_args vba; 335 bus_space_handle_t bh; 336 int node; 337 int cline; 338 339 sc->sc_bustag = ia->iom_bustag; 340 sc->sc_dmatag = ia->iom_dmatag; 341 342 /* VME interrupt entry point */ 343 sc->sc_vmeintr = vmeintr4m; 344 345 /*XXX*/ sparc_vme_chipset_tag.cookie = sc; 346 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_create = sparc_vct_iommu_dmamap_create; 347 /*XXX*/ sparc_vme_chipset_tag.vct_dmamap_destroy = sparc_vct_dmamap_destroy; 348 /*XXX*/ sparc_vme_iommu_dma_tag._cookie = sc; 349 350 vba.va_vct = &sparc_vme_chipset_tag; 351 vba.va_bdt = &sparc_vme_iommu_dma_tag; 352 vba.va_slaveconfig = 0; 353 354 node = ia->iom_node; 355 356 /* 357 * Map VME control space 358 */ 359 if (ia->iom_nreg < 2) { 360 printf("%s: only %d register sets\n", device_xname(self), 361 ia->iom_nreg); 362 return; 363 } 364 365 if (bus_space_map(ia->iom_bustag, 366 (bus_addr_t) BUS_ADDR(ia->iom_reg[0].oa_space, 367 ia->iom_reg[0].oa_base), 368 (bus_size_t)ia->iom_reg[0].oa_size, 369 BUS_SPACE_MAP_LINEAR, 370 &bh) != 0) { 371 panic("%s: can't map vmebusreg", device_xname(self)); 372 } 373 sc->sc_reg = (struct vmebusreg *)bh; 374 375 if (bus_space_map(ia->iom_bustag, 376 (bus_addr_t) BUS_ADDR(ia->iom_reg[1].oa_space, 377 ia->iom_reg[1].oa_base), 378 (bus_size_t)ia->iom_reg[1].oa_size, 379 BUS_SPACE_MAP_LINEAR, 380 &bh) != 0) { 381 panic("%s: can't map vmebusvec", device_xname(self)); 382 } 383 sc->sc_vec = (struct vmebusvec *)bh; 384 385 /* 386 * Map VME IO cache tags and flush control. 387 */ 388 if (bus_space_map(ia->iom_bustag, 389 (bus_addr_t) BUS_ADDR( 390 ia->iom_reg[1].oa_space, 391 ia->iom_reg[1].oa_base + VME_IOC_TAGOFFSET), 392 VME_IOC_SIZE, 393 BUS_SPACE_MAP_LINEAR, 394 &bh) != 0) { 395 panic("%s: can't map IOC tags", device_xname(self)); 396 } 397 sc->sc_ioctags = (uint32_t *)bh; 398 399 if (bus_space_map(ia->iom_bustag, 400 (bus_addr_t) BUS_ADDR( 401 ia->iom_reg[1].oa_space, 402 ia->iom_reg[1].oa_base + VME_IOC_FLUSHOFFSET), 403 VME_IOC_SIZE, 404 BUS_SPACE_MAP_LINEAR, 405 &bh) != 0) { 406 panic("%s: can't map IOC flush registers", device_xname(self)); 407 } 408 sc->sc_iocflush = (uint32_t *)bh; 409 410 /* 411 * Get "range" property. 412 */ 413 if (prom_getprop(node, "ranges", sizeof(struct rom_range), 414 &sc->sc_nrange, &sc->sc_range) != 0) { 415 panic("%s: can't get ranges property", device_xname(self)); 416 } 417 418 sparcvme_sc = sc; 419 vmeerr_handler = sparc_vme_error; 420 421 /* 422 * Invalidate all IO-cache entries. 423 */ 424 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 425 sc->sc_ioctags[--cline] = 0; 426 } 427 428 /* Enable IO-cache */ 429 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 430 431 printf(": version 0x%x\n", 432 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 433 434 (void)config_found(self, &vba, 0); 435 #endif /* SUN4M */ 436 } 437 438 #if defined(SUN4M) 439 static int 440 sparc_vme_error(void) 441 { 442 struct sparcvme_softc *sc = sparcvme_sc; 443 uint32_t afsr, afpa; 444 char bits[64]; 445 446 afsr = sc->sc_reg->vmebus_afsr; 447 afpa = sc->sc_reg->vmebus_afar; 448 snprintb(bits, sizeof(bits), VMEBUS_AFSR_BITS, afsr); 449 printf("VME error:\n\tAFSR %s\n", bits); 450 printf("\taddress: 0x%x%x\n", afsr, afpa); 451 return (0); 452 } 453 #endif 454 455 static int 456 vmebus_translate(struct sparcvme_softc *sc, vme_am_t mod, vme_addr_t addr, 457 bus_addr_t *bap) 458 { 459 int i; 460 461 for (i = 0; i < sc->sc_nrange; i++) { 462 struct rom_range *rp = &sc->sc_range[i]; 463 464 if (rp->cspace != mod) 465 continue; 466 467 /* We've found the connection to the parent bus */ 468 *bap = BUS_ADDR(rp->pspace, rp->poffset + addr); 469 return (0); 470 } 471 return (ENOENT); 472 } 473 474 struct vmeprobe_myarg { 475 int (*cb)(void *, bus_space_tag_t, bus_space_handle_t); 476 void *cbarg; 477 bus_space_tag_t tag; 478 int res; /* backwards */ 479 }; 480 481 static int vmeprobe_mycb(void *, void *); 482 483 static int 484 vmeprobe_mycb(void *bh, void *arg) 485 { 486 struct vmeprobe_myarg *a = arg; 487 488 a->res = (*a->cb)(a->cbarg, a->tag, (bus_space_handle_t)bh); 489 return (!a->res); 490 } 491 492 static int 493 sparc_vme_probe(void *cookie, vme_addr_t addr, vme_size_t len, vme_am_t mod, 494 vme_datasize_t datasize, 495 int (*callback)(void *, bus_space_tag_t, bus_space_handle_t), 496 void *arg) 497 { 498 struct sparcvme_softc *sc = cookie; 499 bus_addr_t paddr; 500 bus_size_t size; 501 struct vmeprobe_myarg myarg; 502 int res, i; 503 504 if (vmebus_translate(sc, mod, addr, &paddr) != 0) 505 return (EINVAL); 506 507 size = (datasize == VME_D8 ? 1 : (datasize == VME_D16 ? 2 : 4)); 508 509 if (callback) { 510 myarg.cb = callback; 511 myarg.cbarg = arg; 512 myarg.tag = sc->sc_bustag; 513 myarg.res = 0; 514 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 515 0, vmeprobe_mycb, &myarg); 516 return (res ? 0 : (myarg.res ? myarg.res : EIO)); 517 } 518 519 for (i = 0; i < len / size; i++) { 520 myarg.res = 0; 521 res = bus_space_probe(sc->sc_bustag, paddr, size, 0, 522 0, 0, 0); 523 if (res == 0) 524 return (EIO); 525 paddr += size; 526 } 527 return (0); 528 } 529 530 static int 531 sparc_vme_map(void *cookie, vme_addr_t addr, vme_size_t size, vme_am_t mod, 532 vme_datasize_t datasize, vme_swap_t swap, 533 bus_space_tag_t *tp, bus_space_handle_t *hp, vme_mapresc_t *rp) 534 { 535 struct sparcvme_softc *sc = cookie; 536 bus_addr_t paddr; 537 int error; 538 539 error = vmebus_translate(sc, mod, addr, &paddr); 540 if (error != 0) 541 return (error); 542 543 *tp = sc->sc_bustag; 544 return (bus_space_map(sc->sc_bustag, paddr, size, 0, hp)); 545 } 546 547 int 548 sparc_vme_mmap_cookie(vme_addr_t addr, vme_am_t mod, bus_space_handle_t *hp) 549 { 550 struct sparcvme_softc *sc = sparcvme_sc; 551 bus_addr_t paddr; 552 int error; 553 554 error = vmebus_translate(sc, mod, addr, &paddr); 555 if (error != 0) 556 return (error); 557 558 return (bus_space_mmap(sc->sc_bustag, paddr, 0, 559 0/*prot is ignored*/, 0)); 560 } 561 562 #ifdef notyet 563 #if defined(SUN4M) 564 static void 565 sparc_vme_iommu_barrier(bus_space_tag_t t, bus_space_handle_t h, 566 bus_size_t offset, bus_size_t size. 567 int flags) 568 { 569 struct vmebusreg *vbp = t->cookie; 570 571 /* Read async fault status to flush write-buffers */ 572 (*(volatile int *)&vbp->vmebus_afsr); 573 } 574 #endif /* SUN4M */ 575 #endif 576 577 578 579 /* 580 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 581 */ 582 static int vme_ipl_to_pil[] = { 583 0, 584 2, 585 3, 586 5, 587 7, 588 9, 589 11, 590 13 591 }; 592 593 594 /* 595 * All VME device interrupts go through vmeintr(). This function reads 596 * the VME vector from the bus, then dispatches the device interrupt 597 * handler. All handlers for devices that map to the same Processor 598 * Interrupt Level (according to the table above) are on a linked list 599 * of `sparc_vme_intr_handle' structures. The head of which is passed 600 * down as the argument to `vmeintr(void *arg)'. 601 */ 602 struct sparc_vme_intr_handle { 603 struct intrhand ih; 604 struct sparc_vme_intr_handle *next; 605 int vec; /* VME interrupt vector */ 606 int pri; /* VME interrupt priority */ 607 struct sparcvme_softc *sc;/*XXX*/ 608 }; 609 610 #if defined(SUN4) 611 int 612 vmeintr4(void *arg) 613 { 614 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 615 int level, vec; 616 int rv = 0; 617 618 level = (ihp->pri << 1) | 1; 619 620 vec = ldcontrolb((void *)(AC_VMEINTVEC | level)); 621 622 if (vec == -1) { 623 #ifdef DEBUG 624 /* 625 * This seems to happen only with the i82586 based 626 * `ie1' boards. 627 */ 628 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 629 #endif 630 return (1); /* XXX - pretend we handled it, for now */ 631 } 632 633 for (; ihp; ihp = ihp->next) 634 if (ihp->vec == vec && ihp->ih.ih_fun) { 635 splx(ihp->ih.ih_classipl); 636 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 637 } 638 639 return (rv); 640 } 641 #endif 642 643 #if defined(SUN4M) 644 int 645 vmeintr4m(void *arg) 646 { 647 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 648 int level, vec; 649 int rv = 0; 650 651 level = (ihp->pri << 1) | 1; 652 653 #if 0 654 int pending; 655 656 /* Flush VME <=> Sbus write buffers */ 657 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 658 659 pending = *((int*)ICR_SI_PEND); 660 if ((pending & SINTR_VME(ihp->pri)) == 0) { 661 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 662 ihp->pri, pending); 663 return (0); 664 } 665 #endif 666 #if 0 667 /* Why gives this a bus timeout sometimes? */ 668 vec = ihp->sc->sc_vec->vmebusvec[level]; 669 #else 670 /* so, arrange to catch the fault... */ 671 { 672 extern int fkbyte(volatile char *, struct pcb *); 673 volatile char *addr = &ihp->sc->sc_vec->vmebusvec[level]; 674 struct pcb *xpcb; 675 void *saveonfault; 676 int s; 677 678 s = splhigh(); 679 680 xpcb = lwp_getpcb(curlwp); 681 saveonfault = xpcb->pcb_onfault; 682 vec = fkbyte(addr, xpcb); 683 xpcb->pcb_onfault = saveonfault; 684 685 splx(s); 686 } 687 #endif 688 689 if (vec == -1) { 690 #ifdef DEBUG 691 /* 692 * This seems to happen only with the i82586 based 693 * `ie1' boards. 694 */ 695 printf("vme: spurious interrupt at VME level %d\n", ihp->pri); 696 printf(" ICR_SI_PEND=0x%x; VME AFSR=0x%x; VME AFAR=0x%x\n", 697 *((int*)ICR_SI_PEND), 698 ihp->sc->sc_reg->vmebus_afsr, 699 ihp->sc->sc_reg->vmebus_afar); 700 #endif 701 return (1); /* XXX - pretend we handled it, for now */ 702 } 703 704 for (; ihp; ihp = ihp->next) 705 if (ihp->vec == vec && ihp->ih.ih_fun) { 706 splx(ihp->ih.ih_classipl); 707 rv |= (ihp->ih.ih_fun)(ihp->ih.ih_arg); 708 } 709 710 return (rv); 711 } 712 #endif /* SUN4M */ 713 714 static int 715 sparc_vme_intr_map(void *cookie, int level, int vec, 716 vme_intr_handle_t *ihp) 717 { 718 struct sparc_vme_intr_handle *ih; 719 720 ih = malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_WAITOK); 721 ih->pri = level; 722 ih->vec = vec; 723 ih->sc = cookie;/*XXX*/ 724 *ihp = ih; 725 return (0); 726 } 727 728 static const struct evcnt * 729 sparc_vme_intr_evcnt(void *cookie, vme_intr_handle_t vih) 730 { 731 732 /* XXX for now, no evcnt parent reported */ 733 return NULL; 734 } 735 736 static void * 737 sparc_vme_intr_establish(void *cookie, vme_intr_handle_t vih, int level, 738 int (*func)(void *), void *arg) 739 { 740 struct sparcvme_softc *sc = cookie; 741 struct sparc_vme_intr_handle *svih = 742 (struct sparc_vme_intr_handle *)vih; 743 struct intrhand *ih; 744 int pil; 745 746 /* Translate VME priority to processor IPL */ 747 pil = vme_ipl_to_pil[svih->pri]; 748 749 if (level < pil) 750 panic("vme_intr_establish: class lvl (%d) < pil (%d)\n", 751 level, pil); 752 753 svih->ih.ih_fun = func; 754 svih->ih.ih_arg = arg; 755 svih->ih.ih_classipl = level; /* note: used slightly differently 756 than in intr.c (no shift) */ 757 svih->next = NULL; 758 759 /* ensure the interrupt subsystem will call us at this level */ 760 for (ih = intrhand[pil]; ih != NULL; ih = ih->ih_next) 761 if (ih->ih_fun == sc->sc_vmeintr) 762 break; 763 764 if (ih == NULL) { 765 ih = malloc(sizeof(struct intrhand), M_DEVBUF, M_WAITOK|M_ZERO); 766 ih->ih_fun = sc->sc_vmeintr; 767 ih->ih_arg = vih; 768 intr_establish(pil, 0, ih, NULL, false); 769 } else { 770 svih->next = (vme_intr_handle_t)ih->ih_arg; 771 ih->ih_arg = vih; 772 } 773 return (NULL); 774 } 775 776 static void 777 sparc_vme_unmap(void *cookie, vme_mapresc_t resc) 778 { 779 780 /* Not implemented */ 781 panic("sparc_vme_unmap"); 782 } 783 784 static void 785 sparc_vme_intr_disestablish(void *cookie, void *a) 786 { 787 788 /* Not implemented */ 789 panic("sparc_vme_intr_disestablish"); 790 } 791 792 793 794 /* 795 * VME DMA functions. 796 */ 797 798 #if defined(SUN4) || defined(SUN4M) 799 static void 800 sparc_vct_dmamap_destroy(void *cookie, bus_dmamap_t map) 801 { 802 struct sparcvme_softc *sc = cookie; 803 804 bus_dmamap_destroy(sc->sc_dmatag, map); 805 } 806 #endif 807 808 #if defined(SUN4) 809 static int 810 sparc_vct4_dmamap_create(void *cookie, vme_size_t size, vme_am_t am, 811 vme_datasize_t datasize, vme_swap_t swap, 812 int nsegments, vme_size_t maxsegsz, 813 vme_addr_t boundary, int flags, 814 bus_dmamap_t *dmamp) 815 { 816 struct sparcvme_softc *sc = cookie; 817 818 /* Allocate a base map through parent bus ops */ 819 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 820 boundary, flags, dmamp)); 821 } 822 823 static int 824 sparc_vme4_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, 825 void *buf, bus_size_t buflen, 826 struct proc *p, int flags) 827 { 828 bus_addr_t dva; 829 bus_size_t sgsize; 830 u_long ldva; 831 vaddr_t va, voff; 832 pmap_t pmap; 833 int pagesz = PAGE_SIZE; 834 int error; 835 836 cache_flush(buf, buflen); /* XXX - move to bus_dma_sync */ 837 838 va = (vaddr_t)buf; 839 voff = va & (pagesz - 1); 840 va &= -pagesz; 841 842 /* 843 * Allocate an integral number of pages from DVMA space 844 * covering the passed buffer. 845 */ 846 sgsize = (buflen + voff + pagesz - 1) & -pagesz; 847 error = extent_alloc(vme_dvmamap, sgsize, pagesz, 848 map->_dm_boundary, 849 (flags & BUS_DMA_NOWAIT) == 0 850 ? EX_WAITOK 851 : EX_NOWAIT, 852 &ldva); 853 if (error != 0) 854 return (error); 855 dva = (bus_addr_t)ldva; 856 857 map->dm_mapsize = buflen; 858 map->dm_nsegs = 1; 859 /* Adjust DVMA address to VME view */ 860 map->dm_segs[0].ds_addr = dva + voff - VME4_DVMA_BASE; 861 map->dm_segs[0].ds_len = buflen; 862 map->dm_segs[0]._ds_sgsize = sgsize; 863 864 pmap = (p == NULL) ? pmap_kernel() : p->p_vmspace->vm_map.pmap; 865 866 for (; sgsize != 0; ) { 867 paddr_t pa; 868 /* 869 * Get the physical address for this page. 870 */ 871 (void) pmap_extract(pmap, va, &pa); 872 873 #ifdef notyet 874 if (have_iocache) 875 pa |= PG_IOC; 876 #endif 877 pmap_enter(pmap_kernel(), dva, 878 pa | PMAP_NC, 879 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 880 881 dva += pagesz; 882 va += pagesz; 883 sgsize -= pagesz; 884 } 885 pmap_update(pmap_kernel()); 886 887 return (0); 888 } 889 890 static void 891 sparc_vme4_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) 892 { 893 bus_dma_segment_t *segs = map->dm_segs; 894 int nsegs = map->dm_nsegs; 895 bus_addr_t dva; 896 bus_size_t len; 897 int i, s, error; 898 899 for (i = 0; i < nsegs; i++) { 900 /* Go from VME to CPU view */ 901 dva = segs[i].ds_addr + VME4_DVMA_BASE; 902 dva &= -PAGE_SIZE; 903 len = segs[i]._ds_sgsize; 904 905 /* Remove double-mapping in DVMA space */ 906 pmap_remove(pmap_kernel(), dva, dva + len); 907 908 /* Release DVMA space */ 909 s = splhigh(); 910 error = extent_free(vme_dvmamap, dva, len, EX_NOWAIT); 911 splx(s); 912 if (error != 0) 913 printf("warning: %ld of DVMA space lost\n", len); 914 } 915 pmap_update(pmap_kernel()); 916 917 /* Mark the mappings as invalid. */ 918 map->dm_mapsize = 0; 919 map->dm_nsegs = 0; 920 } 921 922 static void 923 sparc_vme4_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, 924 bus_addr_t offset, bus_size_t len, int ops) 925 { 926 927 /* 928 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 929 * Currently the cache is flushed in bus_dma_load()... 930 */ 931 } 932 #endif /* SUN4 */ 933 934 #if defined(SUN4M) 935 static int 936 sparc_vme_iommu_dmamap_create(bus_dma_tag_t t, bus_size_t size, 937 int nsegments, bus_size_t maxsegsz, 938 bus_size_t boundary, int flags, 939 bus_dmamap_t *dmamp) 940 { 941 942 printf("sparc_vme_dmamap_create: please use `vme_dmamap_create'\n"); 943 return (EINVAL); 944 } 945 946 static int 947 sparc_vct_iommu_dmamap_create(void *cookie, vme_size_t size, vme_am_t am, 948 vme_datasize_t datasize, vme_swap_t swap, 949 int nsegments, vme_size_t maxsegsz, 950 vme_addr_t boundary, int flags, 951 bus_dmamap_t *dmamp) 952 { 953 struct sparcvme_softc *sc = cookie; 954 bus_dmamap_t map; 955 int error; 956 957 /* Allocate a base map through parent bus ops */ 958 error = bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 959 boundary, flags, &map); 960 if (error != 0) 961 return (error); 962 963 /* 964 * Each I/O cache line maps to a 8K section of VME DVMA space, so 965 * we must ensure that DVMA alloctions are always 8K aligned. 966 */ 967 map->_dm_align = VME_IOC_PAGESZ; 968 969 /* Set map region based on Address Modifier */ 970 switch ((am & VME_AM_ADRSIZEMASK)) { 971 case VME_AM_A16: 972 case VME_AM_A24: 973 /* 1 MB of DVMA space */ 974 map->_dm_ex_start = VME_IOMMU_DVMA_AM24_BASE; 975 map->_dm_ex_end = VME_IOMMU_DVMA_AM24_END; 976 break; 977 case VME_AM_A32: 978 /* 8 MB of DVMA space */ 979 map->_dm_ex_start = VME_IOMMU_DVMA_AM32_BASE; 980 map->_dm_ex_end = VME_IOMMU_DVMA_AM32_END; 981 break; 982 } 983 984 *dmamp = map; 985 return (0); 986 } 987 988 static int 989 sparc_vme_iommu_dmamap_load(bus_dma_tag_t t, bus_dmamap_t map, 990 void *buf, bus_size_t buflen, 991 struct proc *p, int flags) 992 { 993 struct sparcvme_softc *sc = t->_cookie; 994 volatile uint32_t *ioctags; 995 int error; 996 997 /* Round request to a multiple of the I/O cache size */ 998 buflen = (buflen + VME_IOC_PAGESZ - 1) & -VME_IOC_PAGESZ; 999 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 1000 if (error != 0) 1001 return (error); 1002 1003 /* Allocate I/O cache entries for this range */ 1004 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1005 while (buflen > 0) { 1006 *ioctags = VME_IOC_IC | VME_IOC_W; 1007 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 1008 buflen -= VME_IOC_PAGESZ; 1009 } 1010 1011 /* 1012 * Adjust DVMA address to VME view. 1013 * Note: the DVMA base address is the same for all 1014 * VME address spaces. 1015 */ 1016 map->dm_segs[0].ds_addr -= VME_IOMMU_DVMA_BASE; 1017 return (0); 1018 } 1019 1020 1021 static void 1022 sparc_vme_iommu_dmamap_unload(bus_dma_tag_t t, bus_dmamap_t map) 1023 { 1024 struct sparcvme_softc *sc = t->_cookie; 1025 volatile uint32_t *flushregs; 1026 int len; 1027 1028 /* Go from VME to CPU view */ 1029 map->dm_segs[0].ds_addr += VME_IOMMU_DVMA_BASE; 1030 1031 /* Flush VME I/O cache */ 1032 len = map->dm_segs[0]._ds_sgsize; 1033 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 1034 while (len > 0) { 1035 *flushregs = 0; 1036 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 1037 len -= VME_IOC_PAGESZ; 1038 } 1039 1040 /* 1041 * Start a read from `tag space' which will not complete until 1042 * all cache flushes have finished 1043 */ 1044 (*sc->sc_ioctags); 1045 1046 bus_dmamap_unload(sc->sc_dmatag, map); 1047 } 1048 1049 static void 1050 sparc_vme_iommu_dmamap_sync(bus_dma_tag_t t, bus_dmamap_t map, 1051 bus_addr_t offset, bus_size_t len, int ops) 1052 { 1053 1054 /* 1055 * XXX Should perform cache flushes as necessary. 1056 */ 1057 } 1058 #endif /* SUN4M */ 1059 1060 #if defined(SUN4) || defined(SUN4M) 1061 static int 1062 sparc_vme_dmamem_map(bus_dma_tag_t t, bus_dma_segment_t *segs, int nsegs, 1063 size_t size, void **kvap, int flags) 1064 { 1065 struct sparcvme_softc *sc = t->_cookie; 1066 1067 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 1068 } 1069 #endif /* SUN4 || SUN4M */ 1070
Indexes created Tue Sep 23 21:09:50 GMT 2025