vme_machdep.c revision 1.9
1 /* $NetBSD: vme_machdep.c,v 1.9 1998/07/30 22:29:34 pk Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Paul Kranenburg. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 44 #include <sys/proc.h> 45 #include <sys/user.h> 46 #include <sys/syslog.h> 47 48 #include <vm/vm.h> 49 50 #define _SPARC_BUS_DMA_PRIVATE 51 #include <machine/bus.h> 52 #include <sparc/sparc/iommuvar.h> 53 #include <machine/autoconf.h> 54 #include <machine/pmap.h> 55 #include <machine/oldmon.h> 56 #include <machine/cpu.h> 57 #include <machine/ctlreg.h> 58 59 #include <dev/vme/vmevar.h> 60 61 #include <sparc/sparc/asm.h> 62 #include <sparc/sparc/vaddrs.h> 63 #include <sparc/sparc/cpuvar.h> 64 #include <sparc/dev/vmereg.h> 65 66 struct vmebus_softc { 67 struct device sc_dev; /* base device */ 68 bus_space_tag_t sc_bustag; 69 bus_dma_tag_t sc_dmatag; 70 struct vmebusreg *sc_reg; /* VME control registers */ 71 struct vmebusvec *sc_vec; /* VME interrupt vector */ 72 struct rom_range *sc_range; /* ROM range property */ 73 int sc_nrange; 74 volatile u_int32_t *sc_ioctags; /* VME IO-cache tag registers */ 75 volatile u_int32_t *sc_iocflush;/* VME IO-cache flush registers */ 76 int (*sc_vmeintr) __P((void *)); 77 struct bootpath *sc_bp; 78 }; 79 struct vmebus_softc *vmebus_sc;/*XXX*/ 80 81 /* autoconfiguration driver */ 82 static int vmematch_iommu __P((struct device *, struct cfdata *, void *)); 83 static void vmeattach_iommu __P((struct device *, struct device *, void *)); 84 static int vmematch_mainbus __P((struct device *, struct cfdata *, void *)); 85 static void vmeattach_mainbus __P((struct device *, struct device *, void *)); 86 #if defined(SUN4) 87 int vmeintr4 __P((void *)); 88 #endif 89 #if defined(SUN4M) 90 int vmeintr4m __P((void *)); 91 #endif 92 93 94 static int sparc_vme_probe __P((void *, bus_space_tag_t, vme_addr_t, 95 size_t, vme_size_t, vme_mod_t, 96 int (*) __P((void *, void *)), void *)); 97 static int sparc_vme_map __P((void *, vme_addr_t, vme_size_t, vme_mod_t, 98 bus_space_tag_t, bus_space_handle_t *)); 99 static void sparc_vme_unmap __P((void *)); 100 static int sparc_vme_mmap_cookie __P((void *, vme_addr_t, vme_mod_t, 101 bus_space_tag_t, bus_space_handle_t *)); 102 static int sparc_vme_intr_map __P((void *, int, int, vme_intr_handle_t *)); 103 static void * sparc_vme_intr_establish __P((void *, vme_intr_handle_t, 104 int (*) __P((void *)), void *)); 105 static void sparc_vme_intr_disestablish __P((void *, void *)); 106 107 static int vmebus_translate __P((struct vmebus_softc *, vme_mod_t, 108 vme_addr_t, bus_type_t *, bus_addr_t *)); 109 static void sparc_vme_bus_establish __P((void *, struct device *)); 110 #if defined(SUN4M) 111 static void sparc_vme4m_barrier __P(( bus_space_tag_t, bus_space_handle_t, 112 bus_size_t, bus_size_t, int)); 113 114 #endif 115 116 /* 117 * DMA functions. 118 */ 119 #if defined(SUN4) 120 static int sparc_vme4_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 121 bus_size_t, struct proc *, int)); 122 static void sparc_vme4_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 123 static void sparc_vme4_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 124 bus_addr_t, bus_size_t, int)); 125 126 static int sparc_vme4_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 127 bus_size_t, bus_size_t, bus_dma_segment_t *, 128 int, int *, int)); 129 static void sparc_vme4_dmamem_free __P((bus_dma_tag_t, 130 bus_dma_segment_t *, int)); 131 #endif 132 133 #if defined(SUN4M) 134 static int sparc_vme4m_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, 135 bus_size_t, bus_size_t, int, bus_dmamap_t *)); 136 137 static int sparc_vme4m_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 138 bus_size_t, struct proc *, int)); 139 static void sparc_vme4m_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 140 static void sparc_vme4m_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, 141 bus_addr_t, bus_size_t, int)); 142 143 static int sparc_vme4m_dmamem_alloc __P((bus_dma_tag_t, bus_size_t, 144 bus_size_t, bus_size_t, bus_dma_segment_t *, 145 int, int *, int)); 146 static void sparc_vme4m_dmamem_free __P((bus_dma_tag_t, 147 bus_dma_segment_t *, int)); 148 #endif 149 150 static int sparc_vme_dmamem_map __P((bus_dma_tag_t, bus_dma_segment_t *, 151 int, size_t, caddr_t *, int)); 152 #if 0 153 static void sparc_vme_dmamap_destroy __P((bus_dma_tag_t, bus_dmamap_t)); 154 static void sparc_vme_dmamem_unmap __P((bus_dma_tag_t, caddr_t, size_t)); 155 static int sparc_vme_dmamem_mmap __P((bus_dma_tag_t, 156 bus_dma_segment_t *, int, int, int, int)); 157 #endif 158 159 struct cfattach vme_mainbus_ca = { 160 sizeof(struct vmebus_softc), vmematch_mainbus, vmeattach_mainbus 161 }; 162 163 struct cfattach vme_iommu_ca = { 164 sizeof(struct vmebus_softc), vmematch_iommu, vmeattach_iommu 165 }; 166 167 /* If the PROM does not provide the `ranges' property, we make up our own */ 168 struct rom_range vmebus_translations[] = { 169 #define _DS (VMEMOD_D|VMEMOD_S) 170 { VMEMOD_A16|_DS, 0, PMAP_VME16, 0xffff0000, 0 }, 171 { VMEMOD_A24|_DS, 0, PMAP_VME16, 0xff000000, 0 }, 172 { VMEMOD_A32|_DS, 0, PMAP_VME16, 0x00000000, 0 }, 173 { VMEMOD_A16|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xffff0000, 0 }, 174 { VMEMOD_A24|VMEMOD_D32|_DS, 0, PMAP_VME32, 0xff000000, 0 }, 175 { VMEMOD_A32|VMEMOD_D32|_DS, 0, PMAP_VME32, 0x00000000, 0 } 176 #undef _DS 177 }; 178 179 struct sparc_bus_space_tag sparc_vme_bus_tag = { 180 NULL, /* cookie */ 181 NULL, /* parent bus tag */ 182 NULL, /* bus_map */ 183 NULL, /* bus_unmap */ 184 NULL, /* bus_subregion */ 185 NULL /* barrier */ 186 }; 187 188 struct vme_chipset_tag sparc_vme_chipset_tag = { 189 NULL, 190 sparc_vme_probe, 191 sparc_vme_map, 192 sparc_vme_unmap, 193 sparc_vme_mmap_cookie, 194 sparc_vme_intr_map, 195 sparc_vme_intr_establish, 196 sparc_vme_intr_disestablish, 197 sparc_vme_bus_establish 198 }; 199 200 201 #if defined(SUN4) 202 struct sparc_bus_dma_tag sparc_vme4_dma_tag = { 203 NULL, /* cookie */ 204 _bus_dmamap_create, 205 _bus_dmamap_destroy, 206 sparc_vme4_dmamap_load, 207 _bus_dmamap_load_mbuf, 208 _bus_dmamap_load_uio, 209 _bus_dmamap_load_raw, 210 sparc_vme4_dmamap_unload, 211 sparc_vme4_dmamap_sync, 212 213 sparc_vme4_dmamem_alloc, 214 sparc_vme4_dmamem_free, 215 sparc_vme_dmamem_map, 216 _bus_dmamem_unmap, 217 _bus_dmamem_mmap 218 }; 219 #endif 220 221 #if defined(SUN4M) 222 struct sparc_bus_dma_tag sparc_vme4m_dma_tag = { 223 NULL, /* cookie */ 224 sparc_vme4m_dmamap_create, 225 _bus_dmamap_destroy, 226 sparc_vme4m_dmamap_load, 227 _bus_dmamap_load_mbuf, 228 _bus_dmamap_load_uio, 229 _bus_dmamap_load_raw, 230 sparc_vme4m_dmamap_unload, 231 sparc_vme4m_dmamap_sync, 232 233 sparc_vme4m_dmamem_alloc, 234 sparc_vme4m_dmamem_free, 235 sparc_vme_dmamem_map, 236 _bus_dmamem_unmap, 237 _bus_dmamem_mmap 238 }; 239 #endif 240 241 242 void 243 sparc_vme_bus_establish(cookie, dev) 244 void *cookie; 245 struct device *dev; 246 { 247 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 248 struct bootpath *bp = sc->sc_bp; 249 char *name; 250 251 name = dev->dv_cfdata->cf_driver->cd_name; 252 #ifdef DEBUG 253 printf("sparc_vme_bus_establish: %s%d\n", name, dev->dv_unit); 254 #endif 255 if (bp != NULL && strcmp(bp->name, name) == 0 && 256 dev->dv_unit == bp->val[1]) { 257 bp->dev = dev; 258 #ifdef DEBUG 259 printf("sparc_vme_bus_establish: on the boot path\n"); 260 #endif 261 sc->sc_bp++; 262 bootpath_store(1, sc->sc_bp); 263 } 264 } 265 266 267 int 268 vmematch_mainbus(parent, cf, aux) 269 struct device *parent; 270 struct cfdata *cf; 271 void *aux; 272 { 273 274 if (!CPU_ISSUN4) 275 return (0); 276 277 return (1); 278 } 279 280 int 281 vmematch_iommu(parent, cf, aux) 282 struct device *parent; 283 struct cfdata *cf; 284 void *aux; 285 { 286 struct mainbus_attach_args *ma = aux; 287 288 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 289 } 290 291 292 void 293 vmeattach_mainbus(parent, self, aux) 294 struct device *parent, *self; 295 void *aux; 296 { 297 #if defined(SUN4) 298 struct mainbus_attach_args *ma = aux; 299 struct vmebus_softc *sc = (struct vmebus_softc *)self; 300 struct vme_busattach_args vba; 301 302 if (self->dv_unit > 0) { 303 printf(" unsupported\n"); 304 return; 305 } 306 307 sc->sc_bustag = ma->ma_bustag; 308 sc->sc_dmatag = ma->ma_dmatag; 309 310 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "vme") == 0) { 311 sc->sc_bp = ma->ma_bp + 1; 312 bootpath_store(1, sc->sc_bp); 313 } 314 315 /* VME interrupt entry point */ 316 sc->sc_vmeintr = vmeintr4; 317 318 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 319 /*XXX*/ sparc_vme4_dma_tag._cookie = self; 320 321 vba.vba_bustag = &sparc_vme_bus_tag; 322 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 323 vba.vba_dmatag = &sparc_vme4_dma_tag; 324 325 /* Fall back to our own `range' construction */ 326 sc->sc_range = vmebus_translations; 327 sc->sc_nrange = 328 sizeof(vmebus_translations)/sizeof(vmebus_translations[0]); 329 330 printf("\n"); 331 (void)config_search(vmesearch, self, &vba); 332 333 bootpath_store(1, NULL); 334 #endif 335 return; 336 } 337 338 /* sun4m vmebus */ 339 void 340 vmeattach_iommu(parent, self, aux) 341 struct device *parent, *self; 342 void *aux; 343 { 344 #if defined(SUN4M) 345 struct vmebus_softc *sc = (struct vmebus_softc *)self; 346 struct iommu_attach_args *ia = aux; 347 struct vme_busattach_args vba; 348 bus_space_handle_t bh; 349 struct rom_reg *rr; 350 int nreg; 351 int node; 352 int cline; 353 354 if (self->dv_unit > 0) { 355 printf(" unsupported\n"); 356 return; 357 } 358 359 sc->sc_bustag = ia->iom_bustag; 360 sc->sc_dmatag = ia->iom_dmatag; 361 362 /* VME interrupt entry point */ 363 sc->sc_vmeintr = vmeintr4m; 364 365 /*XXX*/ sparc_vme_chipset_tag.cookie = self; 366 /*XXX*/ sparc_vme4m_dma_tag._cookie = self; 367 sparc_vme_bus_tag.sparc_bus_barrier = sparc_vme4m_barrier; 368 369 vba.vba_bustag = &sparc_vme_bus_tag; 370 vba.vba_chipset_tag = &sparc_vme_chipset_tag; 371 vba.vba_dmatag = &sparc_vme4m_dma_tag; 372 373 node = ia->iom_node; 374 375 /* 376 * Map VME control space 377 */ 378 rr = NULL; 379 if (getpropA(node, "reg", sizeof(*rr), &nreg, (void**)&rr) != 0) { 380 printf("%s: can't get register property\n", self->dv_xname); 381 return; 382 } 383 if (nreg < 2) { 384 printf("%s: only %d register sets\n", self->dv_xname, nreg); 385 return; 386 } 387 388 if (bus_space_map2(ia->iom_bustag, 389 (bus_type_t)rr[0].rr_iospace, 390 (bus_addr_t)rr[0].rr_paddr, 391 (bus_size_t)rr[0].rr_len, 392 BUS_SPACE_MAP_LINEAR, 393 0, &bh) != 0) { 394 panic("%s: can't map vmebusreg", self->dv_xname); 395 } 396 sc->sc_reg = (struct vmebusreg *)bh; 397 398 if (bus_space_map2(ia->iom_bustag, 399 (bus_type_t)rr[1].rr_iospace, 400 (bus_addr_t)rr[1].rr_paddr, 401 (bus_size_t)rr[1].rr_len, 402 BUS_SPACE_MAP_LINEAR, 403 0, &bh) != 0) { 404 panic("%s: can't map vmebusvec", self->dv_xname); 405 } 406 sc->sc_vec = (struct vmebusvec *)bh; 407 408 /* 409 * Map VME IO cache tags and flush control. 410 */ 411 if (bus_space_map2(ia->iom_bustag, 412 (bus_type_t)rr[1].rr_iospace, 413 (bus_addr_t)rr[1].rr_paddr + VME_IOC_TAGOFFSET, 414 VME_IOC_SIZE, 415 BUS_SPACE_MAP_LINEAR, 416 0, &bh) != 0) { 417 panic("%s: can't map IOC tags", self->dv_xname); 418 } 419 sc->sc_ioctags = (u_int32_t *)bh; 420 421 if (bus_space_map2(ia->iom_bustag, 422 (bus_type_t)rr[1].rr_iospace, 423 (bus_addr_t)rr[1].rr_paddr + VME_IOC_FLUSHOFFSET, 424 VME_IOC_SIZE, 425 BUS_SPACE_MAP_LINEAR, 426 0, &bh) != 0) { 427 panic("%s: can't map IOC flush registers", self->dv_xname); 428 } 429 sc->sc_iocflush = (u_int32_t *)bh; 430 431 /*XXX*/ sparc_vme_bus_tag.cookie = sc->sc_reg; 432 433 /* 434 * Get "range" property. 435 */ 436 if (getpropA(node, "ranges", sizeof(struct rom_range), 437 &sc->sc_nrange, (void **)&sc->sc_range) != 0) { 438 panic("%s: can't get ranges property", self->dv_xname); 439 } 440 441 vmebus_sc = sc; 442 443 /* 444 * Invalidate all IO-cache entries. 445 */ 446 for (cline = VME_IOC_SIZE/VME_IOC_LINESZ; cline > 0;) { 447 sc->sc_ioctags[--cline] = 0; 448 } 449 450 /* Enable IO-cache */ 451 sc->sc_reg->vmebus_cr |= VMEBUS_CR_C; 452 453 printf(": version 0x%x\n", 454 sc->sc_reg->vmebus_cr & VMEBUS_CR_IMPL); 455 456 (void)config_search(vmesearch, self, &vba); 457 #endif 458 } 459 460 void sparc_vme_async_fault __P((void)); 461 void 462 sparc_vme_async_fault() 463 { 464 struct vmebus_softc *sc = vmebus_sc; 465 u_int32_t addr; 466 467 addr = sc->sc_reg->vmebus_afar; 468 printf("vme afsr: %x; addr %x\n", sc->sc_reg->vmebus_afsr, addr); 469 } 470 471 int 472 vmebus_translate(sc, mod, addr, btp, bap) 473 struct vmebus_softc *sc; 474 vme_mod_t mod; 475 vme_addr_t addr; 476 bus_type_t *btp; 477 bus_addr_t *bap; 478 { 479 int i; 480 481 for (i = 0; i < sc->sc_nrange; i++) { 482 483 if (sc->sc_range[i].cspace != mod) 484 continue; 485 486 /* We've found the connection to the parent bus */ 487 *bap = sc->sc_range[i].poffset + addr; 488 *btp = sc->sc_range[i].pspace; 489 return (0); 490 } 491 return (ENOENT); 492 } 493 494 int 495 sparc_vme_probe(cookie, tag, addr, offset, size, mod, callback, arg) 496 void *cookie; 497 bus_space_tag_t tag; 498 vme_addr_t addr; 499 size_t offset; 500 vme_size_t size; 501 int mod; 502 int (*callback) __P((void *, void *)); 503 void *arg; 504 { 505 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 506 bus_type_t iospace; 507 bus_addr_t paddr; 508 509 if (vmebus_translate(sc, mod, addr, &iospace, &paddr) != 0) 510 return (0); 511 512 return (bus_space_probe(sc->sc_bustag, iospace, paddr, size, offset, 513 0, callback, arg)); 514 } 515 516 int 517 sparc_vme_map(cookie, addr, size, mod, tag, hp) 518 void *cookie; 519 vme_addr_t addr; 520 vme_size_t size; 521 int mod; 522 bus_space_tag_t tag; 523 bus_space_handle_t *hp; 524 { 525 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 526 bus_type_t iospace; 527 bus_addr_t paddr; 528 int error; 529 530 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 531 if (error != 0) 532 return (error); 533 534 return (bus_space_map2(sc->sc_bustag, iospace, paddr, size, 0, 0, hp)); 535 } 536 537 int 538 sparc_vme_mmap_cookie(cookie, addr, mod, tag, hp) 539 void *cookie; 540 vme_addr_t addr; 541 int mod; 542 bus_space_tag_t tag; 543 bus_space_handle_t *hp; 544 { 545 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 546 bus_type_t iospace; 547 bus_addr_t paddr; 548 int error; 549 550 error = vmebus_translate(sc, mod, addr, &iospace, &paddr); 551 if (error != 0) 552 return (error); 553 554 return (bus_space_mmap(sc->sc_bustag, iospace, paddr, 0, hp)); 555 } 556 557 #if defined(SUN4M) 558 void 559 sparc_vme4m_barrier(t, h, offset, size, flags) 560 bus_space_tag_t t; 561 bus_space_handle_t h; 562 bus_size_t offset; 563 bus_size_t size; 564 int flags; 565 { 566 struct vmebusreg *vbp = (struct vmebusreg *)t->cookie; 567 568 /* Read async fault status to flush write-buffers */ 569 (*(volatile int *)&vbp->vmebus_afsr); 570 } 571 #endif 572 573 574 575 /* 576 * VME Interrupt Priority Level to sparc Processor Interrupt Level. 577 */ 578 static int vme_ipl_to_pil[] = { 579 0, 580 2, 581 3, 582 5, 583 7, 584 9, 585 11, 586 13 587 }; 588 589 590 /* 591 * All VME device interrupts go through vmeintr(). This function reads 592 * the VME vector from the bus, then dispatches the device interrupt 593 * handler. All handlers for devices that map to the same Processor 594 * Interrupt Level (according to the table above) are on a linked list 595 * of `sparc_vme_intr_handle' structures. The head of which is passed 596 * down as the argument to `vmeintr(void *arg)'. 597 */ 598 struct sparc_vme_intr_handle { 599 struct intrhand ih; 600 struct sparc_vme_intr_handle *next; 601 int vec; /* VME interrupt vector */ 602 int pri; /* VME interrupt priority */ 603 struct vmebus_softc *sc;/*XXX*/ 604 }; 605 606 #if defined(SUN4) 607 int 608 vmeintr4(arg) 609 void *arg; 610 { 611 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 612 int level, vec; 613 int i = 0; 614 615 level = (ihp->pri << 1) | 1; 616 617 vec = ldcontrolb((caddr_t)(AC_VMEINTVEC | level)); 618 619 if (vec == -1) { 620 printf("vme: spurious interrupt\n"); 621 return 1; /* XXX - pretend we handled it, for now */ 622 } 623 624 for (; ihp; ihp = ihp->next) 625 if (ihp->vec == vec && ihp->ih.ih_fun) 626 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 627 return (i); 628 } 629 #endif 630 631 #if defined(SUN4M) 632 int 633 vmeintr4m(arg) 634 void *arg; 635 { 636 struct sparc_vme_intr_handle *ihp = (vme_intr_handle_t)arg; 637 int level, vec; 638 int i = 0; 639 640 level = (ihp->pri << 1) | 1; 641 642 #if 0 643 int pending; 644 645 /* Flush VME <=> Sbus write buffers */ 646 (*(volatile int *)&ihp->sc->sc_reg->vmebus_afsr); 647 648 pending = *((int*)ICR_SI_PEND); 649 if ((pending & SINTR_VME(ihp->pri)) == 0) { 650 printf("vmeintr: non pending at pri %x(p 0x%x)\n", 651 ihp->pri, pending); 652 return (0); 653 } 654 #endif 655 #if 0 656 /* Why gives this a bus timeout sometimes? */ 657 vec = ihp->sc->sc_vec->vmebusvec[level]; 658 #else 659 /* so, arrange to catch the fault... */ 660 { 661 extern struct user *proc0paddr; 662 extern int fkbyte __P((caddr_t, struct pcb *)); 663 caddr_t addr = (caddr_t)&ihp->sc->sc_vec->vmebusvec[level]; 664 struct pcb *xpcb; 665 u_long saveonfault; 666 int s; 667 668 s = splhigh(); 669 if (curproc == NULL) 670 xpcb = (struct pcb *)proc0paddr; 671 else 672 xpcb = &curproc->p_addr->u_pcb; 673 674 saveonfault = (u_long)xpcb->pcb_onfault; 675 vec = fkbyte(addr, xpcb); 676 xpcb->pcb_onfault = (caddr_t)saveonfault; 677 678 splx(s); 679 } 680 #endif 681 682 if (vec == -1) { 683 printf("vme: spurious interrupt: "); 684 printf("SI: 0x%x, VME AFSR: 0x%x, VME AFAR 0x%x\n", 685 *((int*)ICR_SI_PEND), 686 ihp->sc->sc_reg->vmebus_afsr, 687 ihp->sc->sc_reg->vmebus_afar); 688 return 1; /* XXX - pretend we handled it, for now */ 689 } 690 691 for (; ihp; ihp = ihp->next) 692 if (ihp->vec == vec && ihp->ih.ih_fun) 693 i += (ihp->ih.ih_fun)(ihp->ih.ih_arg); 694 return (i); 695 } 696 #endif 697 698 int 699 sparc_vme_intr_map(cookie, vec, pri, ihp) 700 void *cookie; 701 int vec; 702 int pri; 703 vme_intr_handle_t *ihp; 704 { 705 struct sparc_vme_intr_handle *ih; 706 707 ih = (vme_intr_handle_t) 708 malloc(sizeof(struct sparc_vme_intr_handle), M_DEVBUF, M_NOWAIT); 709 ih->pri = pri; 710 ih->vec = vec; 711 ih->sc = cookie;/*XXX*/ 712 *ihp = ih; 713 return (0); 714 } 715 716 void * 717 sparc_vme_intr_establish(cookie, vih, func, arg) 718 void *cookie; 719 vme_intr_handle_t vih; 720 int (*func) __P((void *)); 721 void *arg; 722 { 723 struct vmebus_softc *sc = (struct vmebus_softc *)cookie; 724 struct sparc_vme_intr_handle *svih = 725 (struct sparc_vme_intr_handle *)vih; 726 struct intrhand *ih; 727 int level; 728 729 /* Translate VME priority to processor IPL */ 730 level = vme_ipl_to_pil[svih->pri]; 731 732 svih->ih.ih_fun = func; 733 svih->ih.ih_arg = arg; 734 svih->next = NULL; 735 736 /* ensure the interrupt subsystem will call us at this level */ 737 for (ih = intrhand[level]; ih != NULL; ih = ih->ih_next) 738 if (ih->ih_fun == sc->sc_vmeintr) 739 break; 740 741 if (ih == NULL) { 742 ih = (struct intrhand *) 743 malloc(sizeof(struct intrhand), M_DEVBUF, M_NOWAIT); 744 if (ih == NULL) 745 panic("vme_addirq"); 746 bzero(ih, sizeof *ih); 747 ih->ih_fun = sc->sc_vmeintr; 748 ih->ih_arg = vih; 749 intr_establish(level, ih); 750 } else { 751 svih->next = (vme_intr_handle_t)ih->ih_arg; 752 ih->ih_arg = vih; 753 } 754 return (NULL); 755 } 756 757 void 758 sparc_vme_unmap(cookie) 759 void * cookie; 760 { 761 /* Not implemented */ 762 panic("sparc_vme_unmap"); 763 } 764 765 void 766 sparc_vme_intr_disestablish(cookie, a) 767 void *cookie; 768 void *a; 769 { 770 /* Not implemented */ 771 panic("sparc_vme_intr_disestablish"); 772 } 773 774 775 776 /* 777 * VME DMA functions. 778 */ 779 780 #if defined(SUN4) 781 int 782 sparc_vme4_dmamap_load(t, map, buf, buflen, p, flags) 783 bus_dma_tag_t t; 784 bus_dmamap_t map; 785 void *buf; 786 bus_size_t buflen; 787 struct proc *p; 788 int flags; 789 { 790 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 791 int error; 792 793 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 794 if (error != 0) 795 return (error); 796 797 /* Adjust DVMA address to VME view */ 798 map->dm_segs[0].ds_addr -= DVMA_BASE; 799 return (0); 800 } 801 802 void 803 sparc_vme4_dmamap_unload(t, map) 804 bus_dma_tag_t t; 805 bus_dmamap_t map; 806 { 807 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 808 809 map->dm_segs[0].ds_addr += DVMA_BASE; 810 bus_dmamap_unload(sc->sc_dmatag, map); 811 } 812 813 int 814 sparc_vme4_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 815 bus_dma_tag_t t; 816 bus_size_t size, alignment, boundary; 817 bus_dma_segment_t *segs; 818 int nsegs; 819 int *rsegs; 820 int flags; 821 { 822 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 823 int error; 824 825 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignment, boundary, 826 segs, nsegs, rsegs, flags); 827 if (error != 0) 828 return (error); 829 830 segs[0].ds_addr -= DVMA_BASE; 831 return (0); 832 } 833 834 void 835 sparc_vme4_dmamem_free(t, segs, nsegs) 836 bus_dma_tag_t t; 837 bus_dma_segment_t *segs; 838 int nsegs; 839 { 840 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 841 842 segs[0].ds_addr += DVMA_BASE; 843 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 844 } 845 846 void 847 sparc_vme4_dmamap_sync(t, map, offset, len, ops) 848 bus_dma_tag_t t; 849 bus_dmamap_t map; 850 bus_addr_t offset; 851 bus_size_t len; 852 int ops; 853 { 854 855 /* 856 * XXX Should perform cache flushes as necessary (e.g. 4/200 W/B). 857 */ 858 } 859 #endif /* SUN4 */ 860 861 #if defined(SUN4M) 862 static int 863 sparc_vme4m_dmamap_create (t, size, nsegments, maxsegsz, boundary, flags, dmamp) 864 bus_dma_tag_t t; 865 bus_size_t size; 866 int nsegments; 867 bus_size_t maxsegsz; 868 bus_size_t boundary; 869 int flags; 870 bus_dmamap_t *dmamp; 871 { 872 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 873 int align; 874 875 /* VME DVMA addresses must always be 8K aligned */ 876 align = 8192; 877 878 /* XXX - todo: allocate DVMA addresses from assigned ranges: 879 upper 8MB for A32 space; upper 1MB for A24 space */ 880 return (bus_dmamap_create(sc->sc_dmatag, size, nsegments, maxsegsz, 881 boundary, /*align,*/ flags, dmamp)); 882 } 883 884 int 885 sparc_vme4m_dmamap_load(t, map, buf, buflen, p, flags) 886 bus_dma_tag_t t; 887 bus_dmamap_t map; 888 void *buf; 889 bus_size_t buflen; 890 struct proc *p; 891 int flags; 892 { 893 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 894 volatile u_int32_t *ioctags; 895 int error; 896 897 buflen = (buflen + VME_IOC_PAGESZ - 1) & ~(VME_IOC_PAGESZ - 1); 898 error = bus_dmamap_load(sc->sc_dmatag, map, buf, buflen, p, flags); 899 if (error != 0) 900 return (error); 901 902 /* allocate IO cache entries for this range */ 903 ioctags = sc->sc_ioctags + VME_IOC_LINE(map->dm_segs[0].ds_addr); 904 for (;buflen > 0;) { 905 *ioctags = VME_IOC_IC | VME_IOC_W; 906 ioctags += VME_IOC_LINESZ/sizeof(*ioctags); 907 buflen -= VME_IOC_PAGESZ; 908 } 909 return (0); 910 } 911 912 913 void 914 sparc_vme4m_dmamap_unload(t, map) 915 bus_dma_tag_t t; 916 bus_dmamap_t map; 917 { 918 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 919 volatile u_int32_t *flushregs; 920 int len; 921 922 /* Flush VME IO cache */ 923 len = map->dm_segs[0].ds_len; 924 flushregs = sc->sc_iocflush + VME_IOC_LINE(map->dm_segs[0].ds_addr); 925 for (;len > 0;) { 926 *flushregs = 0; 927 flushregs += VME_IOC_LINESZ/sizeof(*flushregs); 928 len -= VME_IOC_PAGESZ; 929 } 930 /* Read a tag to synchronize the IOC flushes */ 931 (*sc->sc_ioctags); 932 933 bus_dmamap_unload(sc->sc_dmatag, map); 934 } 935 936 int 937 sparc_vme4m_dmamem_alloc(t, size, alignmnt, boundary, segs, nsegs, rsegs, flags) 938 bus_dma_tag_t t; 939 bus_size_t size, alignmnt, boundary; 940 bus_dma_segment_t *segs; 941 int nsegs; 942 int *rsegs; 943 int flags; 944 { 945 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 946 int error; 947 948 error = bus_dmamem_alloc(sc->sc_dmatag, size, alignmnt, boundary, 949 segs, nsegs, rsegs, flags); 950 if (error != 0) 951 return (error); 952 953 return (0); 954 } 955 956 void 957 sparc_vme4m_dmamem_free(t, segs, nsegs) 958 bus_dma_tag_t t; 959 bus_dma_segment_t *segs; 960 int nsegs; 961 { 962 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 963 964 bus_dmamem_free(sc->sc_dmatag, segs, nsegs); 965 } 966 967 int 968 sparc_vme_dmamem_map(t, segs, nsegs, size, kvap, flags) 969 bus_dma_tag_t t; 970 bus_dma_segment_t *segs; 971 int nsegs; 972 size_t size; 973 caddr_t *kvap; 974 int flags; 975 { 976 struct vmebus_softc *sc = (struct vmebus_softc *)t->_cookie; 977 978 return (bus_dmamem_map(sc->sc_dmatag, segs, nsegs, size, kvap, flags)); 979 } 980 981 void 982 sparc_vme4m_dmamap_sync(t, map, offset, len, ops) 983 bus_dma_tag_t t; 984 bus_dmamap_t map; 985 bus_addr_t offset; 986 bus_size_t len; 987 int ops; 988 { 989 990 /* 991 * XXX Should perform cache flushes as necessary. 992 */ 993 } 994 #endif /* SUN4M */ 995
Indexes created Mon Sep 22 05:09:51 GMT 2025