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vmereg.h revision 1.3
      1 /*	$NetBSD: vmereg.h,v 1.3 1998/01/25 16:06:25 pk Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1997 	Paul Kranenburg
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Paul Kranenburg.
     17  * 4. Neither the name of the University nor the names of its contributors
     18  *    may be used to endorse or promote products derived from this software
     19  *    without specific prior written permission.
     20  *
     21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     31  * SUCH DAMAGE.
     32  *
     33  */
     34 
     35 struct vmebusreg {
     36 	volatile u_int32_t	vmebus_cr;	/* VMEbus control register */
     37 	volatile u_int32_t	vmebus_afar;	/* VMEbus async fault address */
     38 	volatile u_int32_t	vmebus_afsr;	/* VMEbus async fault status */
     39 };
     40 
     41 /* VME Control Register bits */
     42 #define VMEBUS_CR_C	0x80000000	/* I/O cache enable */
     43 #define VMEBUS_CR_S	0x40000000	/* VME slave enable */
     44 #define VMEBUS_CR_L	0x20000000	/* Loopback enable (diagnostic) */
     45 #define VMEBUS_CR_R	0x10000000	/* VMEbus reset */
     46 #define VMEBUS_CR_RSVD	0x0ffffff0	/* reserved */
     47 #define VMEBUS_CR_IMPL	0x0000000f	/* VMEbus interface implementation */
     48 
     49 /* VME Asynchronous Fault Status bits */
     50 #define VMEBUS_AFSR_SZ	0xe0000000	/* Error transaction size */
     51 #define    VMEBUS_AFSR_SZ4	0	/* 4 byte */
     52 #define    VMEBUS_AFSR_SZ1	1	/* 1 byte */
     53 #define    VMEBUS_AFSR_SZ2	2	/* 2 byte */
     54 #define    VMEBUS_AFSR_SZ32	5	/* 32 byte */
     55 #define VMEBUS_AFSR_TO	0x10000000	/* VME master access time-out */
     56 #define VMEBUS_AFSR_BERR 0x08000000	/* VME master got BERR */
     57 #define VMEBUS_AFSR_WB	0x04000000	/* IOC write-back error (if SZ == 32) */
     58 					/* Non-IOC write error (id SZ != 32) */
     59 #define VMEBUS_AFSR_ERR	0x02000000	/* Error summary bit */
     60 #define VMEBUS_AFSR_S	0x01000000	/* MVME error in supervisor space */
     61 #define VMEBUS_AFSR_ME	0x00800000	/* Multiple error */
     62 #define VMEBUS_AFSR_RSVD 0x007fffff	/* reserved */
     63 
     64 struct vmebusvec {
     65 	volatile u_int8_t	vmebusvec[16];
     66 };
     67 
     68 /*
     69  * VME IO-cache definitions.
     70  */
     71 #define VME_IOC_SIZE		0x8000
     72 #define VME_IOC_LINESHFT	5
     73 #define VME_IOC_LINESZ		(1 << VME_IOC_LINESHFT)
     74 
     75 /*
     76  * The VME IO cache lines are selected by bits [13-22] of the DVMA address.
     77  * A byte within a cache line is selected by bits [0-4]. The bits in between
     78  * (e.g. [5-12]) are used as the cache tag.
     79  */
     80 #define VME_IOC_IDXSHFT		13
     81 #define VME_IOC_IDXMASK		0x3ff
     82 #define VME_IOC_PAGESZ		(1 << VME_IOC_IDXSHFT) /* 8192 */
     83 #define VME_IOC_LINE_IDX(addr)	\
     84 	((((u_long)(addr)) >> VME_IOC_IDXSHFT) & VME_IOC_IDXMASK)
     85 #define VME_IOC_LINE(addr)	(VME_IOC_LINE_IDX(addr) << VME_IOC_LINESHFT)
     86 
     87 /* Format of a IO cache tag entry */
     88 #define VME_IOC_W		0x00100000	/* Allow writes */
     89 #define VME_IOC_IC		0x00200000	/* Line is cacheable */
     90 #define VME_IOC_M		0x00400000	/* Line is modified */
     91 #define VME_IOC_V		0x00800000	/* Data is valid */
     92 #define VME_IOC_TAGMASK		0xff000000	/* Tag (bits <5-12> of DVMA) */
     93 
     94 /*
     95  * Physical IO-cache addresses.
     96  * (expressed as offsets relative to VME vector registers, for want
     97  *  of something better).
     98  */
     99 #define VME_IOC_TAGOFFSET	0x0f000000
    100 #define VME_IOC_DATAOFFSET	0x0f008000
    101 #define VME_IOC_FLUSHOFFSET	0x0f020000
    102 
    103