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vmereg.h revision 1.5.70.1 
      1 /*	$NetBSD: vmereg.h,v 1.5.70.1 2005/11/22 16:08:02 yamt Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Paul Kranenburg.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *        This product includes software developed by the NetBSD
     21  *        Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 struct vmebusreg {
     40 	volatile uint32_t	vmebus_cr;	/* VMEbus control register */
     41 	volatile uint32_t	vmebus_afar;	/* VMEbus async fault address */
     42 	volatile uint32_t	vmebus_afsr;	/* VMEbus async fault status */
     43 };
     44 
     45 /* VME bus Register offsets */
     46 #define VMEBUS_CR_REG	0
     47 #define VMEBUS_AFAR_REG	4
     48 #define VMEBUS_AFSR_REG	8
     49 
     50 /* VME Control Register bits */
     51 #define VMEBUS_CR_C	0x80000000	/* I/O cache enable */
     52 #define VMEBUS_CR_S	0x40000000	/* VME slave enable */
     53 #define VMEBUS_CR_L	0x20000000	/* Loopback enable (diagnostic) */
     54 #define VMEBUS_CR_R	0x10000000	/* VMEbus reset */
     55 #define VMEBUS_CR_RSVD	0x0ffffff0	/* reserved */
     56 #define VMEBUS_CR_IMPL	0x0000000f	/* VMEbus interface implementation */
     57 #define VMEBUS_CR_BITS	"\177\020"	\
     58 			"f\0\4IMPL\0b\34R\0b\35L\0b\36S\0b\37C\0"
     59 
     60 /* VME Asynchronous Fault Status bits */
     61 #define VMEBUS_AFSR_SZ	0xe0000000	/* Error transaction size */
     62 #define    VMEBUS_AFSR_SZ4	0	/* 4 byte */
     63 #define    VMEBUS_AFSR_SZ1	1	/* 1 byte */
     64 #define    VMEBUS_AFSR_SZ2	2	/* 2 byte */
     65 #define    VMEBUS_AFSR_SZ32	5	/* 32 byte */
     66 #define VMEBUS_AFSR_TO	0x10000000	/* VME master access time-out */
     67 #define VMEBUS_AFSR_BERR 0x08000000	/* VME master got BERR */
     68 #define VMEBUS_AFSR_WB	0x04000000	/* IOC write-back error (if SZ == 32) */
     69 					/* Non-IOC write error (id SZ != 32) */
     70 #define VMEBUS_AFSR_ERR	0x02000000	/* Error summary bit */
     71 #define VMEBUS_AFSR_S	0x01000000	/* MVME error in supervisor space */
     72 #define VMEBUS_AFSR_ME	0x00800000	/* Multiple error */
     73 #define VMEBUS_AFSR_RSVD 0x007fffff	/* reserved */
     74 #define VMEBUS_AFSR_BITS "\177\020"	\
     75 			 "b\27ME\0b\30S\0b\31ERR\0b\32WB\0\33TO\0f\34\3SZ\0"
     76 
     77 struct vmebusvec {
     78 	volatile uint8_t	vmebusvec[16];
     79 };
     80 
     81 /*
     82  * VME IO-cache definitions.
     83  */
     84 #define VME_IOC_SIZE		0x8000
     85 #define VME_IOC_LINESHFT	5
     86 #define VME_IOC_LINESZ		(1 << VME_IOC_LINESHFT)
     87 
     88 /*
     89  * The VME IO cache lines are selected by bits [13-22] of the DVMA address.
     90  * A byte within a cache line is selected by bits [0-4]. The bits in between
     91  * (e.g. [5-12]) are used as the cache tag.
     92  */
     93 #define VME_IOC_IDXSHFT		13
     94 #define VME_IOC_IDXMASK		0x3ff
     95 #define VME_IOC_PAGESZ		(1 << VME_IOC_IDXSHFT) /* 8192 */
     96 #define VME_IOC_LINE_IDX(addr)	\
     97 	((((u_long)(addr)) >> VME_IOC_IDXSHFT) & VME_IOC_IDXMASK)
     98 #define VME_IOC_LINE(addr)	(VME_IOC_LINE_IDX(addr) << VME_IOC_LINESHFT)
     99 
    100 /* Format of a IO cache tag entry */
    101 #define VME_IOC_W		0x00100000	/* Allow writes */
    102 #define VME_IOC_IC		0x00200000	/* Line is cacheable */
    103 #define VME_IOC_M		0x00400000	/* Line is modified */
    104 #define VME_IOC_V		0x00800000	/* Data is valid */
    105 #define VME_IOC_TAGMASK		0xff000000	/* Tag (bits <5-12> of DVMA) */
    106 #define VME_IOC_BITS		"\177\020"	\
    107 				"b\24W\0b\25IC\0b\26M\0b\27V\0f\30\10TAG\0"
    108 
    109 /*
    110  * Physical IO-cache addresses.
    111  * (expressed as offsets relative to VME vector registers, for want
    112  *  of something better).
    113  */
    114 #define VME_IOC_TAGOFFSET	0x0f000000
    115 #define VME_IOC_DATAOFFSET	0x0f008000
    116 #define VME_IOC_FLUSHOFFSET	0x0f020000
    117