fpu.c revision 1.19
1 /* $NetBSD: fpu.c,v 1.19 2003/07/15 00:04:58 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 #include <sys/cdefs.h> 48 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.19 2003/07/15 00:04:58 lukem Exp $"); 49 50 #include <sys/param.h> 51 #include <sys/proc.h> 52 #include <sys/signal.h> 53 #include <sys/systm.h> 54 #include <sys/syslog.h> 55 #include <sys/signalvar.h> 56 57 #include <machine/instr.h> 58 #include <machine/reg.h> 59 60 #include <sparc/fpu/fpu_emu.h> 61 #include <sparc/fpu/fpu_extern.h> 62 63 int fpe_debug = 0; 64 65 #ifdef DEBUG 66 /* 67 * Dump a `fpn' structure. 68 */ 69 void 70 fpu_dumpfpn(struct fpn *fp) 71 { 72 static char *class[] = { 73 "SNAN", "QNAN", "ZERO", "NUM", "INF" 74 }; 75 76 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 77 fp->fp_sign ? '-' : ' ', 78 fp->fp_mant[0], fp->fp_mant[1], 79 fp->fp_mant[2], fp->fp_mant[3], 80 fp->fp_exp); 81 } 82 #endif 83 84 /* 85 * fpu_execute returns the following error numbers (0 = no error): 86 */ 87 #define FPE 1 /* take a floating point exception */ 88 #define NOTFPU 2 /* not an FPU instruction */ 89 90 /* 91 * Translate current exceptions into `first' exception. The 92 * bits go the wrong way for ffs() (0x10 is most important, etc). 93 * There are only 5, so do it the obvious way. 94 */ 95 #define X1(x) x 96 #define X2(x) x,x 97 #define X4(x) x,x,x,x 98 #define X8(x) X4(x),X4(x) 99 #define X16(x) X8(x),X8(x) 100 101 static char cx_to_trapx[] = { 102 X1(FSR_NX), 103 X2(FSR_DZ), 104 X4(FSR_UF), 105 X8(FSR_OF), 106 X16(FSR_NV) 107 }; 108 static u_char fpu_codes[] = { 109 X1(FPE_FLTINEX_TRAP), 110 X2(FPE_FLTDIV_TRAP), 111 X4(FPE_FLTUND_TRAP), 112 X8(FPE_FLTOVF_TRAP), 113 X16(FPE_FLTOPERR_TRAP) 114 }; 115 116 /* 117 * The FPU gave us an exception. Clean up the mess. Note that the 118 * fp queue can only have FPops in it, never load/store FP registers 119 * nor FBfcc instructions. Experiments with `crashme' prove that 120 * unknown FPops do enter the queue, however. 121 */ 122 void 123 fpu_cleanup(l, fs) 124 register struct lwp *l; 125 #ifndef SUN4U 126 register struct fpstate *fs; 127 #else /* SUN4U */ 128 register struct fpstate64 *fs; 129 #endif /* SUN4U */ 130 { 131 register int i, fsr = fs->fs_fsr, error; 132 struct proc *p = l->l_proc; 133 union instr instr; 134 struct fpemu fe; 135 136 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 137 138 case FSR_TT_NONE: 139 panic("fpu_cleanup: No fault"); /* ??? */ 140 break; 141 142 case FSR_TT_IEEE: 143 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_IEEE\n")); 144 /* XXX missing trap address! */ 145 if ((i = fsr & FSR_CX) == 0) 146 panic("fpu ieee trap, but no exception"); 147 KERNEL_PROC_LOCK(l); 148 trapsignal(l, SIGFPE, fpu_codes[i - 1]); 149 KERNEL_PROC_UNLOCK(l); 150 break; /* XXX should return, but queue remains */ 151 152 case FSR_TT_UNFIN: 153 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNFIN\n")); 154 #ifdef SUN4U 155 if (fs->fs_qsize == 0) { 156 printf("fpu_cleanup: unfinished fpop"); 157 /* The book sez reexecute or emulate. */ 158 return; 159 } 160 break; 161 162 #endif /* SUN4U */ 163 case FSR_TT_UNIMP: 164 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNIMP\n")); 165 if (fs->fs_qsize == 0) 166 panic("fpu_cleanup: unimplemented fpop"); 167 break; 168 169 case FSR_TT_SEQ: 170 panic("fpu sequence error"); 171 /* NOTREACHED */ 172 173 case FSR_TT_HWERR: 174 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_HWERR\n")); 175 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 176 p->p_comm, p->p_pid); 177 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 178 KERNEL_PROC_LOCK(l); 179 trapsignal(l, SIGFPE, -1); /* ??? */ 180 KERNEL_PROC_UNLOCK(l); 181 goto out; 182 183 default: 184 printf("fsr=0x%x\n", fsr); 185 panic("fpu error"); 186 } 187 188 /* emulate the instructions left in the queue */ 189 fe.fe_fpstate = fs; 190 for (i = 0; i < fs->fs_qsize; i++) { 191 instr.i_int = fs->fs_queue[i].fq_instr; 192 if (instr.i_any.i_op != IOP_reg || 193 (instr.i_op3.i_op3 != IOP3_FPop1 && 194 instr.i_op3.i_op3 != IOP3_FPop2)) 195 panic("bogus fpu queue"); 196 error = fpu_execute(&fe, instr); 197 if (error == 0) 198 continue; 199 200 KERNEL_PROC_LOCK(l); 201 switch (error) { 202 case FPE: 203 trapsignal(l, SIGFPE, 204 fpu_codes[(fs->fs_fsr & FSR_CX) - 1]); 205 break; 206 207 case NOTFPU: 208 #ifdef SUN4U 209 #ifdef DEBUG 210 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n"); 211 #endif 212 #endif /* SUN4U */ 213 trapsignal(l, SIGILL, 0); /* ??? code? */ 214 break; 215 216 default: 217 panic("fpu_cleanup 3"); 218 /* NOTREACHED */ 219 } 220 KERNEL_PROC_UNLOCK(l); 221 /* XXX should stop here, but queue remains */ 222 } 223 out: 224 fs->fs_qsize = 0; 225 } 226 227 #ifdef notyet 228 /* 229 * If we have no FPU at all (are there any machines like this out 230 * there!?) we have to emulate each instruction, and we need a pointer 231 * to the trapframe so that we can step over them and do FBfcc's. 232 * We know the `queue' is empty, though; we just want to emulate 233 * the instruction at tf->tf_pc. 234 */ 235 fpu_emulate(l, tf, fs) 236 struct lwp *l; 237 register struct trapframe *tf; 238 #ifndef SUN4U 239 register struct fpstate *fs; 240 #else /* SUN4U */ 241 register struct fpstate64 *fs; 242 #endif /* SUN4U */ 243 { 244 245 do { 246 fetch instr from pc 247 decode 248 if (integer instr) { 249 /* 250 * We do this here, rather than earlier, to avoid 251 * losing even more badly than usual. 252 */ 253 if (l->l_addr->u_pcb.pcb_uw) { 254 write_user_windows(); 255 if (rwindow_save(l)) 256 sigexit(l, SIGILL); 257 } 258 if (loadstore) { 259 do_it; 260 pc = npc, npc += 4 261 } else if (fbfcc) { 262 do_annul_stuff; 263 } else 264 return; 265 } else if (fpu instr) { 266 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 267 error = fpu_execute(&fe, fs, instr); 268 switch (error) { 269 etc; 270 } 271 } else 272 return; 273 if (want to reschedule) 274 return; 275 } while (error == 0); 276 } 277 #endif 278 279 /* 280 * Execute an FPU instruction (one that runs entirely in the FPU; not 281 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 282 * modified to reflect the setting the hardware would have left. 283 * 284 * Note that we do not catch all illegal opcodes, so you can, for instance, 285 * multiply two integers this way. 286 */ 287 int 288 fpu_execute(fe, instr) 289 register struct fpemu *fe; 290 union instr instr; 291 { 292 register struct fpn *fp; 293 #ifndef SUN4U 294 register int opf, rs1, rs2, rd, type, mask, fsr, cx; 295 register struct fpstate *fs; 296 #else /* SUN4U */ 297 register int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 298 register struct fpstate64 *fs; 299 #endif /* SUN4U */ 300 u_int space[4]; 301 302 /* 303 * `Decode' and execute instruction. Start with no exceptions. 304 * The type of any i_opf opcode is in the bottom two bits, so we 305 * squish them out here. 306 */ 307 opf = instr.i_opf.i_opf; 308 /* 309 * The low two bits of the opf field for floating point insns usually 310 * correspond to the operation width: 311 * 312 * 0: Invalid 313 * 1: Single precision float 314 * 2: Double precision float 315 * 3: Quad precision float 316 * 317 * The exceptions are the integer to float conversion instructions. 318 * 319 * For double and quad precision, the low bit if the rs or rd field 320 * is actually the high bit of the register number. 321 */ 322 323 type = opf & 3; 324 mask = 0x3 >> (3 - type); 325 326 rs1 = instr.i_opf.i_rs1; 327 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5); 328 rs2 = instr.i_opf.i_rs2; 329 rs2 = (rs2 & ~mask) | ((rs2 & mask & 0x1) << 5); 330 rd = instr.i_opf.i_rd; 331 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 332 #ifdef DIAGNOSTIC 333 if ((rs1 | rs2 | rd) & mask) 334 /* This may be an FPU insn but it is illegal. */ 335 return (NOTFPU); 336 #endif 337 fs = fe->fe_fpstate; 338 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 339 fe->fe_cx = 0; 340 #ifdef SUN4U 341 /* 342 * Check to see if we're dealing with a fancy cmove and handle 343 * it first. 344 */ 345 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 346 switch (opf >>= 2) { 347 case FMVFC0 >> 2: 348 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n")); 349 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 350 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 351 rs1 = fs->fs_regs[rs2]; 352 goto mov; 353 case FMVFC1 >> 2: 354 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n")); 355 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 356 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 357 rs1 = fs->fs_regs[rs2]; 358 goto mov; 359 case FMVFC2 >> 2: 360 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n")); 361 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 362 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 363 rs1 = fs->fs_regs[rs2]; 364 goto mov; 365 case FMVFC3 >> 2: 366 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n")); 367 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 368 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 369 rs1 = fs->fs_regs[rs2]; 370 goto mov; 371 case FMVIC >> 2: 372 /* Presume we're curlwp */ 373 DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n")); 374 cond = (curlwp->l_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 375 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 376 rs1 = fs->fs_regs[rs2]; 377 goto mov; 378 case FMVXC >> 2: 379 /* Presume we're curlwp */ 380 DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n")); 381 cond = (curlwp->l_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 382 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 383 rs1 = fs->fs_regs[rs2]; 384 goto mov; 385 case FMVRZ >> 2: 386 /* Presume we're curlwp */ 387 DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n")); 388 rs1 = instr.i_fmovr.i_rs1; 389 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] != 0) 390 return (0); /* success */ 391 rs1 = fs->fs_regs[rs2]; 392 goto mov; 393 case FMVRLEZ >> 2: 394 /* Presume we're curlwp */ 395 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n")); 396 rs1 = instr.i_fmovr.i_rs1; 397 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] > 0) 398 return (0); /* success */ 399 rs1 = fs->fs_regs[rs2]; 400 goto mov; 401 case FMVRLZ >> 2: 402 /* Presume we're curlwp */ 403 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n")); 404 rs1 = instr.i_fmovr.i_rs1; 405 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] >= 0) 406 return (0); /* success */ 407 rs1 = fs->fs_regs[rs2]; 408 goto mov; 409 case FMVRNZ >> 2: 410 /* Presume we're curlwp */ 411 DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n")); 412 rs1 = instr.i_fmovr.i_rs1; 413 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] == 0) 414 return (0); /* success */ 415 rs1 = fs->fs_regs[rs2]; 416 goto mov; 417 case FMVRGZ >> 2: 418 /* Presume we're curlwp */ 419 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n")); 420 rs1 = instr.i_fmovr.i_rs1; 421 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] <= 0) 422 return (0); /* success */ 423 rs1 = fs->fs_regs[rs2]; 424 goto mov; 425 case FMVRGEZ >> 2: 426 /* Presume we're curlwp */ 427 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n")); 428 rs1 = instr.i_fmovr.i_rs1; 429 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] < 0) 430 return (0); /* success */ 431 rs1 = fs->fs_regs[rs2]; 432 goto mov; 433 default: 434 DPRINTF(FPE_INSN, 435 ("fpu_execute: unknown v9 FP inst %x opf %x\n", 436 instr.i_int, opf)); 437 return (NOTFPU); 438 } 439 } 440 #endif /* SUN4U */ 441 switch (opf >>= 2) { 442 443 default: 444 DPRINTF(FPE_INSN, 445 ("fpu_execute: unknown basic FP inst %x opf %x\n", 446 instr.i_int, opf)); 447 return (NOTFPU); 448 449 case FMOV >> 2: /* these should all be pretty obvious */ 450 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n")); 451 rs1 = fs->fs_regs[rs2]; 452 goto mov; 453 454 case FNEG >> 2: 455 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n")); 456 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 457 goto mov; 458 459 case FABS >> 2: 460 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 461 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 462 mov: 463 #ifndef SUN4U 464 fs->fs_regs[rd] = rs1; 465 #else /* SUN4U */ 466 i = 1<<(type-1); 467 fs->fs_regs[rd++] = rs1; 468 while (--i > 0) 469 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 470 #endif /* SUN4U */ 471 fs->fs_fsr = fe->fe_fsr; 472 return (0); /* success */ 473 474 case FSQRT >> 2: 475 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 476 fpu_explode(fe, &fe->fe_f1, type, rs2); 477 fp = fpu_sqrt(fe); 478 break; 479 480 case FADD >> 2: 481 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 482 fpu_explode(fe, &fe->fe_f1, type, rs1); 483 fpu_explode(fe, &fe->fe_f2, type, rs2); 484 fp = fpu_add(fe); 485 break; 486 487 case FSUB >> 2: 488 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 489 fpu_explode(fe, &fe->fe_f1, type, rs1); 490 fpu_explode(fe, &fe->fe_f2, type, rs2); 491 fp = fpu_sub(fe); 492 break; 493 494 case FMUL >> 2: 495 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 496 fpu_explode(fe, &fe->fe_f1, type, rs1); 497 fpu_explode(fe, &fe->fe_f2, type, rs2); 498 fp = fpu_mul(fe); 499 break; 500 501 case FDIV >> 2: 502 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 503 fpu_explode(fe, &fe->fe_f1, type, rs1); 504 fpu_explode(fe, &fe->fe_f2, type, rs2); 505 fp = fpu_div(fe); 506 break; 507 508 case FCMP >> 2: 509 DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n")); 510 fpu_explode(fe, &fe->fe_f1, type, rs1); 511 fpu_explode(fe, &fe->fe_f2, type, rs2); 512 fpu_compare(fe, 0); 513 goto cmpdone; 514 515 case FCMPE >> 2: 516 DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n")); 517 fpu_explode(fe, &fe->fe_f1, type, rs1); 518 fpu_explode(fe, &fe->fe_f2, type, rs2); 519 fpu_compare(fe, 1); 520 cmpdone: 521 /* 522 * The only possible exception here is NV; catch it 523 * early and get out, as there is no result register. 524 */ 525 cx = fe->fe_cx; 526 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 527 if (cx != 0) { 528 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 529 fs->fs_fsr = (fsr & ~FSR_FTT) | 530 (FSR_TT_IEEE << FSR_FTT_SHIFT); 531 return (FPE); 532 } 533 fsr |= FSR_NV << FSR_AX_SHIFT; 534 } 535 fs->fs_fsr = fsr; 536 return (0); 537 538 case FSMULD >> 2: 539 case FDMULX >> 2: 540 DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n")); 541 if (type == FTYPE_EXT) 542 return (NOTFPU); 543 fpu_explode(fe, &fe->fe_f1, type, rs1); 544 fpu_explode(fe, &fe->fe_f2, type, rs2); 545 type++; /* single to double, or double to quad */ 546 fp = fpu_mul(fe); 547 break; 548 549 #ifdef SUN4U 550 case FXTOS >> 2: 551 case FXTOD >> 2: 552 case FXTOQ >> 2: 553 DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n")); 554 type = FTYPE_LNG; 555 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 556 type = opf & 3; /* sneaky; depends on instruction encoding */ 557 break; 558 559 case FTOX >> 2: 560 DPRINTF(FPE_INSN, ("fpu_execute: FTOX\n")); 561 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 562 type = FTYPE_LNG; 563 /* Recalculate destination register */ 564 rd = instr.i_opf.i_rd; 565 break; 566 567 #endif /* SUN4U */ 568 case FTOI >> 2: 569 DPRINTF(FPE_INSN, ("fpu_execute: FTOI\n")); 570 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 571 type = FTYPE_INT; 572 /* Recalculate destination register */ 573 rd = instr.i_opf.i_rd; 574 break; 575 576 case FTOS >> 2: 577 case FTOD >> 2: 578 case FTOQ >> 2: 579 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 580 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 581 /* Recalculate rd with correct type info. */ 582 type = opf & 3; /* sneaky; depends on instruction encoding */ 583 mask = 0x3 >> (3 - type); 584 rd = instr.i_opf.i_rd; 585 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 586 break; 587 } 588 589 /* 590 * ALU operation is complete. Collapse the result and then check 591 * for exceptions. If we got any, and they are enabled, do not 592 * alter the destination register, just stop with an exception. 593 * Otherwise set new current exceptions and accrue. 594 */ 595 fpu_implode(fe, fp, type, space); 596 cx = fe->fe_cx; 597 fsr = fe->fe_fsr; 598 if (cx != 0) { 599 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 600 if (cx & mask) { 601 /* not accrued??? */ 602 fs->fs_fsr = (fsr & ~FSR_FTT) | 603 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 604 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 605 return (FPE); 606 } 607 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 608 } 609 fs->fs_fsr = fsr; 610 DPRINTF(FPE_REG, ("-> %c%d\n", (type == FTYPE_LNG) ? 'x' : 611 ((type == FTYPE_INT) ? 'i' : 612 ((type == FTYPE_SNG) ? 's' : 613 ((type == FTYPE_DBL) ? 'd' : 614 ((type == FTYPE_EXT) ? 'q' : '?')))), 615 rd)); 616 fs->fs_regs[rd] = space[0]; 617 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 618 fs->fs_regs[rd + 1] = space[1]; 619 if (type > FTYPE_DBL) { 620 fs->fs_regs[rd + 2] = space[2]; 621 fs->fs_regs[rd + 3] = space[3]; 622 } 623 } 624 return (0); /* success */ 625 } 626
Indexes created Thu Sep 25 16:09:42 GMT 2025