fpu.c revision 1.22
1 /* $NetBSD: fpu.c,v 1.22 2003/10/06 07:10:41 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.22 2003/10/06 07:10:41 pk Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/proc.h> 48 #include <sys/signal.h> 49 #include <sys/systm.h> 50 #include <sys/syslog.h> 51 #include <sys/signalvar.h> 52 53 #include <machine/instr.h> 54 #include <machine/reg.h> 55 56 #include <sparc/fpu/fpu_emu.h> 57 #include <sparc/fpu/fpu_extern.h> 58 59 int fpe_debug = 0; 60 61 #ifdef DEBUG 62 /* 63 * Dump a `fpn' structure. 64 */ 65 void 66 fpu_dumpfpn(struct fpn *fp) 67 { 68 static char *class[] = { 69 "SNAN", "QNAN", "ZERO", "NUM", "INF" 70 }; 71 72 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 73 fp->fp_sign ? '-' : ' ', 74 fp->fp_mant[0], fp->fp_mant[1], 75 fp->fp_mant[2], fp->fp_mant[3], 76 fp->fp_exp); 77 } 78 #endif 79 80 /* 81 * fpu_execute returns the following error numbers (0 = no error): 82 */ 83 #define FPE 1 /* take a floating point exception */ 84 #define NOTFPU 2 /* not an FPU instruction */ 85 86 /* 87 * Translate current exceptions into `first' exception. The 88 * bits go the wrong way for ffs() (0x10 is most important, etc). 89 * There are only 5, so do it the obvious way. 90 */ 91 #define X1(x) x 92 #define X2(x) x,x 93 #define X4(x) x,x,x,x 94 #define X8(x) X4(x),X4(x) 95 #define X16(x) X8(x),X8(x) 96 97 static char cx_to_trapx[] = { 98 X1(FSR_NX), 99 X2(FSR_DZ), 100 X4(FSR_UF), 101 X8(FSR_OF), 102 X16(FSR_NV) 103 }; 104 static u_char fpu_codes_native[] = { 105 X1(FPE_FLTRES), 106 X2(FPE_FLTDIV), 107 X4(FPE_FLTUND), 108 X8(FPE_FLTOVF), 109 X16(FPE_FLTINV) 110 }; 111 #if defined(COMPAT_SUNOS) 112 static u_char fpu_codes_sunos[] = { 113 X1(FPE_FLTINEX_TRAP), 114 X2(FPE_FLTDIV_TRAP), 115 X4(FPE_FLTUND_TRAP), 116 X8(FPE_FLTOVF_TRAP), 117 X16(FPE_FLTOPERR_TRAP) 118 }; 119 extern struct emul emul_sunos; 120 #endif /* SUNOS_COMPAT */ 121 /* Note: SVR4(Solaris) FPE_* codes happen to be compatible with ours */ 122 123 /* 124 * The FPU gave us an exception. Clean up the mess. Note that the 125 * fp queue can only have FPops in it, never load/store FP registers 126 * nor FBfcc instructions. Experiments with `crashme' prove that 127 * unknown FPops do enter the queue, however. 128 */ 129 void 130 fpu_cleanup(l, fs) 131 struct lwp *l; 132 #ifndef SUN4U 133 struct fpstate *fs; 134 #else /* SUN4U */ 135 struct fpstate64 *fs; 136 #endif /* SUN4U */ 137 { 138 int i, fsr = fs->fs_fsr, error; 139 struct proc *p = l->l_proc; 140 union instr instr; 141 struct fpemu fe; 142 u_char *fpu_codes; 143 ksiginfo_t ksi; 144 145 fpu_codes = 146 #ifdef COMPAT_SUNOS 147 (p->p_emul == &emul_sunos) ? fpu_codes_sunos : 148 #endif 149 fpu_codes_native; 150 151 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 152 153 case FSR_TT_NONE: 154 panic("fpu_cleanup: No fault"); /* ??? */ 155 break; 156 157 case FSR_TT_IEEE: 158 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_IEEE\n")); 159 /* XXX missing trap address! */ 160 if ((i = fsr & FSR_CX) == 0) 161 panic("fpu ieee trap, but no exception"); 162 ksi.ksi_signo = SIGFPE; 163 ksi.ksi_code = fpu_codes[i - 1]; 164 KERNEL_PROC_LOCK(l); 165 #ifdef __HAVE_SIGINFO 166 trapsignal(l, &ksi); 167 #else 168 trapsignal(l, ksi.ksi_signo, ksi.ksi_code); 169 #endif 170 KERNEL_PROC_UNLOCK(l); 171 break; /* XXX should return, but queue remains */ 172 173 case FSR_TT_UNFIN: 174 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNFIN\n")); 175 #ifdef SUN4U 176 if (fs->fs_qsize == 0) { 177 printf("fpu_cleanup: unfinished fpop"); 178 /* The book sez reexecute or emulate. */ 179 return; 180 } 181 break; 182 183 #endif /* SUN4U */ 184 case FSR_TT_UNIMP: 185 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_UNIMP\n")); 186 if (fs->fs_qsize == 0) 187 panic("fpu_cleanup: unimplemented fpop"); 188 break; 189 190 case FSR_TT_SEQ: 191 panic("fpu sequence error"); 192 /* NOTREACHED */ 193 194 case FSR_TT_HWERR: 195 DPRINTF(FPE_INSN, ("fpu_cleanup: FSR_TT_HWERR\n")); 196 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 197 p->p_comm, p->p_pid); 198 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 199 ksi.ksi_signo = SIGFPE; 200 ksi.ksi_code = 0; 201 KERNEL_PROC_LOCK(l); 202 #ifdef __HAVE_SIGINFO 203 trapsignal(l, &ksi); 204 #else 205 trapsignal(l, ksi.ksi_signo, ksi.ksi_code); 206 #endif 207 KERNEL_PROC_UNLOCK(l); 208 goto out; 209 210 default: 211 printf("fsr=0x%x\n", fsr); 212 panic("fpu error"); 213 } 214 215 /* emulate the instructions left in the queue */ 216 fe.fe_fpstate = fs; 217 for (i = 0; i < fs->fs_qsize; i++) { 218 instr.i_int = fs->fs_queue[i].fq_instr; 219 if (instr.i_any.i_op != IOP_reg || 220 (instr.i_op3.i_op3 != IOP3_FPop1 && 221 instr.i_op3.i_op3 != IOP3_FPop2)) 222 panic("bogus fpu queue"); 223 error = fpu_execute(&fe, instr); 224 if (error == 0) 225 continue; 226 227 KERNEL_PROC_LOCK(l); 228 switch (error) { 229 case FPE: 230 ksi.ksi_signo = SIGFPE; 231 ksi.ksi_code = fpu_codes[(fs->fs_fsr & FSR_CX) - 1]; 232 #ifdef __HAVE_SIGINFO 233 trapsignal(l, &ksi); 234 #else 235 trapsignal(l, ksi.ksi_signo, ksi.ksi_code); 236 #endif 237 break; 238 239 case NOTFPU: 240 #ifdef SUN4U 241 #ifdef DEBUG 242 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n"); 243 #endif 244 #endif /* SUN4U */ 245 ksi.ksi_signo = SIGFPE; 246 ksi.ksi_code = ILL_ILLOPC; 247 #ifdef __HAVE_SIGINFO 248 trapsignal(l, &ksi); 249 #else 250 trapsignal(l, ksi.ksi_signo, ksi.ksi_code); 251 #endif 252 break; 253 254 default: 255 panic("fpu_cleanup 3"); 256 /* NOTREACHED */ 257 } 258 KERNEL_PROC_UNLOCK(l); 259 /* XXX should stop here, but queue remains */ 260 } 261 out: 262 fs->fs_qsize = 0; 263 } 264 265 #ifdef notyet 266 /* 267 * If we have no FPU at all (are there any machines like this out 268 * there!?) we have to emulate each instruction, and we need a pointer 269 * to the trapframe so that we can step over them and do FBfcc's. 270 * We know the `queue' is empty, though; we just want to emulate 271 * the instruction at tf->tf_pc. 272 */ 273 fpu_emulate(l, tf, fs) 274 struct lwp *l; 275 struct trapframe *tf; 276 #ifndef SUN4U 277 struct fpstate *fs; 278 #else /* SUN4U */ 279 struct fpstate64 *fs; 280 #endif /* SUN4U */ 281 { 282 283 do { 284 fetch instr from pc 285 decode 286 if (integer instr) { 287 /* 288 * We do this here, rather than earlier, to avoid 289 * losing even more badly than usual. 290 */ 291 if (l->l_addr->u_pcb.pcb_uw) { 292 write_user_windows(); 293 if (rwindow_save(l)) 294 sigexit(l, SIGILL); 295 } 296 if (loadstore) { 297 do_it; 298 pc = npc, npc += 4 299 } else if (fbfcc) { 300 do_annul_stuff; 301 } else 302 return; 303 } else if (fpu instr) { 304 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 305 error = fpu_execute(&fe, fs, instr); 306 switch (error) { 307 etc; 308 } 309 } else 310 return; 311 if (want to reschedule) 312 return; 313 } while (error == 0); 314 } 315 #endif 316 317 /* 318 * Execute an FPU instruction (one that runs entirely in the FPU; not 319 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 320 * modified to reflect the setting the hardware would have left. 321 * 322 * Note that we do not catch all illegal opcodes, so you can, for instance, 323 * multiply two integers this way. 324 */ 325 int 326 fpu_execute(fe, instr) 327 struct fpemu *fe; 328 union instr instr; 329 { 330 struct fpn *fp; 331 #ifndef SUN4U 332 int opf, rs1, rs2, rd, type, mask, fsr, cx; 333 struct fpstate *fs; 334 #else /* SUN4U */ 335 int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 336 struct fpstate64 *fs; 337 #endif /* SUN4U */ 338 u_int space[4]; 339 340 /* 341 * `Decode' and execute instruction. Start with no exceptions. 342 * The type of any i_opf opcode is in the bottom two bits, so we 343 * squish them out here. 344 */ 345 opf = instr.i_opf.i_opf; 346 /* 347 * The low two bits of the opf field for floating point insns usually 348 * correspond to the operation width: 349 * 350 * 0: Invalid 351 * 1: Single precision float 352 * 2: Double precision float 353 * 3: Quad precision float 354 * 355 * The exceptions are the integer to float conversion instructions. 356 * 357 * For double and quad precision, the low bit if the rs or rd field 358 * is actually the high bit of the register number. 359 */ 360 361 type = opf & 3; 362 mask = 0x3 >> (3 - type); 363 364 rs1 = instr.i_opf.i_rs1; 365 rs1 = (rs1 & ~mask) | ((rs1 & mask & 0x1) << 5); 366 rs2 = instr.i_opf.i_rs2; 367 rs2 = (rs2 & ~mask) | ((rs2 & mask & 0x1) << 5); 368 rd = instr.i_opf.i_rd; 369 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 370 #ifdef DIAGNOSTIC 371 if ((rs1 | rs2 | rd) & mask) 372 /* This may be an FPU insn but it is illegal. */ 373 return (NOTFPU); 374 #endif 375 fs = fe->fe_fpstate; 376 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 377 fe->fe_cx = 0; 378 #ifdef SUN4U 379 /* 380 * Check to see if we're dealing with a fancy cmove and handle 381 * it first. 382 */ 383 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 384 switch (opf >>= 2) { 385 case FMVFC0 >> 2: 386 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n")); 387 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 388 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 389 rs1 = fs->fs_regs[rs2]; 390 goto mov; 391 case FMVFC1 >> 2: 392 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n")); 393 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 394 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 395 rs1 = fs->fs_regs[rs2]; 396 goto mov; 397 case FMVFC2 >> 2: 398 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n")); 399 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 400 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 401 rs1 = fs->fs_regs[rs2]; 402 goto mov; 403 case FMVFC3 >> 2: 404 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n")); 405 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 406 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 407 rs1 = fs->fs_regs[rs2]; 408 goto mov; 409 case FMVIC >> 2: 410 /* Presume we're curlwp */ 411 DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n")); 412 cond = (curlwp->l_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 413 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 414 rs1 = fs->fs_regs[rs2]; 415 goto mov; 416 case FMVXC >> 2: 417 /* Presume we're curlwp */ 418 DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n")); 419 cond = (curlwp->l_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 420 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 421 rs1 = fs->fs_regs[rs2]; 422 goto mov; 423 case FMVRZ >> 2: 424 /* Presume we're curlwp */ 425 DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n")); 426 rs1 = instr.i_fmovr.i_rs1; 427 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] != 0) 428 return (0); /* success */ 429 rs1 = fs->fs_regs[rs2]; 430 goto mov; 431 case FMVRLEZ >> 2: 432 /* Presume we're curlwp */ 433 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n")); 434 rs1 = instr.i_fmovr.i_rs1; 435 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] > 0) 436 return (0); /* success */ 437 rs1 = fs->fs_regs[rs2]; 438 goto mov; 439 case FMVRLZ >> 2: 440 /* Presume we're curlwp */ 441 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n")); 442 rs1 = instr.i_fmovr.i_rs1; 443 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] >= 0) 444 return (0); /* success */ 445 rs1 = fs->fs_regs[rs2]; 446 goto mov; 447 case FMVRNZ >> 2: 448 /* Presume we're curlwp */ 449 DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n")); 450 rs1 = instr.i_fmovr.i_rs1; 451 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] == 0) 452 return (0); /* success */ 453 rs1 = fs->fs_regs[rs2]; 454 goto mov; 455 case FMVRGZ >> 2: 456 /* Presume we're curlwp */ 457 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n")); 458 rs1 = instr.i_fmovr.i_rs1; 459 if (rs1 == 0 || (int64_t)curlwp->l_md.md_tf->tf_global[rs1] <= 0) 460 return (0); /* success */ 461 rs1 = fs->fs_regs[rs2]; 462 goto mov; 463 case FMVRGEZ >> 2: 464 /* Presume we're curlwp */ 465 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n")); 466 rs1 = instr.i_fmovr.i_rs1; 467 if (rs1 != 0 && (int64_t)curlwp->l_md.md_tf->tf_global[rs1] < 0) 468 return (0); /* success */ 469 rs1 = fs->fs_regs[rs2]; 470 goto mov; 471 default: 472 DPRINTF(FPE_INSN, 473 ("fpu_execute: unknown v9 FP inst %x opf %x\n", 474 instr.i_int, opf)); 475 return (NOTFPU); 476 } 477 } 478 #endif /* SUN4U */ 479 switch (opf >>= 2) { 480 481 default: 482 DPRINTF(FPE_INSN, 483 ("fpu_execute: unknown basic FP inst %x opf %x\n", 484 instr.i_int, opf)); 485 return (NOTFPU); 486 487 case FMOV >> 2: /* these should all be pretty obvious */ 488 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n")); 489 rs1 = fs->fs_regs[rs2]; 490 goto mov; 491 492 case FNEG >> 2: 493 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n")); 494 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 495 goto mov; 496 497 case FABS >> 2: 498 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 499 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 500 mov: 501 #ifndef SUN4U 502 fs->fs_regs[rd] = rs1; 503 #else /* SUN4U */ 504 i = 1<<(type-1); 505 fs->fs_regs[rd++] = rs1; 506 while (--i > 0) 507 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 508 #endif /* SUN4U */ 509 fs->fs_fsr = fe->fe_fsr; 510 return (0); /* success */ 511 512 case FSQRT >> 2: 513 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 514 fpu_explode(fe, &fe->fe_f1, type, rs2); 515 fp = fpu_sqrt(fe); 516 break; 517 518 case FADD >> 2: 519 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 520 fpu_explode(fe, &fe->fe_f1, type, rs1); 521 fpu_explode(fe, &fe->fe_f2, type, rs2); 522 fp = fpu_add(fe); 523 break; 524 525 case FSUB >> 2: 526 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 527 fpu_explode(fe, &fe->fe_f1, type, rs1); 528 fpu_explode(fe, &fe->fe_f2, type, rs2); 529 fp = fpu_sub(fe); 530 break; 531 532 case FMUL >> 2: 533 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 534 fpu_explode(fe, &fe->fe_f1, type, rs1); 535 fpu_explode(fe, &fe->fe_f2, type, rs2); 536 fp = fpu_mul(fe); 537 break; 538 539 case FDIV >> 2: 540 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 541 fpu_explode(fe, &fe->fe_f1, type, rs1); 542 fpu_explode(fe, &fe->fe_f2, type, rs2); 543 fp = fpu_div(fe); 544 break; 545 546 case FCMP >> 2: 547 DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n")); 548 fpu_explode(fe, &fe->fe_f1, type, rs1); 549 fpu_explode(fe, &fe->fe_f2, type, rs2); 550 fpu_compare(fe, 0); 551 goto cmpdone; 552 553 case FCMPE >> 2: 554 DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n")); 555 fpu_explode(fe, &fe->fe_f1, type, rs1); 556 fpu_explode(fe, &fe->fe_f2, type, rs2); 557 fpu_compare(fe, 1); 558 cmpdone: 559 /* 560 * The only possible exception here is NV; catch it 561 * early and get out, as there is no result register. 562 */ 563 cx = fe->fe_cx; 564 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 565 if (cx != 0) { 566 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 567 fs->fs_fsr = (fsr & ~FSR_FTT) | 568 (FSR_TT_IEEE << FSR_FTT_SHIFT); 569 return (FPE); 570 } 571 fsr |= FSR_NV << FSR_AX_SHIFT; 572 } 573 fs->fs_fsr = fsr; 574 return (0); 575 576 case FSMULD >> 2: 577 case FDMULX >> 2: 578 DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n")); 579 if (type == FTYPE_EXT) 580 return (NOTFPU); 581 fpu_explode(fe, &fe->fe_f1, type, rs1); 582 fpu_explode(fe, &fe->fe_f2, type, rs2); 583 type++; /* single to double, or double to quad */ 584 fp = fpu_mul(fe); 585 break; 586 587 #ifdef SUN4U 588 case FXTOS >> 2: 589 case FXTOD >> 2: 590 case FXTOQ >> 2: 591 DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n")); 592 type = FTYPE_LNG; 593 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 594 type = opf & 3; /* sneaky; depends on instruction encoding */ 595 break; 596 597 case FTOX >> 2: 598 DPRINTF(FPE_INSN, ("fpu_execute: FTOX\n")); 599 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 600 type = FTYPE_LNG; 601 /* Recalculate destination register */ 602 rd = instr.i_opf.i_rd; 603 break; 604 605 #endif /* SUN4U */ 606 case FTOI >> 2: 607 DPRINTF(FPE_INSN, ("fpu_execute: FTOI\n")); 608 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 609 type = FTYPE_INT; 610 /* Recalculate destination register */ 611 rd = instr.i_opf.i_rd; 612 break; 613 614 case FTOS >> 2: 615 case FTOD >> 2: 616 case FTOQ >> 2: 617 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 618 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 619 /* Recalculate rd with correct type info. */ 620 type = opf & 3; /* sneaky; depends on instruction encoding */ 621 mask = 0x3 >> (3 - type); 622 rd = instr.i_opf.i_rd; 623 rd = (rd & ~mask) | ((rd & mask & 0x1) << 5); 624 break; 625 } 626 627 /* 628 * ALU operation is complete. Collapse the result and then check 629 * for exceptions. If we got any, and they are enabled, do not 630 * alter the destination register, just stop with an exception. 631 * Otherwise set new current exceptions and accrue. 632 */ 633 fpu_implode(fe, fp, type, space); 634 cx = fe->fe_cx; 635 fsr = fe->fe_fsr; 636 if (cx != 0) { 637 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 638 if (cx & mask) { 639 /* not accrued??? */ 640 fs->fs_fsr = (fsr & ~FSR_FTT) | 641 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 642 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 643 return (FPE); 644 } 645 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 646 } 647 fs->fs_fsr = fsr; 648 DPRINTF(FPE_REG, ("-> %c%d\n", (type == FTYPE_LNG) ? 'x' : 649 ((type == FTYPE_INT) ? 'i' : 650 ((type == FTYPE_SNG) ? 's' : 651 ((type == FTYPE_DBL) ? 'd' : 652 ((type == FTYPE_EXT) ? 'q' : '?')))), 653 rd)); 654 fs->fs_regs[rd] = space[0]; 655 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 656 fs->fs_regs[rd + 1] = space[1]; 657 if (type > FTYPE_DBL) { 658 fs->fs_regs[rd + 2] = space[2]; 659 fs->fs_regs[rd + 3] = space[3]; 660 } 661 } 662 return (0); /* success */ 663 } 664
Indexes created Wed Sep 24 22:09:59 GMT 2025