fpu.c revision 1.7
1 /* $NetBSD: fpu.c,v 1.7 2000/06/18 06:54:17 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 #include <sys/param.h> 48 #include <sys/proc.h> 49 #include <sys/signal.h> 50 #include <sys/systm.h> 51 #include <sys/syslog.h> 52 #include <sys/signalvar.h> 53 54 #include <machine/instr.h> 55 #include <machine/reg.h> 56 57 #include <sparc/fpu/fpu_emu.h> 58 #include <sparc/fpu/fpu_extern.h> 59 60 /* 61 * fpu_execute returns the following error numbers (0 = no error): 62 */ 63 #define FPE 1 /* take a floating point exception */ 64 #define NOTFPU 2 /* not an FPU instruction */ 65 66 /* 67 * Translate current exceptions into `first' exception. The 68 * bits go the wrong way for ffs() (0x10 is most important, etc). 69 * There are only 5, so do it the obvious way. 70 */ 71 #define X1(x) x 72 #define X2(x) x,x 73 #define X4(x) x,x,x,x 74 #define X8(x) X4(x),X4(x) 75 #define X16(x) X8(x),X8(x) 76 77 static char cx_to_trapx[] = { 78 X1(FSR_NX), 79 X2(FSR_DZ), 80 X4(FSR_UF), 81 X8(FSR_OF), 82 X16(FSR_NV) 83 }; 84 static u_char fpu_codes[] = { 85 X1(FPE_FLTINEX_TRAP), 86 X2(FPE_FLTDIV_TRAP), 87 X4(FPE_FLTUND_TRAP), 88 X8(FPE_FLTOVF_TRAP), 89 X16(FPE_FLTOPERR_TRAP) 90 }; 91 92 /* 93 * The FPU gave us an exception. Clean up the mess. Note that the 94 * fp queue can only have FPops in it, never load/store FP registers 95 * nor FBfcc instructions. Experiments with `crashme' prove that 96 * unknown FPops do enter the queue, however. 97 */ 98 void 99 fpu_cleanup(p, fs) 100 register struct proc *p; 101 #ifndef SUN4U 102 register struct fpstate *fs; 103 #else /* SUN4U */ 104 register struct fpstate64 *fs; 105 #endif /* SUN4U */ 106 { 107 register int i, fsr = fs->fs_fsr, error; 108 union instr instr; 109 struct fpemu fe; 110 111 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 112 113 case FSR_TT_NONE: 114 panic("fpu_cleanup: No fault"); /* ??? */ 115 break; 116 117 case FSR_TT_IEEE: 118 /* XXX missing trap address! */ 119 if ((i = fsr & FSR_CX) == 0) 120 panic("fpu ieee trap, but no exception"); 121 trapsignal(p, SIGFPE, fpu_codes[i - 1]); 122 break; /* XXX should return, but queue remains */ 123 124 case FSR_TT_UNFIN: 125 #ifdef SUN4U 126 if (fs->fs_qsize == 0) { 127 printf("fpu_cleanup: unfinished fpop"); 128 /* The book sez reexecute or emulate. */ 129 return; 130 } 131 break; 132 133 #endif /* SUN4U */ 134 case FSR_TT_UNIMP: 135 if (fs->fs_qsize == 0) 136 panic("fpu_cleanup: unimplemented fpop"); 137 break; 138 139 case FSR_TT_SEQ: 140 panic("fpu sequence error"); 141 /* NOTREACHED */ 142 143 case FSR_TT_HWERR: 144 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 145 p->p_comm, p->p_pid); 146 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 147 trapsignal(p, SIGFPE, -1); /* ??? */ 148 goto out; 149 150 default: 151 printf("fsr=0x%x\n", fsr); 152 panic("fpu error"); 153 } 154 155 /* emulate the instructions left in the queue */ 156 fe.fe_fpstate = fs; 157 for (i = 0; i < fs->fs_qsize; i++) { 158 instr.i_int = fs->fs_queue[i].fq_instr; 159 if (instr.i_any.i_op != IOP_reg || 160 (instr.i_op3.i_op3 != IOP3_FPop1 && 161 instr.i_op3.i_op3 != IOP3_FPop2)) 162 panic("bogus fpu queue"); 163 error = fpu_execute(&fe, instr); 164 switch (error) { 165 166 case 0: 167 continue; 168 169 case FPE: 170 trapsignal(p, SIGFPE, 171 fpu_codes[(fs->fs_fsr & FSR_CX) - 1]); 172 break; 173 174 case NOTFPU: 175 #ifdef SUN4U 176 #ifdef DEBUG 177 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n", p); 178 Debugger(); 179 #endif 180 #endif /* SUN4U */ 181 trapsignal(p, SIGILL, 0); /* ??? code? */ 182 break; 183 184 default: 185 panic("fpu_cleanup 3"); 186 /* NOTREACHED */ 187 } 188 /* XXX should stop here, but queue remains */ 189 } 190 out: 191 fs->fs_qsize = 0; 192 } 193 194 #ifdef notyet 195 /* 196 * If we have no FPU at all (are there any machines like this out 197 * there!?) we have to emulate each instruction, and we need a pointer 198 * to the trapframe so that we can step over them and do FBfcc's. 199 * We know the `queue' is empty, though; we just want to emulate 200 * the instruction at tf->tf_pc. 201 */ 202 fpu_emulate(p, tf, fs) 203 struct proc *p; 204 register struct trapframe *tf; 205 #ifndef SUN4U 206 register struct fpstate *fs; 207 #else /* SUN4U */ 208 register struct fpstate64 *fs; 209 #endif /* SUN4U */ 210 { 211 212 do { 213 fetch instr from pc 214 decode 215 if (integer instr) { 216 /* 217 * We do this here, rather than earlier, to avoid 218 * losing even more badly than usual. 219 */ 220 if (p->p_addr->u_pcb.pcb_uw) { 221 write_user_windows(); 222 if (rwindow_save(p)) 223 sigexit(p, SIGILL); 224 } 225 if (loadstore) { 226 do_it; 227 pc = npc, npc += 4 228 } else if (fbfcc) { 229 do_annul_stuff; 230 } else 231 return; 232 } else if (fpu instr) { 233 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 234 error = fpu_execute(&fe, fs, instr); 235 switch (error) { 236 etc; 237 } 238 } else 239 return; 240 if (want to reschedule) 241 return; 242 } while (error == 0); 243 } 244 #endif 245 246 /* 247 * Execute an FPU instruction (one that runs entirely in the FPU; not 248 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 249 * modified to reflect the setting the hardware would have left. 250 * 251 * Note that we do not catch all illegal opcodes, so you can, for instance, 252 * multiply two integers this way. 253 */ 254 int 255 fpu_execute(fe, instr) 256 register struct fpemu *fe; 257 union instr instr; 258 { 259 register struct fpn *fp; 260 #ifndef SUN4U 261 register int opf, rs1, rs2, rd, type, mask, fsr, cx; 262 register struct fpstate *fs; 263 #else /* SUN4U */ 264 register int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 265 register struct fpstate64 *fs; 266 #endif /* SUN4U */ 267 u_int space[4]; 268 269 /* 270 * `Decode' and execute instruction. Start with no exceptions. 271 * The type of any i_opf opcode is in the bottom two bits, so we 272 * squish them out here. 273 */ 274 opf = instr.i_opf.i_opf; 275 type = opf & 3; 276 mask = "\0\0\1\3"[type]; 277 rs1 = instr.i_opf.i_rs1 & ~mask; 278 rs2 = instr.i_opf.i_rs2 & ~mask; 279 rd = instr.i_opf.i_rd & ~mask; 280 #ifdef notdef 281 if ((rs1 | rs2 | rd) & mask) 282 return (BADREG); 283 #endif 284 fs = fe->fe_fpstate; 285 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 286 fe->fe_cx = 0; 287 #ifdef SUN4U 288 /* 289 * Check to see if we're dealing with a fancy cmove and handle 290 * it first. 291 */ 292 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 293 switch (opf >>= 2) { 294 case FMVFC0 >> 2: 295 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 296 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 297 rs1 = fs->fs_regs[rs2]; 298 goto mov; 299 case FMVFC1 >> 2: 300 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 301 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 302 rs1 = fs->fs_regs[rs2]; 303 goto mov; 304 case FMVFC2 >> 2: 305 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 306 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 307 rs1 = fs->fs_regs[rs2]; 308 goto mov; 309 case FMVFC3 >> 2: 310 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 311 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 312 rs1 = fs->fs_regs[rs2]; 313 goto mov; 314 case FMVIC >> 2: 315 /* Presume we're curproc */ 316 cond = (curproc->p_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 317 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 318 rs1 = fs->fs_regs[rs2]; 319 goto mov; 320 case FMVXC >> 2: 321 /* Presume we're curproc */ 322 cond = (curproc->p_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 323 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 324 rs1 = fs->fs_regs[rs2]; 325 goto mov; 326 case FMVRZ >> 2: 327 /* Presume we're curproc */ 328 rs1 = instr.i_fmovr.i_rs1; 329 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] != 0) 330 return (0); /* success */ 331 rs1 = fs->fs_regs[rs2]; 332 goto mov; 333 case FMVRLEZ >> 2: 334 /* Presume we're curproc */ 335 rs1 = instr.i_fmovr.i_rs1; 336 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] > 0) 337 return (0); /* success */ 338 rs1 = fs->fs_regs[rs2]; 339 goto mov; 340 case FMVRLZ >> 2: 341 /* Presume we're curproc */ 342 rs1 = instr.i_fmovr.i_rs1; 343 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] >= 0) 344 return (0); /* success */ 345 rs1 = fs->fs_regs[rs2]; 346 goto mov; 347 case FMVRNZ >> 2: 348 /* Presume we're curproc */ 349 rs1 = instr.i_fmovr.i_rs1; 350 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] == 0) 351 return (0); /* success */ 352 rs1 = fs->fs_regs[rs2]; 353 goto mov; 354 case FMVRGZ >> 2: 355 /* Presume we're curproc */ 356 rs1 = instr.i_fmovr.i_rs1; 357 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] <= 0) 358 return (0); /* success */ 359 rs1 = fs->fs_regs[rs2]; 360 goto mov; 361 case FMVRGEZ >> 2: 362 /* Presume we're curproc */ 363 rs1 = instr.i_fmovr.i_rs1; 364 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] < 0) 365 return (0); /* success */ 366 rs1 = fs->fs_regs[rs2]; 367 goto mov; 368 case FCMP >> 2: 369 fpu_explode(fe, &fe->fe_f1, type, rs1); 370 fpu_explode(fe, &fe->fe_f2, type, rs2); 371 fpu_compare(fe, 0); 372 goto cmpdone; 373 374 case FCMPE >> 2: 375 fpu_explode(fe, &fe->fe_f1, type, rs1); 376 fpu_explode(fe, &fe->fe_f2, type, rs2); 377 fpu_compare(fe, 1); 378 cmpdone: 379 /* 380 * The only possible exception here is NV; catch it 381 * early and get out, as there is no result register. 382 */ 383 cx = fe->fe_cx; 384 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 385 if (cx != 0) { 386 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 387 fs->fs_fsr = (fsr & ~FSR_FTT) | 388 (FSR_TT_IEEE << FSR_FTT_SHIFT); 389 return (FPE); 390 } 391 fsr |= FSR_NV << FSR_AX_SHIFT; 392 } 393 fs->fs_fsr = fsr; 394 return (0); 395 default: 396 return (NOTFPU); 397 } 398 } 399 #endif /* SUN4U */ 400 switch (opf >>= 2) { 401 402 default: 403 return (NOTFPU); 404 405 case FMOV >> 2: /* these should all be pretty obvious */ 406 rs1 = fs->fs_regs[rs2]; 407 goto mov; 408 409 case FNEG >> 2: 410 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 411 goto mov; 412 413 case FABS >> 2: 414 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 415 mov: 416 #ifndef SUN4U 417 fs->fs_regs[rd] = rs1; 418 #else /* SUN4U */ 419 i = 1<<type; 420 fs->fs_regs[rd++] = rs1; 421 while (--i) 422 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 423 #endif /* SUN4U */ 424 fs->fs_fsr = fe->fe_fsr; 425 return (0); /* success */ 426 427 case FSQRT >> 2: 428 fpu_explode(fe, &fe->fe_f1, type, rs2); 429 fp = fpu_sqrt(fe); 430 break; 431 432 case FADD >> 2: 433 fpu_explode(fe, &fe->fe_f1, type, rs1); 434 fpu_explode(fe, &fe->fe_f2, type, rs2); 435 fp = fpu_add(fe); 436 break; 437 438 case FSUB >> 2: 439 fpu_explode(fe, &fe->fe_f1, type, rs1); 440 fpu_explode(fe, &fe->fe_f2, type, rs2); 441 fp = fpu_sub(fe); 442 break; 443 444 case FMUL >> 2: 445 fpu_explode(fe, &fe->fe_f1, type, rs1); 446 fpu_explode(fe, &fe->fe_f2, type, rs2); 447 fp = fpu_mul(fe); 448 break; 449 450 case FDIV >> 2: 451 fpu_explode(fe, &fe->fe_f1, type, rs1); 452 fpu_explode(fe, &fe->fe_f2, type, rs2); 453 fp = fpu_div(fe); 454 break; 455 456 #ifndef SUN4U 457 case FCMP >> 2: 458 fpu_explode(fe, &fe->fe_f1, type, rs1); 459 fpu_explode(fe, &fe->fe_f2, type, rs2); 460 fpu_compare(fe, 0); 461 goto cmpdone; 462 463 case FCMPE >> 2: 464 fpu_explode(fe, &fe->fe_f1, type, rs1); 465 fpu_explode(fe, &fe->fe_f2, type, rs2); 466 fpu_compare(fe, 1); 467 cmpdone: 468 /* 469 * The only possible exception here is NV; catch it 470 * early and get out, as there is no result register. 471 */ 472 cx = fe->fe_cx; 473 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 474 if (cx != 0) { 475 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 476 fs->fs_fsr = (fsr & ~FSR_FTT) | 477 (FSR_TT_IEEE << FSR_FTT_SHIFT); 478 return (FPE); 479 } 480 fsr |= FSR_NV << FSR_AX_SHIFT; 481 } 482 fs->fs_fsr = fsr; 483 return (0); 484 485 #endif /* not SUN4U */ 486 case FSMULD >> 2: 487 case FDMULX >> 2: 488 if (type == FTYPE_EXT) 489 return (NOTFPU); 490 fpu_explode(fe, &fe->fe_f1, type, rs1); 491 fpu_explode(fe, &fe->fe_f2, type, rs2); 492 type++; /* single to double, or double to quad */ 493 fp = fpu_mul(fe); 494 break; 495 496 #ifdef SUN4U 497 case FXTOS >> 2: 498 case FXTOD >> 2: 499 case FXTOQ >> 2: 500 type = FTYPE_LNG; 501 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 502 type = opf & 3; /* sneaky; depends on instruction encoding */ 503 break; 504 505 case FTOX >> 2: 506 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 507 type = FTYPE_LNG; 508 #endif /* SUN4U */ 509 510 case FTOS >> 2: 511 case FTOD >> 2: 512 #ifndef SUN4U 513 case FTOX >> 2: 514 #else /* SUN4U */ 515 case FTOQ >> 2: 516 #endif /* SUN4U */ 517 case FTOI >> 2: 518 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 519 type = opf & 3; /* sneaky; depends on instruction encoding */ 520 break; 521 } 522 523 /* 524 * ALU operation is complete. Collapse the result and then check 525 * for exceptions. If we got any, and they are enabled, do not 526 * alter the destination register, just stop with an exception. 527 * Otherwise set new current exceptions and accrue. 528 */ 529 fpu_implode(fe, fp, type, space); 530 cx = fe->fe_cx; 531 fsr = fe->fe_fsr; 532 if (cx != 0) { 533 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 534 if (cx & mask) { 535 /* not accrued??? */ 536 fs->fs_fsr = (fsr & ~FSR_FTT) | 537 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 538 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 539 return (FPE); 540 } 541 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 542 } 543 fs->fs_fsr = fsr; 544 fs->fs_regs[rd] = space[0]; 545 #ifndef SUN4U 546 if (type >= FTYPE_DBL) { 547 #else /* SUN4U */ 548 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 549 #endif /* SUN4U */ 550 fs->fs_regs[rd + 1] = space[1]; 551 if (type > FTYPE_DBL) { 552 fs->fs_regs[rd + 2] = space[2]; 553 fs->fs_regs[rd + 3] = space[3]; 554 } 555 } 556 return (0); /* success */ 557 } 558
Indexes created Wed Sep 24 15:09:51 GMT 2025