fpu.c revision 1.8
1 /* $NetBSD: fpu.c,v 1.8 2000/08/03 18:32:07 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 #include <sys/param.h> 48 #include <sys/proc.h> 49 #include <sys/signal.h> 50 #include <sys/systm.h> 51 #include <sys/syslog.h> 52 #include <sys/signalvar.h> 53 54 #include <machine/instr.h> 55 #include <machine/reg.h> 56 57 #include <sparc/fpu/fpu_emu.h> 58 #include <sparc/fpu/fpu_extern.h> 59 60 int fpe_debug = 0; 61 62 #ifdef DEBUG 63 /* 64 * Dump a `fpn' structure. 65 */ 66 void 67 fpu_dumpfpn(struct fpn *fp) 68 { 69 static char *class[] = { 70 "SNAN", "QNAN", "ZERO", "NUM", "INF" 71 }; 72 73 printf("%s %c.%x %x %x %xE%d", class[fp->fp_class + 2], 74 fp->fp_sign ? '-' : ' ', 75 fp->fp_mant[0], fp->fp_mant[1], 76 fp->fp_mant[2], fp->fp_mant[3], 77 fp->fp_exp); 78 } 79 #endif 80 81 /* 82 * fpu_execute returns the following error numbers (0 = no error): 83 */ 84 #define FPE 1 /* take a floating point exception */ 85 #define NOTFPU 2 /* not an FPU instruction */ 86 87 /* 88 * Translate current exceptions into `first' exception. The 89 * bits go the wrong way for ffs() (0x10 is most important, etc). 90 * There are only 5, so do it the obvious way. 91 */ 92 #define X1(x) x 93 #define X2(x) x,x 94 #define X4(x) x,x,x,x 95 #define X8(x) X4(x),X4(x) 96 #define X16(x) X8(x),X8(x) 97 98 static char cx_to_trapx[] = { 99 X1(FSR_NX), 100 X2(FSR_DZ), 101 X4(FSR_UF), 102 X8(FSR_OF), 103 X16(FSR_NV) 104 }; 105 static u_char fpu_codes[] = { 106 X1(FPE_FLTINEX_TRAP), 107 X2(FPE_FLTDIV_TRAP), 108 X4(FPE_FLTUND_TRAP), 109 X8(FPE_FLTOVF_TRAP), 110 X16(FPE_FLTOPERR_TRAP) 111 }; 112 113 /* 114 * The FPU gave us an exception. Clean up the mess. Note that the 115 * fp queue can only have FPops in it, never load/store FP registers 116 * nor FBfcc instructions. Experiments with `crashme' prove that 117 * unknown FPops do enter the queue, however. 118 */ 119 void 120 fpu_cleanup(p, fs) 121 register struct proc *p; 122 #ifndef SUN4U 123 register struct fpstate *fs; 124 #else /* SUN4U */ 125 register struct fpstate64 *fs; 126 #endif /* SUN4U */ 127 { 128 register int i, fsr = fs->fs_fsr, error; 129 union instr instr; 130 struct fpemu fe; 131 132 switch ((fsr >> FSR_FTT_SHIFT) & FSR_FTT_MASK) { 133 134 case FSR_TT_NONE: 135 panic("fpu_cleanup: No fault"); /* ??? */ 136 break; 137 138 case FSR_TT_IEEE: 139 /* XXX missing trap address! */ 140 if ((i = fsr & FSR_CX) == 0) 141 panic("fpu ieee trap, but no exception"); 142 trapsignal(p, SIGFPE, fpu_codes[i - 1]); 143 break; /* XXX should return, but queue remains */ 144 145 case FSR_TT_UNFIN: 146 #ifdef SUN4U 147 if (fs->fs_qsize == 0) { 148 printf("fpu_cleanup: unfinished fpop"); 149 /* The book sez reexecute or emulate. */ 150 return; 151 } 152 break; 153 154 #endif /* SUN4U */ 155 case FSR_TT_UNIMP: 156 if (fs->fs_qsize == 0) 157 panic("fpu_cleanup: unimplemented fpop"); 158 break; 159 160 case FSR_TT_SEQ: 161 panic("fpu sequence error"); 162 /* NOTREACHED */ 163 164 case FSR_TT_HWERR: 165 log(LOG_ERR, "fpu hardware error (%s[%d])\n", 166 p->p_comm, p->p_pid); 167 uprintf("%s[%d]: fpu hardware error\n", p->p_comm, p->p_pid); 168 trapsignal(p, SIGFPE, -1); /* ??? */ 169 goto out; 170 171 default: 172 printf("fsr=0x%x\n", fsr); 173 panic("fpu error"); 174 } 175 176 /* emulate the instructions left in the queue */ 177 fe.fe_fpstate = fs; 178 for (i = 0; i < fs->fs_qsize; i++) { 179 instr.i_int = fs->fs_queue[i].fq_instr; 180 if (instr.i_any.i_op != IOP_reg || 181 (instr.i_op3.i_op3 != IOP3_FPop1 && 182 instr.i_op3.i_op3 != IOP3_FPop2)) 183 panic("bogus fpu queue"); 184 error = fpu_execute(&fe, instr); 185 switch (error) { 186 187 case 0: 188 continue; 189 190 case FPE: 191 trapsignal(p, SIGFPE, 192 fpu_codes[(fs->fs_fsr & FSR_CX) - 1]); 193 break; 194 195 case NOTFPU: 196 #ifdef SUN4U 197 #ifdef DEBUG 198 printf("fpu_cleanup: not an FPU error -- sending SIGILL\n", p); 199 Debugger(); 200 #endif 201 #endif /* SUN4U */ 202 trapsignal(p, SIGILL, 0); /* ??? code? */ 203 break; 204 205 default: 206 panic("fpu_cleanup 3"); 207 /* NOTREACHED */ 208 } 209 /* XXX should stop here, but queue remains */ 210 } 211 out: 212 fs->fs_qsize = 0; 213 } 214 215 #ifdef notyet 216 /* 217 * If we have no FPU at all (are there any machines like this out 218 * there!?) we have to emulate each instruction, and we need a pointer 219 * to the trapframe so that we can step over them and do FBfcc's. 220 * We know the `queue' is empty, though; we just want to emulate 221 * the instruction at tf->tf_pc. 222 */ 223 fpu_emulate(p, tf, fs) 224 struct proc *p; 225 register struct trapframe *tf; 226 #ifndef SUN4U 227 register struct fpstate *fs; 228 #else /* SUN4U */ 229 register struct fpstate64 *fs; 230 #endif /* SUN4U */ 231 { 232 233 do { 234 fetch instr from pc 235 decode 236 if (integer instr) { 237 /* 238 * We do this here, rather than earlier, to avoid 239 * losing even more badly than usual. 240 */ 241 if (p->p_addr->u_pcb.pcb_uw) { 242 write_user_windows(); 243 if (rwindow_save(p)) 244 sigexit(p, SIGILL); 245 } 246 if (loadstore) { 247 do_it; 248 pc = npc, npc += 4 249 } else if (fbfcc) { 250 do_annul_stuff; 251 } else 252 return; 253 } else if (fpu instr) { 254 fe.fe_fsr = fs->fs_fsr &= ~FSR_CX; 255 error = fpu_execute(&fe, fs, instr); 256 switch (error) { 257 etc; 258 } 259 } else 260 return; 261 if (want to reschedule) 262 return; 263 } while (error == 0); 264 } 265 #endif 266 267 /* 268 * Execute an FPU instruction (one that runs entirely in the FPU; not 269 * FBfcc or STF, for instance). On return, fe->fe_fs->fs_fsr will be 270 * modified to reflect the setting the hardware would have left. 271 * 272 * Note that we do not catch all illegal opcodes, so you can, for instance, 273 * multiply two integers this way. 274 */ 275 int 276 fpu_execute(fe, instr) 277 register struct fpemu *fe; 278 union instr instr; 279 { 280 register struct fpn *fp; 281 #ifndef SUN4U 282 register int opf, rs1, rs2, rd, type, mask, fsr, cx; 283 register struct fpstate *fs; 284 #else /* SUN4U */ 285 register int opf, rs1, rs2, rd, type, mask, fsr, cx, i, cond; 286 register struct fpstate64 *fs; 287 #endif /* SUN4U */ 288 u_int space[4]; 289 290 /* 291 * `Decode' and execute instruction. Start with no exceptions. 292 * The type of any i_opf opcode is in the bottom two bits, so we 293 * squish them out here. 294 */ 295 opf = instr.i_opf.i_opf; 296 type = opf & 3; 297 mask = "\0\0\1\3"[type]; 298 rs1 = instr.i_opf.i_rs1 & ~mask; 299 rs2 = instr.i_opf.i_rs2 & ~mask; 300 rd = instr.i_opf.i_rd & ~mask; 301 #ifdef notdef 302 if ((rs1 | rs2 | rd) & mask) 303 return (BADREG); 304 #endif 305 fs = fe->fe_fpstate; 306 fe->fe_fsr = fs->fs_fsr & ~FSR_CX; 307 fe->fe_cx = 0; 308 #ifdef SUN4U 309 /* 310 * Check to see if we're dealing with a fancy cmove and handle 311 * it first. 312 */ 313 if (instr.i_op3.i_op3 == IOP3_FPop2 && (opf&0xff0) != (FCMP&0xff0)) { 314 switch (opf >>= 2) { 315 case FMVFC0 >> 2: 316 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC0\n")); 317 cond = (fs->fs_fsr>>FSR_FCC_SHIFT)&FSR_FCC_MASK; 318 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 319 rs1 = fs->fs_regs[rs2]; 320 goto mov; 321 case FMVFC1 >> 2: 322 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC1\n")); 323 cond = (fs->fs_fsr>>FSR_FCC1_SHIFT)&FSR_FCC_MASK; 324 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 325 rs1 = fs->fs_regs[rs2]; 326 goto mov; 327 case FMVFC2 >> 2: 328 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC2\n")); 329 cond = (fs->fs_fsr>>FSR_FCC2_SHIFT)&FSR_FCC_MASK; 330 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 331 rs1 = fs->fs_regs[rs2]; 332 goto mov; 333 case FMVFC3 >> 2: 334 DPRINTF(FPE_INSN, ("fpu_execute: FMVFC3\n")); 335 cond = (fs->fs_fsr>>FSR_FCC3_SHIFT)&FSR_FCC_MASK; 336 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 337 rs1 = fs->fs_regs[rs2]; 338 goto mov; 339 case FMVIC >> 2: 340 /* Presume we're curproc */ 341 DPRINTF(FPE_INSN, ("fpu_execute: FMVIC\n")); 342 cond = (curproc->p_md.md_tf->tf_tstate>>TSTATE_CCR_SHIFT)&PSR_ICC; 343 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 344 rs1 = fs->fs_regs[rs2]; 345 goto mov; 346 case FMVXC >> 2: 347 /* Presume we're curproc */ 348 DPRINTF(FPE_INSN, ("fpu_execute: FMVXC\n")); 349 cond = (curproc->p_md.md_tf->tf_tstate>>(TSTATE_CCR_SHIFT+XCC_SHIFT))&PSR_ICC; 350 if (instr.i_fmovcc.i_cond != cond) return(0); /* success */ 351 rs1 = fs->fs_regs[rs2]; 352 goto mov; 353 case FMVRZ >> 2: 354 /* Presume we're curproc */ 355 DPRINTF(FPE_INSN, ("fpu_execute: FMVRZ\n")); 356 rs1 = instr.i_fmovr.i_rs1; 357 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] != 0) 358 return (0); /* success */ 359 rs1 = fs->fs_regs[rs2]; 360 goto mov; 361 case FMVRLEZ >> 2: 362 /* Presume we're curproc */ 363 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLEZ\n")); 364 rs1 = instr.i_fmovr.i_rs1; 365 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] > 0) 366 return (0); /* success */ 367 rs1 = fs->fs_regs[rs2]; 368 goto mov; 369 case FMVRLZ >> 2: 370 /* Presume we're curproc */ 371 DPRINTF(FPE_INSN, ("fpu_execute: FMVRLZ\n")); 372 rs1 = instr.i_fmovr.i_rs1; 373 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] >= 0) 374 return (0); /* success */ 375 rs1 = fs->fs_regs[rs2]; 376 goto mov; 377 case FMVRNZ >> 2: 378 /* Presume we're curproc */ 379 DPRINTF(FPE_INSN, ("fpu_execute: FMVRNZ\n")); 380 rs1 = instr.i_fmovr.i_rs1; 381 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] == 0) 382 return (0); /* success */ 383 rs1 = fs->fs_regs[rs2]; 384 goto mov; 385 case FMVRGZ >> 2: 386 /* Presume we're curproc */ 387 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGZ\n")); 388 rs1 = instr.i_fmovr.i_rs1; 389 if (rs1 == 0 || (int64_t)curproc->p_md.md_tf->tf_global[rs1] <= 0) 390 return (0); /* success */ 391 rs1 = fs->fs_regs[rs2]; 392 goto mov; 393 case FMVRGEZ >> 2: 394 /* Presume we're curproc */ 395 DPRINTF(FPE_INSN, ("fpu_execute: FMVRGEZ\n")); 396 rs1 = instr.i_fmovr.i_rs1; 397 if (rs1 != 0 && (int64_t)curproc->p_md.md_tf->tf_global[rs1] < 0) 398 return (0); /* success */ 399 rs1 = fs->fs_regs[rs2]; 400 goto mov; 401 default: 402 DPRINTF(FPE_INSN, 403 ("fpu_execute: unknown v9 FP inst %x opf %x\n", 404 instr.i_int, opf)); 405 return (NOTFPU); 406 } 407 } 408 #endif /* SUN4U */ 409 switch (opf >>= 2) { 410 411 default: 412 DPRINTF(FPE_INSN, 413 ("fpu_execute: unknown basic FP inst %x opf %x\n", 414 instr.i_int, opf)); 415 return (NOTFPU); 416 417 case FMOV >> 2: /* these should all be pretty obvious */ 418 DPRINTF(FPE_INSN, ("fpu_execute: FMOV\n")); 419 rs1 = fs->fs_regs[rs2]; 420 goto mov; 421 422 case FNEG >> 2: 423 DPRINTF(FPE_INSN, ("fpu_execute: FNEG\n")); 424 rs1 = fs->fs_regs[rs2] ^ (1 << 31); 425 goto mov; 426 427 case FABS >> 2: 428 DPRINTF(FPE_INSN, ("fpu_execute: FABS\n")); 429 rs1 = fs->fs_regs[rs2] & ~(1 << 31); 430 mov: 431 #ifndef SUN4U 432 fs->fs_regs[rd] = rs1; 433 #else /* SUN4U */ 434 i = 1<<type; 435 fs->fs_regs[rd++] = rs1; 436 while (--i) 437 fs->fs_regs[rd++] = fs->fs_regs[++rs2]; 438 #endif /* SUN4U */ 439 fs->fs_fsr = fe->fe_fsr; 440 return (0); /* success */ 441 442 case FSQRT >> 2: 443 DPRINTF(FPE_INSN, ("fpu_execute: FSQRT\n")); 444 fpu_explode(fe, &fe->fe_f1, type, rs2); 445 fp = fpu_sqrt(fe); 446 break; 447 448 case FADD >> 2: 449 DPRINTF(FPE_INSN, ("fpu_execute: FADD\n")); 450 fpu_explode(fe, &fe->fe_f1, type, rs1); 451 fpu_explode(fe, &fe->fe_f2, type, rs2); 452 fp = fpu_add(fe); 453 break; 454 455 case FSUB >> 2: 456 DPRINTF(FPE_INSN, ("fpu_execute: FSUB\n")); 457 fpu_explode(fe, &fe->fe_f1, type, rs1); 458 fpu_explode(fe, &fe->fe_f2, type, rs2); 459 fp = fpu_sub(fe); 460 break; 461 462 case FMUL >> 2: 463 DPRINTF(FPE_INSN, ("fpu_execute: FMUL\n")); 464 fpu_explode(fe, &fe->fe_f1, type, rs1); 465 fpu_explode(fe, &fe->fe_f2, type, rs2); 466 fp = fpu_mul(fe); 467 break; 468 469 case FDIV >> 2: 470 DPRINTF(FPE_INSN, ("fpu_execute: FDIV\n")); 471 fpu_explode(fe, &fe->fe_f1, type, rs1); 472 fpu_explode(fe, &fe->fe_f2, type, rs2); 473 fp = fpu_div(fe); 474 break; 475 476 case FCMP >> 2: 477 DPRINTF(FPE_INSN, ("fpu_execute: FCMP\n")); 478 fpu_explode(fe, &fe->fe_f1, type, rs1); 479 fpu_explode(fe, &fe->fe_f2, type, rs2); 480 fpu_compare(fe, 0); 481 goto cmpdone; 482 483 case FCMPE >> 2: 484 DPRINTF(FPE_INSN, ("fpu_execute: FCMPE\n")); 485 fpu_explode(fe, &fe->fe_f1, type, rs1); 486 fpu_explode(fe, &fe->fe_f2, type, rs2); 487 fpu_compare(fe, 1); 488 cmpdone: 489 /* 490 * The only possible exception here is NV; catch it 491 * early and get out, as there is no result register. 492 */ 493 cx = fe->fe_cx; 494 fsr = fe->fe_fsr | (cx << FSR_CX_SHIFT); 495 if (cx != 0) { 496 if (fsr & (FSR_NV << FSR_TEM_SHIFT)) { 497 fs->fs_fsr = (fsr & ~FSR_FTT) | 498 (FSR_TT_IEEE << FSR_FTT_SHIFT); 499 return (FPE); 500 } 501 fsr |= FSR_NV << FSR_AX_SHIFT; 502 } 503 fs->fs_fsr = fsr; 504 return (0); 505 506 case FSMULD >> 2: 507 case FDMULX >> 2: 508 DPRINTF(FPE_INSN, ("fpu_execute: FSMULx\n")); 509 if (type == FTYPE_EXT) 510 return (NOTFPU); 511 fpu_explode(fe, &fe->fe_f1, type, rs1); 512 fpu_explode(fe, &fe->fe_f2, type, rs2); 513 type++; /* single to double, or double to quad */ 514 fp = fpu_mul(fe); 515 break; 516 517 #ifdef SUN4U 518 case FXTOS >> 2: 519 case FXTOD >> 2: 520 case FXTOQ >> 2: 521 DPRINTF(FPE_INSN, ("fpu_execute: FXTOx\n")); 522 type = FTYPE_LNG; 523 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 524 type = opf & 3; /* sneaky; depends on instruction encoding */ 525 break; 526 527 case FTOX >> 2: 528 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 529 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 530 type = FTYPE_LNG; 531 break; 532 #endif /* SUN4U */ 533 534 case FTOS >> 2: 535 case FTOD >> 2: 536 #ifndef SUN4U 537 case FTOX >> 2: 538 #else /* SUN4U */ 539 case FTOQ >> 2: 540 #endif /* SUN4U */ 541 case FTOI >> 2: 542 DPRINTF(FPE_INSN, ("fpu_execute: FTOx\n")); 543 fpu_explode(fe, fp = &fe->fe_f1, type, rs2); 544 type = opf & 3; /* sneaky; depends on instruction encoding */ 545 break; 546 } 547 548 /* 549 * ALU operation is complete. Collapse the result and then check 550 * for exceptions. If we got any, and they are enabled, do not 551 * alter the destination register, just stop with an exception. 552 * Otherwise set new current exceptions and accrue. 553 */ 554 fpu_implode(fe, fp, type, space); 555 cx = fe->fe_cx; 556 fsr = fe->fe_fsr; 557 if (cx != 0) { 558 mask = (fsr >> FSR_TEM_SHIFT) & FSR_TEM_MASK; 559 if (cx & mask) { 560 /* not accrued??? */ 561 fs->fs_fsr = (fsr & ~FSR_FTT) | 562 (FSR_TT_IEEE << FSR_FTT_SHIFT) | 563 (cx_to_trapx[(cx & mask) - 1] << FSR_CX_SHIFT); 564 return (FPE); 565 } 566 fsr |= (cx << FSR_CX_SHIFT) | (cx << FSR_AX_SHIFT); 567 } 568 fs->fs_fsr = fsr; 569 fs->fs_regs[rd] = space[0]; 570 if (type >= FTYPE_DBL || type == FTYPE_LNG) { 571 fs->fs_regs[rd + 1] = space[1]; 572 if (type > FTYPE_DBL) { 573 fs->fs_regs[rd + 2] = space[2]; 574 fs->fs_regs[rd + 3] = space[3]; 575 } 576 } 577 return (0); /* success */ 578 } 579
Indexes created Wed Sep 24 02:09:48 GMT 2025