fpu_subr.c revision 1.2
1 /* $NetBSD: fpu_subr.c,v 1.2 1994/11/20 20:52:47 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)fpu_subr.c 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * FPU subroutines. 49 */ 50 51 #include <sys/types.h> 52 53 #include <machine/reg.h> 54 55 #include <sparc/fpu/fpu_arith.h> 56 #include <sparc/fpu/fpu_emu.h> 57 58 /* 59 * Shift the given number right rsh bits. Any bits that `fall off' will get 60 * shoved into the sticky field; we return the resulting sticky. Note that 61 * shifting NaNs is legal (this will never shift all bits out); a NaN's 62 * sticky field is ignored anyway. 63 */ 64 int 65 fpu_shr(register struct fpn *fp, register int rsh) 66 { 67 register u_int m0, m1, m2, m3, s; 68 register int lsh; 69 70 #ifdef DIAGNOSTIC 71 if (rsh <= 0 || (fp->fp_class != FPC_NUM && !ISNAN(fp))) 72 panic("fpu_rightshift 1"); 73 #endif 74 75 m0 = fp->fp_mant[0]; 76 m1 = fp->fp_mant[1]; 77 m2 = fp->fp_mant[2]; 78 m3 = fp->fp_mant[3]; 79 80 /* If shifting all the bits out, take a shortcut. */ 81 if (rsh >= FP_NMANT) { 82 #ifdef DIAGNOSTIC 83 if ((m0 | m1 | m2 | m3) == 0) 84 panic("fpu_rightshift 2"); 85 #endif 86 fp->fp_mant[0] = 0; 87 fp->fp_mant[1] = 0; 88 fp->fp_mant[2] = 0; 89 fp->fp_mant[3] = 0; 90 #ifdef notdef 91 if ((m0 | m1 | m2 | m3) == 0) 92 fp->fp_class = FPC_ZERO; 93 else 94 #endif 95 fp->fp_sticky = 1; 96 return (1); 97 } 98 99 /* Squish out full words. */ 100 s = fp->fp_sticky; 101 if (rsh >= 32 * 3) { 102 s |= m3 | m2 | m1; 103 m3 = m0, m2 = 0, m1 = 0, m0 = 0; 104 } else if (rsh >= 32 * 2) { 105 s |= m3 | m2; 106 m3 = m1, m2 = m0, m1 = 0, m0 = 0; 107 } else if (rsh >= 32) { 108 s |= m3; 109 m3 = m2, m2 = m1, m1 = m0, m0 = 0; 110 } 111 112 /* Handle any remaining partial word. */ 113 if ((rsh &= 31) != 0) { 114 lsh = 32 - rsh; 115 s |= m3 << lsh; 116 m3 = (m3 >> rsh) | (m2 << lsh); 117 m2 = (m2 >> rsh) | (m1 << lsh); 118 m1 = (m1 >> rsh) | (m0 << lsh); 119 m0 >>= rsh; 120 } 121 fp->fp_mant[0] = m0; 122 fp->fp_mant[1] = m1; 123 fp->fp_mant[2] = m2; 124 fp->fp_mant[3] = m3; 125 fp->fp_sticky = s; 126 return (s); 127 } 128 129 /* 130 * Force a number to be normal, i.e., make its fraction have all zero 131 * bits before FP_1, then FP_1, then all 1 bits. This is used for denorms 132 * and (sometimes) for intermediate results. 133 * 134 * Internally, this may use a `supernormal' -- a number whose fp_mant 135 * is greater than or equal to 2.0 -- so as a side effect you can hand it 136 * a supernormal and it will fix it (provided fp->fp_mant[3] == 0). 137 */ 138 void 139 fpu_norm(register struct fpn *fp) 140 { 141 register u_int m0, m1, m2, m3, top, sup, nrm; 142 register int lsh, rsh, exp; 143 144 exp = fp->fp_exp; 145 m0 = fp->fp_mant[0]; 146 m1 = fp->fp_mant[1]; 147 m2 = fp->fp_mant[2]; 148 m3 = fp->fp_mant[3]; 149 150 /* Handle severe subnormals with 32-bit moves. */ 151 if (m0 == 0) { 152 if (m1) 153 m0 = m1, m1 = m2, m2 = m3, m3 = 0, exp -= 32; 154 else if (m2) 155 m0 = m2, m1 = m3, m2 = 0, m3 = 0, exp -= 2 * 32; 156 else if (m3) 157 m0 = m3, m1 = 0, m2 = 0, m3 = 0, exp -= 3 * 32; 158 else { 159 fp->fp_class = FPC_ZERO; 160 return; 161 } 162 } 163 164 /* Now fix any supernormal or remaining subnormal. */ 165 nrm = FP_1; 166 sup = nrm << 1; 167 if (m0 >= sup) { 168 /* 169 * We have a supernormal number. We need to shift it right. 170 * We may assume m3==0. 171 */ 172 for (rsh = 1, top = m0 >> 1; top >= sup; rsh++) /* XXX slow */ 173 top >>= 1; 174 exp += rsh; 175 lsh = 32 - rsh; 176 m3 = m2 << lsh; 177 m2 = (m2 >> rsh) | (m1 << lsh); 178 m1 = (m1 >> rsh) | (m0 << lsh); 179 m0 = top; 180 } else if (m0 < nrm) { 181 /* 182 * We have a regular denorm (a subnormal number), and need 183 * to shift it left. 184 */ 185 for (lsh = 1, top = m0 << 1; top < nrm; lsh++) /* XXX slow */ 186 top <<= 1; 187 exp -= lsh; 188 rsh = 32 - lsh; 189 m0 = top | (m1 >> rsh); 190 m1 = (m1 << lsh) | (m2 >> rsh); 191 m2 = (m2 << lsh) | (m3 >> rsh); 192 m3 <<= lsh; 193 } 194 195 fp->fp_exp = exp; 196 fp->fp_mant[0] = m0; 197 fp->fp_mant[1] = m1; 198 fp->fp_mant[2] = m2; 199 fp->fp_mant[3] = m3; 200 } 201 202 /* 203 * Concoct a `fresh' Quiet NaN per Appendix N. 204 * As a side effect, we set NV (invalid) for the current exceptions. 205 */ 206 struct fpn * 207 fpu_newnan(register struct fpemu *fe) 208 { 209 register struct fpn *fp; 210 211 fe->fe_cx = FSR_NV; 212 fp = &fe->fe_f3; 213 fp->fp_class = FPC_QNAN; 214 fp->fp_sign = 0; 215 fp->fp_mant[0] = FP_1 - 1; 216 fp->fp_mant[1] = fp->fp_mant[2] = fp->fp_mant[3] = ~0; 217 return (fp); 218 } 219
Indexes created Wed Sep 24 02:09:48 GMT 2025