cpu.h revision 1.28
1 /* $NetBSD: cpu.h,v 1.28 1998/09/26 20:12:06 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_MAXID 1 /* no valid machdep ids */ 54 55 #define CTL_MACHDEP_NAMES { \ 56 { 0, 0 }, \ 57 } 58 59 #ifdef _KERNEL 60 /* 61 * Exported definitions unique to SPARC cpu support. 62 */ 63 64 #include <machine/psl.h> 65 #include <sparc/sparc/intreg.h> 66 67 /* 68 * definitions of cpu-dependent requirements 69 * referenced in generic code 70 */ 71 #define cpu_swapin(p) /* nothing */ 72 #define cpu_swapout(p) /* nothing */ 73 #define cpu_wait(p) /* nothing */ 74 75 /* 76 * Arguments to hardclock, softclock and gatherstats encapsulate the 77 * previous machine state in an opaque clockframe. The ipl is here 78 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 79 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 80 */ 81 struct clockframe { 82 u_int psr; /* psr before interrupt, excluding PSR_ET */ 83 u_int pc; /* pc at interrupt */ 84 u_int npc; /* npc at interrupt */ 85 u_int ipl; /* actual interrupt priority level */ 86 u_int fp; /* %fp at interrupt */ 87 }; 88 typedef struct clockframe clockframe; 89 90 extern int eintstack[]; 91 92 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 93 #define CLKF_BASEPRI(framep) (((framep)->psr & PSR_PIL) == 0) 94 #define CLKF_PC(framep) ((framep)->pc) 95 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 96 97 /* 98 * Software interrupt request `register'. 99 */ 100 extern union sir { 101 int sir_any; 102 char sir_which[4]; 103 } sir; 104 105 #define SIR_NET 0 106 #define SIR_CLOCK 1 107 108 #if defined(SUN4M) 109 extern void raise __P((int, int)); 110 #if !(defined(SUN4) || defined(SUN4C)) 111 #define setsoftint() raise(0,1) 112 #else /* both defined */ 113 #define setsoftint() (cputyp == CPU_SUN4M ? raise(0,1) : ienab_bis(IE_L1)) 114 #endif /* !4,!4c */ 115 #else /* 4m not defined */ 116 #define setsoftint() ienab_bis(IE_L1) 117 #endif /* SUN4M */ 118 119 #define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint()) 120 #define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 121 122 extern int want_ast; 123 124 /* 125 * Preempt the current process if in interrupt from user mode, 126 * or after the current trap/syscall if in system mode. 127 */ 128 extern int want_resched; /* resched() was called */ 129 #define need_resched() (want_resched = 1, want_ast = 1) 130 131 /* 132 * Give a profiling tick to the current process when the user profiling 133 * buffer pages are invalid. On the sparc, request an ast to send us 134 * through trap(), marking the proc as needing a profiling tick. 135 */ 136 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 137 138 /* 139 * Notify the current process (p) that it has a signal pending, 140 * process as soon as possible. 141 */ 142 #define signotify(p) (want_ast = 1) 143 144 /* Number of CPUs in the system */ 145 extern int ncpu; 146 147 /* 148 * Only one process may own the FPU state. 149 * 150 * XXX this must be per-cpu (eventually) 151 */ 152 extern struct proc *fpproc; /* FPU owner */ 153 extern int foundfpu; /* true => we have an FPU */ 154 155 /* 156 * Interrupt handler chains. Interrupt handlers should return 0 for 157 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 158 * handler into the list. The handler is called with its (single) 159 * argument, or with a pointer to a clockframe if ih_arg is NULL. 160 */ 161 extern struct intrhand { 162 int (*ih_fun) __P((void *)); 163 void *ih_arg; 164 struct intrhand *ih_next; 165 } *intrhand[15]; 166 167 void intr_establish __P((int level, struct intrhand *)); 168 169 /* 170 * intr_fasttrap() is a lot like intr_establish, but is used for ``fast'' 171 * interrupt vectors (vectors that are not shared and are handled in the 172 * trap window). Such functions must be written in assembly. 173 */ 174 void intr_fasttrap __P((int level, void (*vec)(void))); 175 176 /* disksubr.c */ 177 struct dkbad; 178 int isbad __P((struct dkbad *bt, int, int, int)); 179 /* machdep.c */ 180 int ldcontrolb __P((caddr_t)); 181 void dumpconf __P((void)); 182 caddr_t reserve_dumppages __P((caddr_t)); 183 /* clock.c */ 184 struct timeval; 185 void lo_microtime __P((struct timeval *)); 186 int statintr __P((void *)); 187 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 188 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 189 /* locore.s */ 190 struct fpstate; 191 void savefpstate __P((struct fpstate *)); 192 void loadfpstate __P((struct fpstate *)); 193 int probeget __P((caddr_t, int)); 194 void write_all_windows __P((void)); 195 void write_user_windows __P((void)); 196 void proc_trampoline __P((void)); 197 struct pcb; 198 void snapshot __P((struct pcb *)); 199 struct frame *getfp __P((void)); 200 int xldcontrolb __P((caddr_t, struct pcb *)); 201 void copywords __P((const void *, void *, size_t)); 202 void qcopy __P((const void *, void *, size_t)); 203 void qzero __P((void *, size_t)); 204 /* locore2.c */ 205 void remrunqueue __P((struct proc *)); 206 /* trap.c */ 207 void kill_user_windows __P((struct proc *)); 208 int rwindow_save __P((struct proc *)); 209 void child_return __P((struct proc *)); 210 /* amd7930intr.s */ 211 void amd7930_trap __P((void)); 212 /* cons.c */ 213 int cnrom __P((void)); 214 /* zs.c */ 215 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 216 #ifdef KGDB 217 void zs_kgdb_init __P((void)); 218 #endif 219 /* fb.c */ 220 void fb_unblank __P((void)); 221 /* cache.c */ 222 void cache_flush __P((caddr_t, u_int)); 223 /* kgdb_stub.c */ 224 #ifdef KGDB 225 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 226 void kgdb_connect __P((int)); 227 void kgdb_panic __P((void)); 228 #endif 229 /* vm_machdep.c */ 230 void cpu_set_kpc __P((struct proc *, void (*)(struct proc *))); 231 /* emul.c */ 232 struct trapframe; 233 int fixalign __P((struct proc *, struct trapframe *)); 234 int emulinstr __P((int, struct trapframe *)); 235 /* cpu.c */ 236 void mp_pause_cpus __P((void)); 237 void mp_resume_cpus __P((void)); 238 void mp_halt_cpus __P((void)); 239 240 /* 241 * 242 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 243 * of the trap vector table. The next eight bits are supplied by the 244 * hardware when the trap occurs, and the bottom four bits are always 245 * zero (so that we can shove up to 16 bytes of executable code---exactly 246 * four instructions---into each trap vector). 247 * 248 * The hardware allocates half the trap vectors to hardware and half to 249 * software. 250 * 251 * Traps have priorities assigned (lower number => higher priority). 252 */ 253 254 struct trapvec { 255 int tv_instr[4]; /* the four instructions */ 256 }; 257 extern struct trapvec *trapbase; /* the 256 vectors */ 258 259 extern void wzero __P((void *, u_int)); 260 extern void wcopy __P((const void *, void *, u_int)); 261 262 #endif /* _KERNEL */ 263 #endif /* _CPU_H_ */ 264
Indexes created Sat Sep 20 22:09:52 GMT 2025