cpu.h revision 1.37
1 /* $NetBSD: cpu.h,v 1.37 2000/05/31 05:28:26 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_MAXID 2 /* number of valid machdep ids */ 55 56 #define CTL_MACHDEP_NAMES { \ 57 { 0, 0 }, \ 58 { "booted_kernel", CTLTYPE_STRING }, \ 59 } 60 61 #ifdef _KERNEL 62 /* 63 * Exported definitions unique to SPARC cpu support. 64 */ 65 66 #if !defined(_LKM) 67 #include "opt_multiprocessor.h" 68 #include "opt_lockdebug.h" 69 #endif 70 71 #include <machine/psl.h> 72 #include <sparc/sparc/cpuvar.h> 73 #include <sparc/sparc/intreg.h> 74 75 /* 76 * definitions of cpu-dependent requirements 77 * referenced in generic code 78 */ 79 #define curcpu() (cpuinfo.ci_self) 80 #define curproc (curcpu()->ci_curproc) 81 82 #define cpu_swapin(p) /* nothing */ 83 #define cpu_swapout(p) /* nothing */ 84 #define cpu_wait(p) /* nothing */ 85 #define cpu_number() (cpuinfo.cpu_no) 86 87 #if defined(MULTIPROCESSOR) 88 void cpu_boot_secondary_processors __P((void)); 89 #endif 90 91 /* 92 * Arguments to hardclock, softclock and gatherstats encapsulate the 93 * previous machine state in an opaque clockframe. The ipl is here 94 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 95 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 96 */ 97 struct clockframe { 98 u_int psr; /* psr before interrupt, excluding PSR_ET */ 99 u_int pc; /* pc at interrupt */ 100 u_int npc; /* npc at interrupt */ 101 u_int ipl; /* actual interrupt priority level */ 102 u_int fp; /* %fp at interrupt */ 103 }; 104 typedef struct clockframe clockframe; 105 106 extern int eintstack[]; 107 108 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 109 #define CLKF_BASEPRI(framep) (((framep)->psr & PSR_PIL) == 0) 110 #define CLKF_PC(framep) ((framep)->pc) 111 #if defined(MULTIPROCESSOR) 112 #define CLKF_INTR(framep) \ 113 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 114 (framep)->fp < (u_int)cpuinfo.eintstack) 115 #else 116 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 117 #endif 118 119 /* 120 * Software interrupt request `register'. 121 */ 122 extern union sir { 123 int sir_any; 124 char sir_which[4]; 125 } sir; 126 127 #define SIR_NET 0 128 #define SIR_CLOCK 1 129 #define SIR_SERIAL 2 130 131 #if defined(SUN4M) 132 extern void raise __P((int, int)); 133 #if !(defined(SUN4) || defined(SUN4C)) 134 #define setsoftint() raise(0,1) 135 #else /* both defined */ 136 #define setsoftint() (cputyp == CPU_SUN4M ? raise(0,1) : ienab_bis(IE_L1)) 137 #endif /* !4,!4c */ 138 #else /* 4m not defined */ 139 #define setsoftint() ienab_bis(IE_L1) 140 #endif /* SUN4M */ 141 142 #define setsoftnet() (sir.sir_which[SIR_NET] = 1, setsoftint()) 143 #define setsoftclock() (sir.sir_which[SIR_CLOCK] = 1, setsoftint()) 144 #define setsoftserial() (sir.sir_which[SIR_SERIAL] = 1, setsoftint()) 145 146 extern int want_ast; 147 148 /* 149 * Preempt the current process if in interrupt from user mode, 150 * or after the current trap/syscall if in system mode. 151 */ 152 extern int want_resched; /* resched() was called */ 153 #define need_resched() (want_resched = 1, want_ast = 1) 154 155 /* 156 * Give a profiling tick to the current process when the user profiling 157 * buffer pages are invalid. On the sparc, request an ast to send us 158 * through trap(), marking the proc as needing a profiling tick. 159 */ 160 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 161 162 /* 163 * Notify the current process (p) that it has a signal pending, 164 * process as soon as possible. 165 */ 166 #define signotify(p) (want_ast = 1) 167 168 /* Number of CPUs in the system */ 169 extern int ncpu; 170 171 /* 172 * Only one process may own the FPU state. 173 * 174 * XXX this must be per-cpu (eventually) 175 */ 176 extern struct proc *fpproc; /* FPU owner */ 177 extern int foundfpu; /* true => we have an FPU */ 178 179 /* 180 * Interrupt handler chains. Interrupt handlers should return 0 for 181 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 182 * handler into the list. The handler is called with its (single) 183 * argument, or with a pointer to a clockframe if ih_arg is NULL. 184 */ 185 extern struct intrhand { 186 int (*ih_fun) __P((void *)); 187 void *ih_arg; 188 struct intrhand *ih_next; 189 } *intrhand[15]; 190 191 void intr_establish __P((int level, struct intrhand *)); 192 193 /* 194 * intr_fasttrap() is a lot like intr_establish, but is used for ``fast'' 195 * interrupt vectors (vectors that are not shared and are handled in the 196 * trap window). Such functions must be written in assembly. 197 */ 198 void intr_fasttrap __P((int level, void (*vec)(void))); 199 200 /* disksubr.c */ 201 struct dkbad; 202 int isbad __P((struct dkbad *bt, int, int, int)); 203 /* machdep.c */ 204 int ldcontrolb __P((caddr_t)); 205 void dumpconf __P((void)); 206 caddr_t reserve_dumppages __P((caddr_t)); 207 /* clock.c */ 208 struct timeval; 209 void lo_microtime __P((struct timeval *)); 210 int statintr __P((void *)); 211 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 212 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 213 /* locore.s */ 214 struct fpstate; 215 void savefpstate __P((struct fpstate *)); 216 void loadfpstate __P((struct fpstate *)); 217 int probeget __P((caddr_t, int)); 218 void write_all_windows __P((void)); 219 void write_user_windows __P((void)); 220 void proc_trampoline __P((void)); 221 struct pcb; 222 void snapshot __P((struct pcb *)); 223 struct frame *getfp __P((void)); 224 int xldcontrolb __P((caddr_t, struct pcb *)); 225 void copywords __P((const void *, void *, size_t)); 226 void qcopy __P((const void *, void *, size_t)); 227 void qzero __P((void *, size_t)); 228 /* locore2.c */ 229 void remrunqueue __P((struct proc *)); 230 /* trap.c */ 231 void kill_user_windows __P((struct proc *)); 232 int rwindow_save __P((struct proc *)); 233 void child_return __P((void *)); 234 /* amd7930intr.s */ 235 void amd7930_trap __P((void)); 236 /* cons.c */ 237 int cnrom __P((void)); 238 /* zs.c */ 239 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 240 #ifdef KGDB 241 void zs_kgdb_init __P((void)); 242 #endif 243 /* fb.c */ 244 void fb_unblank __P((void)); 245 /* cache.c */ 246 void cache_flush __P((caddr_t, u_int)); 247 /* kgdb_stub.c */ 248 #ifdef KGDB 249 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 250 void kgdb_connect __P((int)); 251 void kgdb_panic __P((void)); 252 #endif 253 /* emul.c */ 254 struct trapframe; 255 int fixalign __P((struct proc *, struct trapframe *)); 256 int emulinstr __P((int, struct trapframe *)); 257 /* cpu.c */ 258 void mp_pause_cpus __P((void)); 259 void mp_resume_cpus __P((void)); 260 void mp_halt_cpus __P((void)); 261 262 /* 263 * 264 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 265 * of the trap vector table. The next eight bits are supplied by the 266 * hardware when the trap occurs, and the bottom four bits are always 267 * zero (so that we can shove up to 16 bytes of executable code---exactly 268 * four instructions---into each trap vector). 269 * 270 * The hardware allocates half the trap vectors to hardware and half to 271 * software. 272 * 273 * Traps have priorities assigned (lower number => higher priority). 274 */ 275 276 struct trapvec { 277 int tv_instr[4]; /* the four instructions */ 278 }; 279 extern struct trapvec *trapbase; /* the 256 vectors */ 280 281 extern void wzero __P((void *, u_int)); 282 extern void wcopy __P((const void *, void *, u_int)); 283 284 #endif /* _KERNEL */ 285 #endif /* _CPU_H_ */ 286
Indexes created Sun Sep 21 19:09:51 GMT 2025