cpu.h revision 1.53
1 /* $NetBSD: cpu.h,v 1.53 2002/12/09 16:13:58 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 45 */ 46 47 #ifndef _CPU_H_ 48 #define _CPU_H_ 49 50 /* 51 * CTL_MACHDEP definitions. 52 */ 53 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 54 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 55 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 56 #define CPU_ARCH 4 /* integer: cpu architecture version */ 57 #define CPU_MAXID 5 /* number of valid machdep ids */ 58 59 #define CTL_MACHDEP_NAMES { \ 60 { 0, 0 }, \ 61 { "booted_kernel", CTLTYPE_STRING }, \ 62 { "booted_device", CTLTYPE_STRING }, \ 63 { "boot_args", CTLTYPE_STRING }, \ 64 { "cpu_arch", CTLTYPE_INT }, \ 65 } 66 67 #ifdef _KERNEL 68 /* 69 * Exported definitions unique to SPARC cpu support. 70 */ 71 72 #if !defined(_LKM) && defined(_KERNEL_OPT) 73 #include "opt_multiprocessor.h" 74 #include "opt_lockdebug.h" 75 #include "opt_sparc_arch.h" 76 #endif 77 78 #include <machine/intr.h> 79 #include <machine/psl.h> 80 #include <sparc/sparc/cpuvar.h> 81 #include <sparc/sparc/intreg.h> 82 83 /* 84 * definitions of cpu-dependent requirements 85 * referenced in generic code 86 */ 87 #define curcpu() (cpuinfo.ci_self) 88 #define curproc (curcpu()->ci_curproc) 89 #define CPU_IS_PRIMARY(ci) ((ci)->master) 90 91 #define cpu_swapin(p) /* nothing */ 92 #define cpu_swapout(p) /* nothing */ 93 #define cpu_wait(p) /* nothing */ 94 #define cpu_number() (cpuinfo.ci_cpuid) 95 96 #if defined(MULTIPROCESSOR) 97 void cpu_boot_secondary_processors __P((void)); 98 #endif 99 100 /* 101 * Arguments to hardclock, softclock and gatherstats encapsulate the 102 * previous machine state in an opaque clockframe. The ipl is here 103 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 104 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 105 */ 106 struct clockframe { 107 u_int psr; /* psr before interrupt, excluding PSR_ET */ 108 u_int pc; /* pc at interrupt */ 109 u_int npc; /* npc at interrupt */ 110 u_int ipl; /* actual interrupt priority level */ 111 u_int fp; /* %fp at interrupt */ 112 }; 113 typedef struct clockframe clockframe; 114 115 extern int eintstack[]; 116 117 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 118 #define CLKF_BASEPRI(framep) (((framep)->psr & PSR_PIL) == 0) 119 #define CLKF_PC(framep) ((framep)->pc) 120 #if defined(MULTIPROCESSOR) 121 #define CLKF_INTR(framep) \ 122 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 123 (framep)->fp < (u_int)cpuinfo.eintstack) 124 #else 125 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 126 #endif 127 128 void softintr_init __P((void)); 129 void *softnet_cookie; 130 131 #define setsoftnet() softintr_schedule(softnet_cookie); 132 133 extern int want_ast; 134 135 /* 136 * Preempt the current process if in interrupt from user mode, 137 * or after the current trap/syscall if in system mode. 138 */ 139 extern int want_resched; /* resched() was called */ 140 #define need_resched(ci) (want_resched = 1, want_ast = 1) 141 142 /* 143 * Give a profiling tick to the current process when the user profiling 144 * buffer pages are invalid. On the sparc, request an ast to send us 145 * through trap(), marking the proc as needing a profiling tick. 146 */ 147 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, want_ast = 1) 148 149 /* 150 * Notify the current process (p) that it has a signal pending, 151 * process as soon as possible. 152 */ 153 #define signotify(p) (want_ast = 1) 154 155 /* CPU architecture version */ 156 extern int cpu_arch; 157 158 /* Number of CPUs in the system */ 159 extern int ncpu; 160 161 /* 162 * Only one process may own the FPU state. 163 * 164 * XXX this must be per-cpu (eventually) 165 */ 166 extern struct proc *fpproc; /* FPU owner */ 167 extern int foundfpu; /* true => we have an FPU */ 168 169 /* 170 * Interrupt handler chains. Interrupt handlers should return 0 for 171 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 172 * handler into the list. The handler is called with its (single) 173 * argument, or with a pointer to a clockframe if ih_arg is NULL. 174 */ 175 extern struct intrhand { 176 int (*ih_fun) __P((void *)); 177 void *ih_arg; 178 struct intrhand *ih_next; 179 int ih_classipl; 180 } *intrhand[15]; 181 182 void intr_establish __P((int level, int classipl, struct intrhand *)); 183 void intr_disestablish __P((int level, struct intrhand *)); 184 185 /* 186 * intr_fasttrap() is a lot like intr_establish, but is used for ``fast'' 187 * interrupt vectors (vectors that are not shared and are handled in the 188 * trap window). Such functions must be written in assembly. 189 */ 190 void intr_fasttrap __P((int level, void (*vec)(void))); 191 192 void intr_lock_kernel __P((void)); 193 void intr_unlock_kernel __P((void)); 194 195 /* disksubr.c */ 196 struct dkbad; 197 int isbad __P((struct dkbad *bt, int, int, int)); 198 /* machdep.c */ 199 int ldcontrolb __P((caddr_t)); 200 void dumpconf __P((void)); 201 caddr_t reserve_dumppages __P((caddr_t)); 202 /* clock.c */ 203 struct timeval; 204 void lo_microtime __P((struct timeval *)); 205 int clockintr __P((void *));/* level 10 (clock) interrupt code */ 206 int statintr __P((void *)); /* level 14 (statclock) interrupt code */ 207 /* locore.s */ 208 struct fpstate; 209 void savefpstate __P((struct fpstate *)); 210 void loadfpstate __P((struct fpstate *)); 211 int probeget __P((caddr_t, int)); 212 void write_all_windows __P((void)); 213 void write_user_windows __P((void)); 214 void proc_trampoline __P((void)); 215 void switchexit __P((struct proc *)); 216 struct pcb; 217 void snapshot __P((struct pcb *)); 218 struct frame *getfp __P((void)); 219 int xldcontrolb __P((caddr_t, struct pcb *)); 220 void copywords __P((const void *, void *, size_t)); 221 void qcopy __P((const void *, void *, size_t)); 222 void qzero __P((void *, size_t)); 223 /* trap.c */ 224 void kill_user_windows __P((struct proc *)); 225 int rwindow_save __P((struct proc *)); 226 /* amd7930intr.s */ 227 void amd7930_trap __P((void)); 228 /* cons.c */ 229 int cnrom __P((void)); 230 /* zs.c */ 231 void zsconsole __P((struct tty *, int, int, void (**)(struct tty *, int))); 232 #ifdef KGDB 233 void zs_kgdb_init __P((void)); 234 #endif 235 /* fb.c */ 236 void fb_unblank __P((void)); 237 /* cache.c */ 238 void cache_flush __P((caddr_t, u_int)); 239 /* kgdb_stub.c */ 240 #ifdef KGDB 241 void kgdb_attach __P((int (*)(void *), void (*)(void *, int), void *)); 242 void kgdb_connect __P((int)); 243 void kgdb_panic __P((void)); 244 #endif 245 /* emul.c */ 246 struct trapframe; 247 int fixalign __P((struct proc *, struct trapframe *)); 248 int emulinstr __P((int, struct trapframe *)); 249 /* cpu.c */ 250 void mp_pause_cpus __P((void)); 251 void mp_resume_cpus __P((void)); 252 void mp_halt_cpus __P((void)); 253 /* msiiep.c */ 254 void msiiep_swap_endian __P((int)); 255 256 /* 257 * 258 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 259 * of the trap vector table. The next eight bits are supplied by the 260 * hardware when the trap occurs, and the bottom four bits are always 261 * zero (so that we can shove up to 16 bytes of executable code---exactly 262 * four instructions---into each trap vector). 263 * 264 * The hardware allocates half the trap vectors to hardware and half to 265 * software. 266 * 267 * Traps have priorities assigned (lower number => higher priority). 268 */ 269 270 struct trapvec { 271 int tv_instr[4]; /* the four instructions */ 272 }; 273 extern struct trapvec *trapbase; /* the 256 vectors */ 274 275 extern void wzero __P((void *, u_int)); 276 extern void wcopy __P((const void *, void *, u_int)); 277 278 #endif /* _KERNEL */ 279 #endif /* _CPU_H_ */ 280
Indexes created Sat Oct 11 19:10:01 GMT 2025