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cpu.h revision 1.65
      1 /*	$NetBSD: cpu.h,v 1.65 2003/11/08 15:19:20 tsutsui Exp $ */
      2 
      3 /*
      4  * Copyright (c) 1992, 1993
      5  *	The Regents of the University of California.  All rights reserved.
      6  *
      7  * This software was developed by the Computer Systems Engineering group
      8  * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
      9  * contributed to Berkeley.
     10  *
     11  * All advertising materials mentioning features or use of this software
     12  * must display the following acknowledgement:
     13  *	This product includes software developed by the University of
     14  *	California, Lawrence Berkeley Laboratory.
     15  *
     16  * Redistribution and use in source and binary forms, with or without
     17  * modification, are permitted provided that the following conditions
     18  * are met:
     19  * 1. Redistributions of source code must retain the above copyright
     20  *    notice, this list of conditions and the following disclaimer.
     21  * 2. Redistributions in binary form must reproduce the above copyright
     22  *    notice, this list of conditions and the following disclaimer in the
     23  *    documentation and/or other materials provided with the distribution.
     24  * 3. Neither the name of the University nor the names of its contributors
     25  *    may be used to endorse or promote products derived from this software
     26  *    without specific prior written permission.
     27  *
     28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38  * SUCH DAMAGE.
     39  *
     40  *	@(#)cpu.h	8.4 (Berkeley) 1/5/94
     41  */
     42 
     43 #ifndef _CPU_H_
     44 #define _CPU_H_
     45 
     46 /*
     47  * CTL_MACHDEP definitions.
     48  */
     49 #define	CPU_BOOTED_KERNEL	1	/* string: booted kernel name */
     50 #define	CPU_BOOTED_DEVICE	2	/* string: device booted from */
     51 #define	CPU_BOOT_ARGS		3	/* string: args booted with */
     52 #define	CPU_ARCH		4	/* integer: cpu architecture version */
     53 #define	CPU_MAXID		5	/* number of valid machdep ids */
     54 
     55 #define	CTL_MACHDEP_NAMES {			\
     56 	{ 0, 0 },				\
     57 	{ "booted_kernel", CTLTYPE_STRING },	\
     58 	{ "booted_device", CTLTYPE_STRING },	\
     59 	{ "boot_args", CTLTYPE_STRING },	\
     60 	{ "cpu_arch", CTLTYPE_INT },		\
     61 }
     62 
     63 #ifdef _KERNEL
     64 /*
     65  * Exported definitions unique to SPARC cpu support.
     66  */
     67 
     68 #if defined(_KERNEL_OPT)
     69 #include "opt_multiprocessor.h"
     70 #include "opt_lockdebug.h"
     71 #include "opt_sparc_arch.h"
     72 #endif
     73 
     74 #include <machine/intr.h>
     75 #include <machine/psl.h>
     76 #include <sparc/sparc/cpuvar.h>
     77 #include <sparc/sparc/intreg.h>
     78 
     79 /*
     80  * definitions of cpu-dependent requirements
     81  * referenced in generic code
     82  */
     83 #define	curcpu()		(cpuinfo.ci_self)
     84 #define	curlwp			(cpuinfo.ci_curlwp)
     85 #define	CPU_IS_PRIMARY(ci)	((ci)->master)
     86 
     87 #define	cpu_swapin(p)		/* nothing */
     88 #define	cpu_swapout(p)		/* nothing */
     89 #define	cpu_wait(p)		/* nothing */
     90 #define	cpu_number()		(cpuinfo.ci_cpuid)
     91 #define	cpu_proc_fork(p1, p2)	/* nothing */
     92 
     93 #if defined(MULTIPROCESSOR)
     94 void	cpu_boot_secondary_processors __P((void));
     95 #endif
     96 
     97 /*
     98  * Arguments to hardclock, softclock and statclock encapsulate the
     99  * previous machine state in an opaque clockframe.  The ipl is here
    100  * as well for strayintr (see locore.s:interrupt and intr.c:strayintr).
    101  * Note that CLKF_INTR is valid only if CLKF_USERMODE is false.
    102  */
    103 struct clockframe {
    104 	u_int	psr;		/* psr before interrupt, excluding PSR_ET */
    105 	u_int	pc;		/* pc at interrupt */
    106 	u_int	npc;		/* npc at interrupt */
    107 	u_int	ipl;		/* actual interrupt priority level */
    108 	u_int	fp;		/* %fp at interrupt */
    109 };
    110 typedef struct clockframe clockframe;
    111 
    112 extern int eintstack[];
    113 
    114 #define	CLKF_USERMODE(framep)	(((framep)->psr & PSR_PS) == 0)
    115 #define	CLKF_BASEPRI(framep)	(((framep)->psr & PSR_PIL) == 0)
    116 #define	CLKF_LOPRI(framep,n)	(((framep)->psr & PSR_PIL) < (n) << 8)
    117 #define	CLKF_PC(framep)		((framep)->pc)
    118 #if defined(MULTIPROCESSOR)
    119 #define	CLKF_INTR(framep)						\
    120 	((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE &&	\
    121 	 (framep)->fp < (u_int)cpuinfo.eintstack)
    122 #else
    123 #define	CLKF_INTR(framep)	((framep)->fp < (u_int)eintstack)
    124 #endif
    125 
    126 void	softintr_init __P((void));
    127 void	*softnet_cookie;
    128 
    129 #define setsoftnet()	softintr_schedule(softnet_cookie);
    130 
    131 /*
    132  * Preempt the current process on the target CPU if in interrupt from
    133  * user mode, or after the current trap/syscall if in system mode.
    134  */
    135 #define need_resched(ci) do {						\
    136 	(ci)->want_resched = 1;						\
    137 	(ci)->want_ast = 1;						\
    138 									\
    139 	/* Just interrupt the target CPU, so it can notice its AST */	\
    140 	if ((ci)->ci_cpuid != cpu_number())				\
    141 		XCALL0(sparc_noop, 1U << (ci)->ci_cpuid);		\
    142 } while(0)
    143 
    144 /*
    145  * Give a profiling tick to the current process when the user profiling
    146  * buffer pages are invalid.  On the sparc, request an ast to send us
    147  * through trap(), marking the proc as needing a profiling tick.
    148  */
    149 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, cpuinfo.want_ast = 1)
    150 
    151 /*
    152  * Notify the current process (p) that it has a signal pending,
    153  * process as soon as possible.
    154  */
    155 #define	signotify(p)		(cpuinfo.want_ast = 1)
    156 
    157 /* CPU architecture version */
    158 extern int cpu_arch;
    159 
    160 /* Number of CPUs in the system */
    161 extern int ncpu;
    162 
    163 /*
    164  * Interrupt handler chains.  Interrupt handlers should return 0 for
    165  * ``not me'' or 1 (``I took care of it'').  intr_establish() inserts a
    166  * handler into the list.  The handler is called with its (single)
    167  * argument, or with a pointer to a clockframe if ih_arg is NULL.
    168  */
    169 extern struct intrhand {
    170 	int	(*ih_fun)(void *);
    171 	void	*ih_arg;
    172 	struct	intrhand *ih_next;
    173 	int	ih_classipl;
    174 } *intrhand[15];
    175 
    176 void	intr_establish(int level, int classipl, struct intrhand *,
    177 			void (*fastvec)(void));
    178 void	intr_disestablish(int level, struct intrhand *);
    179 
    180 void	intr_lock_kernel(void);
    181 void	intr_unlock_kernel(void);
    182 
    183 /* disksubr.c */
    184 struct dkbad;
    185 int isbad(struct dkbad *bt, int, int, int);
    186 /* machdep.c */
    187 int	ldcontrolb(caddr_t);
    188 void	dumpconf(void);
    189 caddr_t	reserve_dumppages(caddr_t);
    190 /* clock.c */
    191 struct timeval;
    192 void	lo_microtime(struct timeval *);
    193 void	schedintr(void *);
    194 /* locore.s */
    195 struct fpstate;
    196 void	savefpstate(struct fpstate *);
    197 void	loadfpstate(struct fpstate *);
    198 int	probeget(caddr_t, int);
    199 void	write_all_windows(void);
    200 void	write_user_windows(void);
    201 void 	proc_trampoline(void);
    202 void	switchexit(struct lwp *, void (*)(struct lwp *));
    203 struct pcb;
    204 void	snapshot(struct pcb *);
    205 struct frame *getfp(void);
    206 int	xldcontrolb(caddr_t, struct pcb *);
    207 void	copywords(const void *, void *, size_t);
    208 void	qcopy(const void *, void *, size_t);
    209 void	qzero(void *, size_t);
    210 /* trap.c */
    211 void	kill_user_windows(struct lwp *);
    212 int	rwindow_save(struct lwp *);
    213 /* cons.c */
    214 int	cnrom(void);
    215 /* zs.c */
    216 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int));
    217 #ifdef KGDB
    218 void zs_kgdb_init(void);
    219 #endif
    220 /* fb.c */
    221 void	fb_unblank(void);
    222 /* cache.c */
    223 void cache_flush(caddr_t, u_int);
    224 /* kgdb_stub.c */
    225 #ifdef KGDB
    226 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *);
    227 void kgdb_connect(int);
    228 void kgdb_panic(void);
    229 #endif
    230 /* emul.c */
    231 struct trapframe;
    232 int fixalign(struct lwp *, struct trapframe *);
    233 int emulinstr(int, struct trapframe *);
    234 /* cpu.c */
    235 void mp_pause_cpus(void);
    236 void mp_resume_cpus(void);
    237 void mp_halt_cpus(void);
    238 #ifdef DDB
    239 void mp_pause_cpus_ddb(void);
    240 void mp_resume_cpus_ddb(void);
    241 #endif
    242 /* msiiep.c */
    243 void msiiep_swap_endian(int);
    244 /* intr.c */
    245 u_int setitr(u_int);
    246 u_int getitr(void);
    247 
    248 /*
    249  *
    250  * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits
    251  * of the trap vector table.  The next eight bits are supplied by the
    252  * hardware when the trap occurs, and the bottom four bits are always
    253  * zero (so that we can shove up to 16 bytes of executable code---exactly
    254  * four instructions---into each trap vector).
    255  *
    256  * The hardware allocates half the trap vectors to hardware and half to
    257  * software.
    258  *
    259  * Traps have priorities assigned (lower number => higher priority).
    260  */
    261 
    262 struct trapvec {
    263 	int	tv_instr[4];		/* the four instructions */
    264 };
    265 extern struct trapvec *trapbase;	/* the 256 vectors */
    266 
    267 extern void wzero __P((void *, u_int));
    268 extern void wcopy __P((const void *, void *, u_int));
    269 
    270 #endif /* _KERNEL */
    271 #endif /* _CPU_H_ */
    272