cpu.h revision 1.78
1 /* $NetBSD: cpu.h,v 1.78 2007/02/09 21:55:12 ad Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)cpu.h 8.4 (Berkeley) 1/5/94 41 */ 42 43 #ifndef _CPU_H_ 44 #define _CPU_H_ 45 46 /* 47 * CTL_MACHDEP definitions. 48 */ 49 #define CPU_BOOTED_KERNEL 1 /* string: booted kernel name */ 50 #define CPU_BOOTED_DEVICE 2 /* string: device booted from */ 51 #define CPU_BOOT_ARGS 3 /* string: args booted with */ 52 #define CPU_ARCH 4 /* integer: cpu architecture version */ 53 #define CPU_MAXID 5 /* number of valid machdep ids */ 54 55 #define CTL_MACHDEP_NAMES { \ 56 { 0, 0 }, \ 57 { "booted_kernel", CTLTYPE_STRING }, \ 58 { "booted_device", CTLTYPE_STRING }, \ 59 { "boot_args", CTLTYPE_STRING }, \ 60 { "cpu_arch", CTLTYPE_INT }, \ 61 } 62 63 #ifdef _KERNEL 64 /* 65 * Exported definitions unique to SPARC cpu support. 66 */ 67 68 #if defined(_KERNEL_OPT) 69 #include "opt_multiprocessor.h" 70 #include "opt_lockdebug.h" 71 #include "opt_sparc_arch.h" 72 #endif 73 74 #include <machine/intr.h> 75 #include <machine/psl.h> 76 #include <sparc/sparc/cpuvar.h> 77 #include <sparc/sparc/intreg.h> 78 79 /* 80 * definitions of cpu-dependent requirements 81 * referenced in generic code 82 */ 83 #define curcpu() (cpuinfo.ci_self) 84 #define curlwp (cpuinfo.ci_curlwp) 85 #define CPU_IS_PRIMARY(ci) ((ci)->master) 86 87 #define cpu_swapin(p) /* nothing */ 88 #define cpu_swapout(p) /* nothing */ 89 #define cpu_number() (cpuinfo.ci_cpuid) 90 void cpu_proc_fork(struct proc *, struct proc *); 91 92 #if defined(MULTIPROCESSOR) 93 void cpu_boot_secondary_processors(void); 94 #endif 95 96 /* 97 * Arguments to hardclock, softclock and statclock encapsulate the 98 * previous machine state in an opaque clockframe. The ipl is here 99 * as well for strayintr (see locore.s:interrupt and intr.c:strayintr). 100 * Note that CLKF_INTR is valid only if CLKF_USERMODE is false. 101 */ 102 struct clockframe { 103 u_int psr; /* psr before interrupt, excluding PSR_ET */ 104 u_int pc; /* pc at interrupt */ 105 u_int npc; /* npc at interrupt */ 106 u_int ipl; /* actual interrupt priority level */ 107 u_int fp; /* %fp at interrupt */ 108 }; 109 typedef struct clockframe clockframe; 110 111 extern int eintstack[]; 112 113 #define CLKF_USERMODE(framep) (((framep)->psr & PSR_PS) == 0) 114 #define CLKF_BASEPRI(framep) (((framep)->psr & PSR_PIL) == 0) 115 #define CLKF_LOPRI(framep,n) (((framep)->psr & PSR_PIL) < (n) << 8) 116 #define CLKF_PC(framep) ((framep)->pc) 117 #if defined(MULTIPROCESSOR) 118 #define CLKF_INTR(framep) \ 119 ((framep)->fp > (u_int)cpuinfo.eintstack - INT_STACK_SIZE && \ 120 (framep)->fp < (u_int)cpuinfo.eintstack) 121 #else 122 #define CLKF_INTR(framep) ((framep)->fp < (u_int)eintstack) 123 #endif 124 125 void softintr_init(void); 126 extern void *softnet_cookie; 127 128 #define setsoftnet() softintr_schedule(softnet_cookie); 129 130 /* 131 * Preempt the current process on the target CPU if in interrupt from 132 * user mode, or after the current trap/syscall if in system mode. 133 */ 134 #define cpu_need_resched(ci) do { \ 135 (ci)->want_resched = 1; \ 136 (ci)->want_ast = 1; \ 137 \ 138 /* Just interrupt the target CPU, so it can notice its AST */ \ 139 if ((ci)->ci_cpuid != cpu_number()) \ 140 XCALL0(sparc_noop, 1U << (ci)->ci_cpuid); \ 141 } while (/*CONSTCOND*/0) 142 143 /* 144 * Give a profiling tick to the current process when the user profiling 145 * buffer pages are invalid. On the sparc, request an ast to send us 146 * through trap(), marking the proc as needing a profiling tick. 147 */ 148 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, cpuinfo.want_ast = 1) 149 150 /* 151 * Notify the current process (p) that it has a signal pending, 152 * process as soon as possible. 153 */ 154 #define cpu_signotify(l) do { \ 155 struct cpu_info *_ci = (l)->l_cpu; \ 156 _ci->want_ast = 1; \ 157 \ 158 /* Just interrupt the target CPU, so it can notice its AST */ \ 159 if (_ci->ci_cpuid != cpu_number()) \ 160 XCALL0(sparc_noop, 1U << _ci->ci_cpuid); \ 161 } while (/*CONSTCOND*/0) 162 163 /* CPU architecture version */ 164 extern int cpu_arch; 165 166 /* Number of CPUs in the system */ 167 extern int sparc_ncpus; 168 169 /* 170 * Interrupt handler chains. Interrupt handlers should return 0 for 171 * ``not me'' or 1 (``I took care of it''). intr_establish() inserts a 172 * handler into the list. The handler is called with its (single) 173 * argument, or with a pointer to a clockframe if ih_arg is NULL. 174 */ 175 extern struct intrhand { 176 int (*ih_fun)(void *); 177 void *ih_arg; 178 struct intrhand *ih_next; 179 int ih_classipl; 180 } *intrhand[15]; 181 182 void intr_establish(int, int, struct intrhand *, void (*)(void)); 183 void intr_disestablish(int, struct intrhand *); 184 185 void intr_lock_kernel(void); 186 void intr_unlock_kernel(void); 187 188 /* disksubr.c */ 189 struct dkbad; 190 int isbad(struct dkbad *, int, int, int); 191 192 /* machdep.c */ 193 int ldcontrolb(caddr_t); 194 void dumpconf(void); 195 caddr_t reserve_dumppages(caddr_t); 196 void wcopy(const void *, void *, u_int); 197 void wzero(void *, u_int); 198 199 /* clock.c */ 200 struct timeval; 201 void lo_microtime(struct timeval *); 202 void schedintr(void *); 203 204 /* locore.s */ 205 struct fpstate; 206 void savefpstate(struct fpstate *); 207 void loadfpstate(struct fpstate *); 208 int probeget(caddr_t, int); 209 void write_all_windows(void); 210 void write_user_windows(void); 211 void proc_trampoline(void); 212 struct pcb; 213 void snapshot(struct pcb *); 214 struct frame *getfp(void); 215 int xldcontrolb(caddr_t, struct pcb *); 216 void copywords(const void *, void *, size_t); 217 void qcopy(const void *, void *, size_t); 218 void qzero(void *, size_t); 219 220 /* trap.c */ 221 void kill_user_windows(struct lwp *); 222 int rwindow_save(struct lwp *); 223 224 /* cons.c */ 225 int cnrom(void); 226 227 /* zs.c */ 228 void zsconsole(struct tty *, int, int, void (**)(struct tty *, int)); 229 #ifdef KGDB 230 void zs_kgdb_init(void); 231 #endif 232 233 /* fb.c */ 234 void fb_unblank(void); 235 236 /* kgdb_stub.c */ 237 #ifdef KGDB 238 void kgdb_attach(int (*)(void *), void (*)(void *, int), void *); 239 void kgdb_connect(int); 240 void kgdb_panic(void); 241 #endif 242 243 /* emul.c */ 244 struct trapframe; 245 int fixalign(struct lwp *, struct trapframe *); 246 int emulinstr(int, struct trapframe *); 247 248 /* cpu.c */ 249 void mp_pause_cpus(void); 250 void mp_resume_cpus(void); 251 void mp_halt_cpus(void); 252 #ifdef DDB 253 void mp_pause_cpus_ddb(void); 254 void mp_resume_cpus_ddb(void); 255 #endif 256 257 /* intr.c */ 258 u_int setitr(u_int); 259 u_int getitr(void); 260 261 262 /* 263 * 264 * The SPARC has a Trap Base Register (TBR) which holds the upper 20 bits 265 * of the trap vector table. The next eight bits are supplied by the 266 * hardware when the trap occurs, and the bottom four bits are always 267 * zero (so that we can shove up to 16 bytes of executable code---exactly 268 * four instructions---into each trap vector). 269 * 270 * The hardware allocates half the trap vectors to hardware and half to 271 * software. 272 * 273 * Traps have priorities assigned (lower number => higher priority). 274 */ 275 276 struct trapvec { 277 int tv_instr[4]; /* the four instructions */ 278 }; 279 280 extern struct trapvec *trapbase; /* the 256 vectors */ 281 282 #endif /* _KERNEL */ 283 #endif /* _CPU_H_ */ 284
Indexes created Mon Sep 22 21:09:42 GMT 2025