instr.h revision 1.1
1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)instr.h 8.1 (Berkeley) 6/11/93 43 * 44 * from: Header: instr.h,v 1.6 92/11/26 02:04:37 torek Exp 45 * $Id: instr.h,v 1.1 1993/10/02 10:23:15 deraadt Exp $ 46 */ 47 48 /* see also Appendix F of the SPARC version 8 document */ 49 enum IOP { IOP_OP2, IOP_CALL, IOP_reg, IOP_mem }; 50 enum IOP2 { IOP2_UNIMP, IOP2_err1, IOP2_Bicc, IOP2_err3, 51 IOP2_SETHI, IOP2_err5, IOP2_FBfcc, IOP2_CBccc }; 52 enum IOP3_reg { 53 IOP3_ADD, IOP3_AND, IOP3_OR, IOP3_XOR, 54 IOP3_SUB, IOP3_ANDN, IOP3_ORN, IOP3_XNOR, 55 IOP3_ADDX, IOP3_rerr09, IOP3_UMUL, IOP3_SMUL, 56 IOP3_SUBX, IOP3_rerr0d, IOP3_UDIV, IOP3_SDIV, 57 IOP3_ADDcc, IOP3_ANDcc, IOP3_ORcc, IOP3_XORcc, 58 IOP3_SUBcc, IOP3_ANDNcc, IOP3_ORNcc, IOP3_XNORcc, 59 IOP3_ADDXcc, IOP3_rerr19, IOP3_UMULcc, IOP3_SMULcc, 60 IOP3_SUBXcc, IOP3_rerr1d, IOP3_UDIVcc, IOP3_SDIVcc, 61 IOP3_TADDcc, IOP3_TSUBcc, IOP3_TADDccTV, IOP3_TSUBccTV, 62 IOP3_MULScc, IOP3_SLL, IOP3_SRL, IOP3_SRA, 63 IOP3_RDASR_RDY_STBAR, IOP3_RDPSR, IOP3_RDWIM, IOP3_RDTGBR, 64 IOP3_rerr2c, IOP3_rerr2d, IOP3_rerr2e, IOP3_rerr2f, 65 IOP3_WRASR_WRY, IOP3_WRPSR, IOP3_WRWIM, IOP3_WRTBR, 66 IOP3_FPop1, IOP3_FPop2, IOP3_CPop1, IOP3_CPop2, 67 IOP3_JMPL, IOP3_RETT, IOP3_Ticc, IOP3_FLUSH, 68 IOP3_SAVE, IOP3_RESTORE, IOP3_rerr3e, IOP3_rerr3f 69 }; 70 enum IOP3_mem { 71 IOP3_LD, IOP3_LDUB, IOP3_LDUH, IOP3_LDD, 72 IOP3_ST, IOP3_STB, IOP3_STH, IOP3_STD, 73 IOP3_merr08, IOP3_LDSB, IOP3_LDSH, IOP3_merr0b, 74 IOP3_merr0c, IOP3_LDSTUB, IOP3_merr0f, IOP3_SWAP, 75 IOP3_LDA, IOP3_LDUBA, IOP3_LDUHA, IOP3_LDDA, 76 IOP3_STA, IOP3_STBA, IOP3_STHA, IOP3_STDA, 77 IOP3_merr18, IOP3_LDSBA, IOP3_LDSHA, IOP3_merr1b, 78 IOP3_merr1c, IOP3_LDSTUBA, IOP3_merr1f, IOP3_SWAPA, 79 IOP3_LDF, IOP3_LDFSR, IOP3_merr22, IOP3_LDDF, 80 IOP3_STF, IOP3_STFSR, IOP3_STDFQ, IOP3_STDF, 81 IOP3_merr28, IOP3_merr29, IOP3_merr2a, IOP3_merr2b, 82 IOP3_merr2c, IOP3_merr2d, IOP3_merr2e, IOP3_merr2f, 83 IOP3_LFC, IOP3_LDCSR, IOP3_merr32, IOP3_LDDC, 84 IOP3_STC, IOP3_STCSR, IOP3_STDCQ, IOP3_STDC, 85 IOP3_merr38, IOP3_merr39, IOP3_merr3a, IOP3_merr3b, 86 IOP3_merr3c, IOP3_merr3d, IOP3_merr3e, IOP3_merr3f 87 }; 88 89 /* 90 * Integer condition codes. 91 */ 92 #define Icc_N 0x0 /* never */ 93 #define Icc_E 0x1 /* equal (equiv. zero) */ 94 #define Icc_LE 0x2 /* less or equal */ 95 #define Icc_L 0x3 /* less */ 96 #define Icc_LEU 0x4 /* less or equal unsigned */ 97 #define Icc_CS 0x5 /* carry set (equiv. less unsigned) */ 98 #define Icc_NEG 0x6 /* negative */ 99 #define Icc_VS 0x7 /* overflow set */ 100 #define Icc_A 0x8 /* always */ 101 #define Icc_NE 0x9 /* not equal (equiv. not zero) */ 102 #define Icc_G 0xa /* greater */ 103 #define Icc_GE 0xb /* greater or equal */ 104 #define Icc_GU 0xc /* greater unsigned */ 105 #define Icc_CC 0xd /* carry clear (equiv. gtr or eq unsigned) */ 106 #define Icc_POS 0xe /* positive */ 107 #define Icc_VC 0xf /* overflow clear */ 108 109 /* 110 * Integer registers. 111 */ 112 #define I_G0 0 113 #define I_G1 1 114 #define I_G2 2 115 #define I_G3 3 116 #define I_G4 4 117 #define I_G5 5 118 #define I_G6 6 119 #define I_G7 7 120 #define I_O0 8 121 #define I_O1 9 122 #define I_O2 10 123 #define I_O3 11 124 #define I_O4 12 125 #define I_O5 13 126 #define I_O6 14 127 #define I_O7 15 128 #define I_L0 16 129 #define I_L1 17 130 #define I_L2 18 131 #define I_L3 19 132 #define I_L4 20 133 #define I_L5 21 134 #define I_L6 22 135 #define I_L7 23 136 #define I_I0 24 137 #define I_I1 25 138 #define I_I2 26 139 #define I_I3 27 140 #define I_I4 28 141 #define I_I5 29 142 #define I_I6 30 143 #define I_I7 31 144 145 /* 146 * An instruction. 147 */ 148 union instr { 149 int i_int; /* as a whole */ 150 151 /* 152 * The first level of decoding is to use the top 2 bits. 153 * This gives us one of three `formats', which usually give 154 * a second level of decoding. 155 */ 156 struct { 157 u_int i_op:2; /* first-level decode */ 158 u_int :30; 159 } i_any; 160 161 /* 162 * Format 1 instructions: CALL (undifferentiated). 163 */ 164 struct { 165 u_int :2; /* 01 */ 166 int i_disp:30; /* displacement */ 167 } i_call; 168 169 /* 170 * Format 2 instructions (SETHI, UNIMP, and branches, plus illegal 171 * unused codes). 172 */ 173 struct { 174 u_int :2; /* 00 */ 175 u_int :5; 176 u_int i_op2:3; /* second-level decode */ 177 u_int :22; 178 } i_op2; 179 180 /* UNIMP, SETHI */ 181 struct { 182 u_int :2; /* 00 */ 183 u_int i_rd:5; /* destination register */ 184 u_int i_op2:3; /* opcode: UNIMP or SETHI */ 185 u_int i_imm:22; /* immediate value */ 186 } i_imm22; 187 188 /* branches: Bicc, FBfcc, CBccc */ 189 struct { 190 u_int :2; /* 00 */ 191 u_int i_annul:1; /* annul bit */ 192 u_int i_cond:4; /* condition codes */ 193 u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */ 194 int i_disp:22; /* branch displacement */ 195 } i_branch; 196 197 /* 198 * Format 3 instructions (memory reference; arithmetic, logical, 199 * shift, and other miscellaneous operations). The second-level 200 * decode almost always makes use of an `rd' and `rs1', however 201 * (see also IOP3_reg and IOP3_mem). 202 * 203 * Beyond that, the low 14 bits may be broken up in one of three 204 * different ways, if at all: 205 * 1 bit of imm=0 + 8 bits of asi + 5 bits of rs2 [reg & mem] 206 * 1 bit of imm=1 + 13 bits of signed immediate [reg & mem] 207 * 9 bits of copressor `opf' opcode + 5 bits of rs2 [reg only] 208 */ 209 struct { 210 u_int :2; /* 10 or 11 */ 211 u_int i_rd:5; /* destination register */ 212 u_int i_op3:6; /* second-level decode */ 213 u_int i_rs1:5; /* source register 1 */ 214 u_int i_low14:14; /* varies */ 215 } i_op3; 216 217 /* 218 * Memory forms. These set i_op=3 and use simm13 or asi layout. 219 * Memory references without an ASI should use 0, but the actual 220 * ASI field is simply ignored. 221 */ 222 struct { 223 u_int :2; /* 11 only */ 224 u_int i_rd:5; /* destination register */ 225 u_int i_op3:6; /* second-level decode (see IOP3_mem) */ 226 u_int i_i:1; /* immediate vs asi */ 227 u_int i_low13:13; /* depend on i bit */ 228 } i_loadstore; 229 230 /* 231 * Memory and register forms. 232 * These come in quite a variety and we do not 233 * attempt to break them down much. 234 */ 235 struct { 236 u_int :2; /* 10 or 11 */ 237 u_int i_rd:5; /* destination register */ 238 u_int i_op3:6; /* second-level decode */ 239 u_int i_rs1:5; /* source register 1 */ 240 u_int i_i:1; /* immediate bit (1) */ 241 int i_simm13:13; /* signed immediate */ 242 } i_simm13; 243 struct { 244 u_int :2; /* 10 or 11 */ 245 u_int i_rd:5; /* destination register */ 246 u_int i_op3:6; /* second-level decode */ 247 u_int i_rs1:5; /* source register 1 */ 248 u_int i_asi:8; /* asi */ 249 u_int i_rs2:5; /* source register 2 */ 250 } i_asi; 251 struct { 252 u_int :2; /* 10 only (register, no memory) */ 253 u_int i_rd:5; /* destination register */ 254 u_int i_op3:6; /* second-level decode (see IOP3_reg) */ 255 u_int i_rs1:5; /* source register 1 */ 256 u_int i_opf:9; /* coprocessor 3rd-level decode */ 257 u_int i_rs2:5; /* source register 2 */ 258 } i_opf; 259 260 }; 261 262 /* 263 * Internal macros for building instructions. These correspond 1-to-1 to 264 * the names above. Note that x << y | z == (x << y) | z. 265 */ 266 #define _I_ANY(op, b) ((op) << 30 | (b)) 267 268 #define _I_OP2(high, op2, low) \ 269 _I_ANY(IOP_OP2, (high) << 25 | (op2) << 22 | (low)) 270 #define _I_IMM22(rd, op2, imm) \ 271 _I_ANY(IOP_OP2, (rd) << 25 | (op2) << 22 | (imm)) 272 #define _I_BRANCH(a, c, op2, disp) \ 273 _I_ANY(IOP_OP2, (a) << 29 | (c) << 25 | (op2) << 22 | (disp)) 274 #define _I_FBFCC(a, cond, disp) \ 275 _I_BRANCH(a, cond, IOP2_FBfcc, disp) 276 #define _I_CBCCC(a, cond, disp) \ 277 _I_BRANCH(a, cond, IOP2_CBccc, disp) 278 279 #define _I_SIMM(simm) (1 << 13 | ((simm) & 0x1fff)) 280 281 #define _I_OP3_GEN(form, rd, op3, rs1, low14) \ 282 _I_ANY(form, (rd) << 25 | (op3) << 19 | (rs1) << 14 | (low14)) 283 #define _I_OP3_LS_RAR(rd, op3, rs1, asi, rs2) \ 284 _I_OP3_GEN(IOP_mem, rd, op3, rs1, (asi) << 5 | (rs2)) 285 #define _I_OP3_LS_RI(rd, op3, rs1, simm13) \ 286 _I_OP3_GEN(IOP_mem, rd, op3, rs1, _I_SIMM(simm13)) 287 #define _I_OP3_LS_RR(rd, op3, rs1, rs2) \ 288 _I_OP3_GEN(IOP_mem, rd, op3, rs1, rs2) 289 #define _I_OP3_R_RAR(rd, op3, rs1, asi, rs2) \ 290 _I_OP3_GEN(IOP_reg, rd, op3, rs1, (asi) << 5 | (rs2)) 291 #define _I_OP3_R_RI(rd, op3, rs1, simm13) \ 292 _I_OP3_GEN(IOP_reg, rd, op3, rs1, _I_SIMM(simm13)) 293 #define _I_OP3_R_RR(rd, op3, rs1, rs2) \ 294 _I_OP3_GEN(IOP_reg, rd, op3, rs1, rs2) 295 296 #define I_CALL(d) _I_ANY(IOP_CALL, d) 297 #define I_UNIMP(v) _I_IMM22(0, IOP2_UNIMP, v) 298 #define I_BN(a, d) _I_BRANCH(a, Icc_N, IOP2_Bicc, d) 299 #define I_BE(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 300 #define I_BZ(a, d) _I_BRANCH(a, Icc_E, IOP2_Bicc, d) 301 #define I_BLE(a, d) _I_BRANCH(a, Icc_LE, IOP2_Bicc, d) 302 #define I_BL(a, d) _I_BRANCH(a, Icc_L, IOP2_Bicc, d) 303 #define I_BLEU(a, d) _I_BRANCH(a, Icc_LEU, IOP2_Bicc, d) 304 #define I_BCS(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 305 #define I_BLU(a, d) _I_BRANCH(a, Icc_CS, IOP2_Bicc, d) 306 #define I_BNEG(a, d) _I_BRANCH(a, Icc_NEG, IOP2_Bicc, d) 307 #define I_BVS(a, d) _I_BRANCH(a, Icc_VS, IOP2_Bicc, d) 308 #define I_BA(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 309 #define I_B(a, d) _I_BRANCH(a, Icc_A, IOP2_Bicc, d) 310 #define I_BNE(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 311 #define I_BNZ(a, d) _I_BRANCH(a, Icc_NE, IOP2_Bicc, d) 312 #define I_BG(a, d) _I_BRANCH(a, Icc_G, IOP2_Bicc, d) 313 #define I_BGE(a, d) _I_BRANCH(a, Icc_GE, IOP2_Bicc, d) 314 #define I_BGU(a, d) _I_BRANCH(a, Icc_GU, IOP2_Bicc, d) 315 #define I_BCC(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 316 #define I_BGEU(a, d) _I_BRANCH(a, Icc_CC, IOP2_Bicc, d) 317 #define I_BPOS(a, d) _I_BRANCH(a, Icc_POS, IOP2_Bicc, d) 318 #define I_BVC(a, d) _I_BRANCH(a, Icc_VC, IOP2_Bicc, d) 319 #define I_SETHI(r, v) _I_IMM22(r, 4, v) 320 321 #define I_ORri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_OR, rs1, imm) 322 #define I_ORrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_OR, rs1, rs2) 323 324 #define I_MOVi(rd, imm) _I_OP3_R_RI(rd, IOP3_OR, I_G0, imm) 325 #define I_MOVr(rd, rs) _I_OP3_R_RR(rd, IOP3_OR, I_G0, rs) 326 327 #define I_RDPSR(rd) _I_OP3_R_RR(rd, IOP3_RDPSR, 0, 0) 328 329 #define I_JMPLri(rd, rs1, imm) _I_OP3_R_RI(rd, IOP3_JMPL, rs1, imm) 330 #define I_JMPLrr(rd, rs1, rs2) _I_OP3_R_RR(rd, IOP3_JMPL, rs1, rs2) 331 332 /* 333 * (Since these are sparse, we skip the enumerations for now.) 334 * FPop values. All appear in both FPop1 and FPop2 spaces, but arithmetic 335 * ops should happen only with FPop1 and comparison only with FPop2. 336 * The type sits in the low two bits; those bits are given as zero here. 337 */ 338 #define FMOV 0x00 339 #define FNEG 0x04 340 #define FABS 0x08 341 #define FSQRT 0x28 342 #define FADD 0x40 343 #define FSUB 0x44 344 #define FMUL 0x48 345 #define FDIV 0x4c 346 #define FCMP 0x50 347 #define FCMPE 0x54 348 #define FSMULD 0x68 349 #define FDMULX 0x6c 350 #define FTOS 0xc4 351 #define FTOD 0xc8 352 #define FTOX 0xcc 353 #define FTOI 0xd0 354 355 /* 356 * FPU data types. 357 */ 358 #define FTYPE_INT 0 /* data = 32-bit signed integer */ 359 #define FTYPE_SNG 1 /* data = 32-bit float */ 360 #define FTYPE_DBL 2 /* data = 64-bit double */ 361 #define FTYPE_EXT 3 /* data = 128-bit extended (quad-prec) */ 362
Indexes created Fri Sep 26 08:10:20 GMT 2025