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      1  1.14      mrg /*	$NetBSD: intr.h,v 1.14 2021/01/24 07:36:54 mrg Exp $ */
      2   1.1       pk 
      3   1.1       pk /*-
      4   1.1       pk  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5   1.1       pk  * All rights reserved.
      6   1.1       pk  *
      7   1.1       pk  * This code is derived from software contributed to The NetBSD Foundation
      8   1.1       pk  * by Paul Kranenburg.
      9   1.1       pk  *
     10   1.1       pk  * Redistribution and use in source and binary forms, with or without
     11   1.1       pk  * modification, are permitted provided that the following conditions
     12   1.1       pk  * are met:
     13   1.1       pk  * 1. Redistributions of source code must retain the above copyright
     14   1.1       pk  *    notice, this list of conditions and the following disclaimer.
     15   1.1       pk  * 2. Redistributions in binary form must reproduce the above copyright
     16   1.1       pk  *    notice, this list of conditions and the following disclaimer in the
     17   1.1       pk  *    documentation and/or other materials provided with the distribution.
     18   1.1       pk  *
     19   1.1       pk  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20   1.1       pk  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21   1.1       pk  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22   1.1       pk  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23   1.1       pk  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24   1.1       pk  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25   1.1       pk  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26   1.1       pk  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27   1.1       pk  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28   1.1       pk  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29   1.1       pk  * POSSIBILITY OF SUCH DAMAGE.
     30   1.1       pk  */
     31   1.1       pk 
     32   1.4       pk /*
     33   1.4       pk  * Device class interrupt levels
     34   1.4       pk  * Note: sun4 and sun4c hardware only has software interrupt available
     35   1.4       pk  *	 on level 1, 4 or 6. This limits the choice of the various
     36   1.4       pk  * 	 IPL_SOFT* symbols to one of those three values.
     37   1.4       pk  */
     38   1.1       pk #define IPL_NONE	0	/* nothing */
     39   1.1       pk #define IPL_SOFTCLOCK	1	/* timeouts */
     40   1.1       pk #define IPL_SOFTNET	1	/* protocol stack */
     41  1.10       ad #define IPL_SOFTBIO	1	/* block I/O */
     42   1.4       pk #define IPL_SOFTAUDIO	4	/* second-level audio */
     43   1.4       pk #define IPL_SOFTFDC	4	/* second-level floppy */
     44   1.4       pk #define IPL_SOFTSERIAL	6	/* serial */
     45   1.7  thorpej #define IPL_VM		7	/* memory allocation */
     46   1.6       pk #define IPL_SCHED	11	/* scheduler */
     47   1.4       pk #define IPL_HIGH	15	/* everything */
     48   1.9     yamt 
     49   1.9     yamt /*
     50  1.13  msaitoh  * fd hardware, ts102, and tadpole microcontroller interrupts are at level 11
     51   1.9     yamt  */
     52   1.9     yamt 
     53  1.10       ad #define	IPL_FD		IPL_SCHED
     54  1.10       ad #define	IPL_TS102	IPL_SCHED
     55   1.9     yamt 
     56   1.9     yamt /*
     57   1.9     yamt  * zs hardware interrupts are at level 12
     58   1.9     yamt  * su (com) hardware interrupts are at level 13
     59   1.9     yamt  * IPL_SERIAL must protect them all.
     60   1.9     yamt  */
     61   1.9     yamt 
     62  1.10       ad #define	IPL_ZS		IPL_HIGH
     63   1.2       pk 
     64  1.12     matt /*
     65  1.12     matt  * IPL_SAFEPRI is a safe priority for sleep to set for a spin-wait
     66  1.12     matt  * during autoconfiguration or after a panic.
     67  1.12     matt  */
     68  1.12     matt #define	IPL_SAFEPRI	0
     69  1.12     matt 
     70   1.4       pk #if defined(_KERNEL) && !defined(_LOCORE)
     71   1.3      mrg void *
     72  1.10       ad sparc_softintr_establish(int level, void (*fun)(void *), void *arg);
     73   1.3      mrg 
     74   1.3      mrg void
     75  1.10       ad sparc_softintr_disestablish(void *cookie);
     76   1.3      mrg 
     77   1.5       pk /*
     78  1.10       ad  * NB that sparc_softintr_schedule() casts the cookie to an int *.
     79   1.5       pk  * This is to get the sic_pilreq member of the softintr_cookie
     80   1.5       pk  * structure, which is otherwise internal to intr.c.
     81   1.5       pk  */
     82   1.5       pk #if defined(SUN4M) || defined(SUN4D)
     83  1.14      mrg extern int (*moduleerr_handler)(void);
     84  1.14      mrg extern int (*memerr_handler)(void);
     85   1.8      uwe extern void	raise(int, int);
     86   1.5       pk #if !(defined(SUN4) || defined(SUN4C))
     87  1.10       ad #define sparc_softintr_schedule(cookie)	raise(0, *((int *) (cookie)))
     88   1.5       pk #else /* both defined */
     89  1.10       ad #define sparc_softintr_schedule(cookie) do {		\
     90   1.5       pk 	if (CPU_ISSUN4M || CPU_ISSUN4D)		\
     91   1.5       pk 		raise(0, *((int *)(cookie)));	\
     92   1.5       pk 	else					\
     93   1.5       pk 		ienab_bis(*((int *)(cookie)));	\
     94   1.5       pk } while (0)
     95   1.5       pk #endif	/* SUN4  || SUN4C */
     96   1.5       pk #else	/* SUN4M || SUN4D */
     97  1.10       ad #define sparc_softintr_schedule(cookie)	ienab_bis(*((int *) (cookie)))
     98   1.5       pk #endif	/* SUN4M || SUN4D */
     99   1.5       pk 
    100   1.5       pk #if 0
    101  1.10       ad void sparc_softintr_schedule(void *cookie);
    102   1.5       pk #endif
    103   1.4       pk #endif /* KERNEL && !_LOCORE */
    104