psl.h revision 1.25
1 /* $NetBSD: psl.h,v 1.25 2001/03/22 06:21:43 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)psl.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 #ifndef PSR_IMPL 48 49 /* 50 * SPARC Process Status Register (in psl.h for hysterical raisins). This 51 * doesn't exist on the V9. 52 * 53 * The picture in the Sun manuals looks like this: 54 * 1 1 55 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0 56 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 57 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP | 58 * | | |n z v c| |C|F| | |S|T| | 59 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 60 */ 61 62 #define PSR_IMPL 0xf0000000 /* implementation */ 63 #define PSR_VER 0x0f000000 /* version */ 64 #define PSR_ICC 0x00f00000 /* integer condition codes */ 65 #define PSR_N 0x00800000 /* negative */ 66 #define PSR_Z 0x00400000 /* zero */ 67 #define PSR_O 0x00200000 /* overflow */ 68 #define PSR_C 0x00100000 /* carry */ 69 #define PSR_EC 0x00002000 /* coprocessor enable */ 70 #define PSR_EF 0x00001000 /* FP enable */ 71 #define PSR_PIL 0x00000f00 /* interrupt level */ 72 #define PSR_S 0x00000080 /* supervisor (kernel) mode */ 73 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */ 74 #define PSR_ET 0x00000020 /* trap enable */ 75 #define PSR_CWP 0x0000001f /* current window pointer */ 76 77 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET" 78 79 /* Interesting spl()s */ 80 #define PIL_SCSI 3 81 #define PIL_FDSOFT 4 82 #define PIL_AUSOFT 4 83 #define PIL_BIO 5 84 #define PIL_VIDEO 5 85 #define PIL_TTY 6 86 #define PIL_LPT 6 87 #define PIL_NET 6 88 #define PIL_IMP 7 89 #define PIL_CLOCK 10 90 #define PIL_FD 11 91 #define PIL_SER 12 92 #define PIL_AUD 13 93 #define PIL_HIGH 15 94 #define PIL_SCHED PIL_CLOCK 95 #define PIL_LOCK PIL_HIGH 96 97 /* 98 * SPARC V9 CCR register 99 */ 100 101 #define ICC_C 0x01L 102 #define ICC_V 0x02L 103 #define ICC_Z 0x04L 104 #define ICC_N 0x08L 105 #define XCC_SHIFT 4 106 #define XCC_C (ICC_C<<XCC_SHIFT) 107 #define XCC_V (ICC_V<<XCC_SHIFT) 108 #define XCC_Z (ICC_Z<<XCC_SHIFT) 109 #define XCC_N (ICC_N<<XCC_SHIFT) 110 111 112 /* 113 * SPARC V9 PSTATE register (what replaces the PSR in V9) 114 * 115 * Here's the layout: 116 * 117 * 11 10 9 8 7 6 5 4 3 2 1 0 118 * +------------------------------------------------------------+ 119 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 120 * +------------------------------------------------------------+ 121 */ 122 123 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 124 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 125 #define PSTATE_CLE 0x200 /* current little endian */ 126 #define PSTATE_TLE 0x100 /* traps little endian */ 127 #define PSTATE_MM 0x0c0 /* memory model */ 128 #define PSTATE_MM_TSO 0x000 /* total store order */ 129 #define PSTATE_MM_PSO 0x040 /* partial store order */ 130 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 131 #define PSTATE_RED 0x020 /* RED state */ 132 #define PSTATE_PEF 0x010 /* enable floating point */ 133 #define PSTATE_AM 0x008 /* 32-bit address masking */ 134 #define PSTATE_PRIV 0x004 /* privileged mode */ 135 #define PSTATE_IE 0x002 /* interrupt enable */ 136 #define PSTATE_AG 0x001 /* enable alternate globals */ 137 138 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 139 140 141 /* 142 * 32-bit code requires TSO or at best PSO since that's what's supported on 143 * SPARC V8 and earlier machines. 144 * 145 * 64-bit code sets the memory model in the ELF header. 146 * 147 * We're running kernel code in TSO for the moment so we don't need to worry 148 * about possible memory barrier bugs. 149 */ 150 151 #ifdef __arch64__ 152 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 153 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 154 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 155 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 156 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 157 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) 158 #else 159 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 160 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) 161 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) 162 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 163 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 164 #define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 165 #endif 166 167 /* 168 * SPARC V9 TSTATE register 169 * 170 * 39 32 31 24 23 18 17 8 7 5 4 0 171 * +-----+-----+-----+--------+---+-----+ 172 * | CCR | ASI | - | PSTATE | - | CWP | 173 * +-----+-----+-----+--------+---+-----+ 174 * */ 175 176 #define TSTATE_CWP 0x01f 177 #define TSTATE_PSTATE 0x6ff00 178 #define TSTATE_PSTATE_SHIFT 8 179 #define TSTATE_ASI 0xff000000LL 180 #define TSTATE_ASI_SHIFT 24 181 #define TSTATE_CCR 0xff00000000LL 182 #define TSTATE_CCR_SHIFT 32 183 184 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 185 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 186 187 /* 188 * These are here to simplify life. 189 */ 190 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 191 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 192 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 193 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 194 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 195 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 196 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 197 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 198 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 199 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 200 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 201 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 202 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 203 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 204 205 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 206 207 #define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 208 #define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT) 209 /* 210 * SPARC V9 VER version register. 211 * 212 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 213 * +-------+------+------+-----+-------+---+--------+ 214 * | manuf | impl | mask | - | maxtl | - | maxwin | 215 * +-------+------+------+-----+-------+---+--------+ 216 * 217 */ 218 219 #define VER_MANUF 0xffff000000000000LL 220 #define VER_MANUF_SHIFT 48 221 #define VER_IMPL 0x0000ffff00000000LL 222 #define VER_IMPL_SHIFT 32 223 #define VER_MASK 0x00000000ff000000LL 224 #define VER_MASK_SHIFT 24 225 #define VER_MAXTL 0x000000000000ff00LL 226 #define VER_MAXTL_SHIFT 8 227 #define VER_MAXWIN 0x000000000000001fLL 228 229 /* 230 * Here are a few things to help us transition between user and kernel mode: 231 */ 232 233 /* Memory models */ 234 #define KERN_MM PSTATE_MM_TSO 235 #define USER_MM PSTATE_MM_RMO 236 237 /* 238 * Register window handlers. These point to generic routines that check the 239 * stack pointer and then vector to the real handler. We could optimize this 240 * if we could guarantee only 32-bit or 64-bit stacks. 241 */ 242 #define WSTATE_KERN 026 243 #define WSTATE_USER 022 244 245 #define CWP 0x01f 246 247 /* 64-byte alignment -- this seems the best place to put this. */ 248 #define BLOCK_SIZE 64 249 #define BLOCK_ALIGN 0x3f 250 251 #if defined(_KERNEL) && !defined(_LOCORE) 252 253 static __inline int getpsr __P((void)); 254 static __inline void setpsr __P((int)); 255 static __inline void spl0 __P((void)); 256 static __inline int splhigh __P((void)); 257 static __inline void splx __P((int)); 258 static __inline int getmid __P((void)); 259 260 /* 261 * GCC pseudo-functions for manipulating PSR (primarily PIL field). 262 */ 263 static __inline int getpsr() 264 { 265 int psr; 266 267 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 268 return (psr); 269 } 270 271 static __inline int getmid() 272 { 273 int mid; 274 275 __asm __volatile("rd %%tbr,%0" : "=r" (mid)); 276 return ((mid >> 20) & 0x3); 277 } 278 279 static __inline void setpsr(newpsr) 280 int newpsr; 281 { 282 __asm __volatile("wr %0,0,%%psr" : : "r" (newpsr)); 283 __asm __volatile("nop; nop; nop"); 284 } 285 286 static __inline void spl0() 287 { 288 int psr, oldipl; 289 290 /* 291 * wrpsr xors two values: we choose old psr and old ipl here, 292 * which gives us the same value as the old psr but with all 293 * the old PIL bits turned off. 294 */ 295 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 296 oldipl = psr & PSR_PIL; 297 __asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl)); 298 299 /* 300 * Three instructions must execute before we can depend 301 * on the bits to be changed. 302 */ 303 __asm __volatile("nop; nop; nop"); 304 } 305 306 /* 307 * PIL 1 through 14 can use this macro. 308 * (spl0 and splhigh are special since they put all 0s or all 1s 309 * into the ipl field.) 310 */ 311 #define _SPLSET(name, newipl) \ 312 static __inline void name __P((void)); \ 313 static __inline void name() \ 314 { \ 315 int psr, oldipl; \ 316 __asm __volatile("rd %%psr,%0" : "=r" (psr)); \ 317 oldipl = psr & PSR_PIL; \ 318 psr &= ~oldipl; \ 319 __asm __volatile("wr %0,%1,%%psr" : : \ 320 "r" (psr), "n" ((newipl) << 8)); \ 321 __asm __volatile("nop; nop; nop"); \ 322 } 323 324 /* Raise IPL and return previous value */ 325 #define _SPLRAISE(name, newipl) \ 326 static __inline int name __P((void)); \ 327 static __inline int name() \ 328 { \ 329 int psr, oldipl; \ 330 __asm __volatile("rd %%psr,%0" : "=r" (psr)); \ 331 oldipl = psr & PSR_PIL; \ 332 if ((newipl << 8) <= oldipl) \ 333 return (oldipl); \ 334 psr &= ~oldipl; \ 335 __asm __volatile("wr %0,%1,%%psr" : : \ 336 "r" (psr), "n" ((newipl) << 8)); \ 337 __asm __volatile("nop; nop; nop"); \ 338 return (oldipl); \ 339 } 340 341 _SPLSET(spllowersoftclock, 1) 342 343 _SPLRAISE(splsoftint, 1) 344 #define splsoftclock splsoftint 345 #define splsoftnet splsoftint 346 347 348 /* audio software interrupts */ 349 _SPLRAISE(splausoft, PIL_AUSOFT) 350 351 /* floppy software interrupts */ 352 _SPLRAISE(splfdsoft, PIL_FDSOFT) 353 354 /* Block devices */ 355 _SPLRAISE(splbio, 5) 356 357 /* network hardware interrupts are at level 6 */ 358 _SPLRAISE(splnet, PIL_NET) 359 360 /* tty input runs at software level 6 */ 361 #define PIL_TTY 6 362 _SPLRAISE(spltty, PIL_TTY) 363 364 /* 365 * Memory allocation (must be as high as highest network, tty, or disk device) 366 */ 367 _SPLRAISE(splimp, 7) 368 _SPLRAISE(splvm, 7) 369 370 /* clock interrupts at level 10 */ 371 _SPLRAISE(splclock, PIL_CLOCK) 372 373 /* fd hardware, ts102, and tadpole microcontoller interrupts are at level 11 */ 374 _SPLRAISE(splfd, 11) 375 _SPLRAISE(splts102, 11) 376 377 /* zs hardware interrupts are at level 12 */ 378 _SPLRAISE(splzs, 12) 379 _SPLRAISE(splserial, 12) /* XXX - other serial hardware might not be at lvl 12 */ 380 381 /* audio hardware interrupts are at level 13 */ 382 _SPLRAISE(splaudio, 13) 383 384 /* second sparc timer interrupts at level 14 */ 385 _SPLRAISE(splstatclock, 14) 386 387 static __inline int splhigh() 388 { 389 int psr, oldipl; 390 391 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 392 __asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL)); 393 __asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \ 394 "r" (psr), "n" (PSR_PIL)); 395 return (oldipl); 396 } 397 398 #define splsched() splhigh() 399 #define spllock() splhigh() 400 401 /* splx does not have a return value */ 402 static __inline void splx(newipl) 403 int newipl; 404 { 405 int psr; 406 407 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 408 __asm __volatile("wr %0,%1,%%psr" : : \ 409 "r" (psr & ~PSR_PIL), "rn" (newipl)); 410 __asm __volatile("nop; nop; nop"); 411 } 412 #endif /* KERNEL && !_LOCORE */ 413 414 #endif /* PSR_IMPL */ 415
Indexes created Sat Sep 27 22:09:54 GMT 2025