psl.h revision 1.34
1 /* $NetBSD: psl.h,v 1.34 2003/08/07 16:29:40 agc Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * @(#)psl.h 8.1 (Berkeley) 6/11/93 41 */ 42 43 #ifndef PSR_IMPL 44 45 /* 46 * SPARC Process Status Register (in psl.h for hysterical raisins). This 47 * doesn't exist on the V9. 48 * 49 * The picture in the Sun manuals looks like this: 50 * 1 1 51 * 31 28 27 24 23 20 19 14 3 2 11 8 7 6 5 4 0 52 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 53 * | impl | ver | icc | reserved |E|E| pil |S|P|E| CWP | 54 * | | |n z v c| |C|F| | |S|T| | 55 * +-------+-------+-------+-----------+-+-+-------+-+-+-+---------+ 56 */ 57 58 #define PSR_IMPL 0xf0000000 /* implementation */ 59 #define PSR_VER 0x0f000000 /* version */ 60 #define PSR_ICC 0x00f00000 /* integer condition codes */ 61 #define PSR_N 0x00800000 /* negative */ 62 #define PSR_Z 0x00400000 /* zero */ 63 #define PSR_O 0x00200000 /* overflow */ 64 #define PSR_C 0x00100000 /* carry */ 65 #define PSR_EC 0x00002000 /* coprocessor enable */ 66 #define PSR_EF 0x00001000 /* FP enable */ 67 #define PSR_PIL 0x00000f00 /* interrupt level */ 68 #define PSR_S 0x00000080 /* supervisor (kernel) mode */ 69 #define PSR_PS 0x00000040 /* previous supervisor mode (traps) */ 70 #define PSR_ET 0x00000020 /* trap enable */ 71 #define PSR_CWP 0x0000001f /* current window pointer */ 72 73 #define PSR_BITS "\20\16EC\15EF\10S\7PS\6ET" 74 75 /* Interesting spl()s */ 76 #define PIL_FDSOFT IPL_SOFTFDC /* compat */ 77 #define PIL_AUSOFT IPL_SOFTAUDIO /* compat */ 78 #define PIL_TTY 6 /* compat */ 79 #define PIL_CLOCK 10 80 #define PIL_FD 11 81 #define PIL_SER 13 82 #define PIL_AUD 13 83 #define PIL_HIGH 15 84 #define PIL_LOCK PIL_HIGH 85 86 /* 87 * SPARC V9 CCR register 88 */ 89 90 #define ICC_C 0x01L 91 #define ICC_V 0x02L 92 #define ICC_Z 0x04L 93 #define ICC_N 0x08L 94 #define XCC_SHIFT 4 95 #define XCC_C (ICC_C<<XCC_SHIFT) 96 #define XCC_V (ICC_V<<XCC_SHIFT) 97 #define XCC_Z (ICC_Z<<XCC_SHIFT) 98 #define XCC_N (ICC_N<<XCC_SHIFT) 99 100 101 /* 102 * SPARC V9 PSTATE register (what replaces the PSR in V9) 103 * 104 * Here's the layout: 105 * 106 * 11 10 9 8 7 6 5 4 3 2 1 0 107 * +------------------------------------------------------------+ 108 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 109 * +------------------------------------------------------------+ 110 */ 111 112 #define PSTATE_IG 0x800 /* enable spitfire interrupt globals */ 113 #define PSTATE_MG 0x400 /* enable spitfire MMU globals */ 114 #define PSTATE_CLE 0x200 /* current little endian */ 115 #define PSTATE_TLE 0x100 /* traps little endian */ 116 #define PSTATE_MM 0x0c0 /* memory model */ 117 #define PSTATE_MM_TSO 0x000 /* total store order */ 118 #define PSTATE_MM_PSO 0x040 /* partial store order */ 119 #define PSTATE_MM_RMO 0x080 /* Relaxed memory order */ 120 #define PSTATE_RED 0x020 /* RED state */ 121 #define PSTATE_PEF 0x010 /* enable floating point */ 122 #define PSTATE_AM 0x008 /* 32-bit address masking */ 123 #define PSTATE_PRIV 0x004 /* privileged mode */ 124 #define PSTATE_IE 0x002 /* interrupt enable */ 125 #define PSTATE_AG 0x001 /* enable alternate globals */ 126 127 #define PSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 128 129 130 /* 131 * 32-bit code requires TSO or at best PSO since that's what's supported on 132 * SPARC V8 and earlier machines. 133 * 134 * 64-bit code sets the memory model in the ELF header. 135 * 136 * We're running kernel code in TSO for the moment so we don't need to worry 137 * about possible memory barrier bugs. 138 */ 139 140 #ifdef __arch64__ 141 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 142 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_PRIV|PSTATE_AG) 143 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_PRIV) 144 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 145 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 146 #define PSTATE_USER (PSTATE_MM_RMO|PSTATE_IE) 147 #else 148 #define PSTATE_PROM (PSTATE_MM_TSO|PSTATE_PRIV) 149 #define PSTATE_NUCLEUS (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV|PSTATE_AG) 150 #define PSTATE_KERN (PSTATE_MM_TSO|PSTATE_AM|PSTATE_PRIV) 151 #define PSTATE_INTR (PSTATE_KERN|PSTATE_IE) 152 #define PSTATE_USER32 (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 153 #define PSTATE_USER (PSTATE_MM_TSO|PSTATE_AM|PSTATE_IE) 154 #endif 155 156 /* 157 * SPARC V9 TSTATE register 158 * 159 * 39 32 31 24 23 18 17 8 7 5 4 0 160 * +-----+-----+-----+--------+---+-----+ 161 * | CCR | ASI | - | PSTATE | - | CWP | 162 * +-----+-----+-----+--------+---+-----+ 163 * */ 164 165 #define TSTATE_CWP 0x01f 166 #define TSTATE_PSTATE 0x6ff00 167 #define TSTATE_PSTATE_SHIFT 8 168 #define TSTATE_ASI 0xff000000LL 169 #define TSTATE_ASI_SHIFT 24 170 #define TSTATE_CCR 0xff00000000LL 171 #define TSTATE_CCR_SHIFT 32 172 173 #define PSRCC_TO_TSTATE(x) (((int64_t)(x)&PSR_ICC)<<(TSTATE_CCR_SHIFT-19)) 174 #define TSTATECCR_TO_PSR(x) (((x)&TSTATE_CCR)>>(TSTATE_CCR_SHIFT-19)) 175 176 /* 177 * These are here to simplify life. 178 */ 179 #define TSTATE_IG (PSTATE_IG<<TSTATE_PSTATE_SHIFT) 180 #define TSTATE_MG (PSTATE_MG<<TSTATE_PSTATE_SHIFT) 181 #define TSTATE_CLE (PSTATE_CLE<<TSTATE_PSTATE_SHIFT) 182 #define TSTATE_TLE (PSTATE_TLE<<TSTATE_PSTATE_SHIFT) 183 #define TSTATE_MM (PSTATE_MM<<TSTATE_PSTATE_SHIFT) 184 #define TSTATE_MM_TSO (PSTATE_MM_TSO<<TSTATE_PSTATE_SHIFT) 185 #define TSTATE_MM_PSO (PSTATE_MM_PSO<<TSTATE_PSTATE_SHIFT) 186 #define TSTATE_MM_RMO (PSTATE_MM_RMO<<TSTATE_PSTATE_SHIFT) 187 #define TSTATE_RED (PSTATE_RED<<TSTATE_PSTATE_SHIFT) 188 #define TSTATE_PEF (PSTATE_PEF<<TSTATE_PSTATE_SHIFT) 189 #define TSTATE_AM (PSTATE_AM<<TSTATE_PSTATE_SHIFT) 190 #define TSTATE_PRIV (PSTATE_PRIV<<TSTATE_PSTATE_SHIFT) 191 #define TSTATE_IE (PSTATE_IE<<TSTATE_PSTATE_SHIFT) 192 #define TSTATE_AG (PSTATE_AG<<TSTATE_PSTATE_SHIFT) 193 194 #define TSTATE_BITS "\20\14IG\13MG\12CLE\11TLE\10\7MM\6RED\5PEF\4AM\3PRIV\2IE\1AG" 195 196 #define TSTATE_KERN ((TSTATE_KERN)<<TSTATE_PSTATE_SHIFT) 197 #define TSTATE_USER ((TSTATE_USER)<<TSTATE_PSTATE_SHIFT) 198 /* 199 * SPARC V9 VER version register. 200 * 201 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 202 * +-------+------+------+-----+-------+---+--------+ 203 * | manuf | impl | mask | - | maxtl | - | maxwin | 204 * +-------+------+------+-----+-------+---+--------+ 205 * 206 */ 207 208 #define VER_MANUF 0xffff000000000000LL 209 #define VER_MANUF_SHIFT 48 210 #define VER_IMPL 0x0000ffff00000000LL 211 #define VER_IMPL_SHIFT 32 212 #define VER_MASK 0x00000000ff000000LL 213 #define VER_MASK_SHIFT 24 214 #define VER_MAXTL 0x000000000000ff00LL 215 #define VER_MAXTL_SHIFT 8 216 #define VER_MAXWIN 0x000000000000001fLL 217 218 /* 219 * Here are a few things to help us transition between user and kernel mode: 220 */ 221 222 /* Memory models */ 223 #define KERN_MM PSTATE_MM_TSO 224 #define USER_MM PSTATE_MM_RMO 225 226 /* 227 * Register window handlers. These point to generic routines that check the 228 * stack pointer and then vector to the real handler. We could optimize this 229 * if we could guarantee only 32-bit or 64-bit stacks. 230 */ 231 #define WSTATE_KERN 026 232 #define WSTATE_USER 022 233 234 #define CWP 0x01f 235 236 /* 64-byte alignment -- this seems the best place to put this. */ 237 #define BLOCK_SIZE 64 238 #define BLOCK_ALIGN 0x3f 239 240 #if defined(_KERNEL) && !defined(_LOCORE) 241 242 static __inline int getpsr __P((void)); 243 static __inline void setpsr __P((int)); 244 static __inline void spl0 __P((void)); 245 static __inline int splhigh __P((void)); 246 static __inline void splx __P((int)); 247 static __inline int getmid __P((void)); 248 249 /* 250 * GCC pseudo-functions for manipulating PSR (primarily PIL field). 251 */ 252 static __inline int getpsr() 253 { 254 int psr; 255 256 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 257 return (psr); 258 } 259 260 static __inline int getmid() 261 { 262 int mid; 263 264 __asm __volatile("rd %%tbr,%0" : "=r" (mid)); 265 return ((mid >> 20) & 0x3); 266 } 267 268 static __inline void setpsr(newpsr) 269 int newpsr; 270 { 271 __asm __volatile("wr %0,0,%%psr" : : "r" (newpsr)); 272 __asm __volatile("nop; nop; nop"); 273 } 274 275 static __inline void spl0() 276 { 277 int psr, oldipl; 278 279 /* 280 * wrpsr xors two values: we choose old psr and old ipl here, 281 * which gives us the same value as the old psr but with all 282 * the old PIL bits turned off. 283 */ 284 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 285 oldipl = psr & PSR_PIL; 286 __asm __volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl)); 287 288 /* 289 * Three instructions must execute before we can depend 290 * on the bits to be changed. 291 */ 292 __asm __volatile("nop; nop; nop"); 293 } 294 295 /* 296 * PIL 1 through 14 can use this macro. 297 * (spl0 and splhigh are special since they put all 0s or all 1s 298 * into the ipl field.) 299 */ 300 #define _SPLSET(name, newipl) \ 301 static __inline void name __P((void)); \ 302 static __inline void name() \ 303 { \ 304 int psr, oldipl; \ 305 __asm __volatile("rd %%psr,%0" : "=r" (psr)); \ 306 oldipl = psr & PSR_PIL; \ 307 psr &= ~oldipl; \ 308 __asm __volatile("wr %0,%1,%%psr" : : \ 309 "r" (psr), "n" ((newipl) << 8)); \ 310 __asm __volatile("nop; nop; nop"); \ 311 } 312 313 /* Raise IPL and return previous value */ 314 #define _SPLRAISE(name, newipl) \ 315 static __inline int name __P((void)); \ 316 static __inline int name() \ 317 { \ 318 int psr, oldipl; \ 319 __asm __volatile("rd %%psr,%0" : "=r" (psr)); \ 320 oldipl = psr & PSR_PIL; \ 321 if ((newipl << 8) <= oldipl) \ 322 return (oldipl); \ 323 psr &= ~oldipl; \ 324 __asm __volatile("wr %0,%1,%%psr" : : \ 325 "r" (psr), "n" ((newipl) << 8)); \ 326 __asm __volatile("nop; nop; nop"); \ 327 return (oldipl); \ 328 } 329 330 _SPLSET(spllowersoftclock, 1) 331 332 _SPLRAISE(splsoftint, 1) 333 #define splsoftclock splsoftint 334 #define splsoftnet splsoftint 335 336 337 /* audio software interrupts */ 338 _SPLRAISE(splausoft, IPL_SOFTAUDIO) 339 340 /* floppy software interrupts */ 341 _SPLRAISE(splfdsoft, IPL_SOFTFDC) 342 343 /* Block devices */ 344 _SPLRAISE(splbio, IPL_BIO) 345 346 /* tty input runs at software level 6 */ 347 _SPLRAISE(spltty, IPL_TTY) 348 349 /* network hardware interrupts are at level 7 */ 350 _SPLRAISE(splnet, IPL_NET) 351 352 /* 353 * Memory allocation (must be as high as highest network, tty, or disk device) 354 */ 355 _SPLRAISE(splvm, IPL_VM) 356 357 /* clock interrupts at level 10 */ 358 _SPLRAISE(splclock, IPL_CLOCK) 359 360 _SPLRAISE(splsched, IPL_SCHED) 361 _SPLSET(spllowerschedclock, IPL_SCHED) 362 363 /* fd hardware, ts102, and tadpole microcontoller interrupts are at level 11 */ 364 _SPLRAISE(splfd, 11) 365 _SPLRAISE(splts102, 11) 366 367 /* 368 * zs hardware interrupts are at level 12 369 * su (com) hardware interrupts are at level 13 370 * IPL_SERIAL must protect them all. 371 */ 372 _SPLRAISE(splzs, 12) 373 374 _SPLRAISE(splserial, IPL_SERIAL) 375 376 /* audio hardware interrupts are at level 13 */ 377 _SPLRAISE(splaudio, IPL_AUDIO) 378 379 /* second sparc timer interrupts at level 14 */ 380 _SPLRAISE(splstatclock, IPL_STATCLOCK) 381 382 static __inline int splhigh() 383 { 384 int psr, oldipl; 385 386 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 387 __asm __volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL)); 388 __asm __volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \ 389 "r" (psr), "n" (PSR_PIL)); 390 return (oldipl); 391 } 392 393 #define spllock() splhigh() 394 395 /* splx does not have a return value */ 396 static __inline void splx(newipl) 397 int newipl; 398 { 399 int psr; 400 401 __asm __volatile("rd %%psr,%0" : "=r" (psr)); 402 __asm __volatile("wr %0,%1,%%psr" : : \ 403 "r" (psr & ~PSR_PIL), "rn" (newipl)); 404 __asm __volatile("nop; nop; nop"); 405 } 406 #endif /* KERNEL && !_LOCORE */ 407 408 #endif /* PSR_IMPL */ 409
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