pte.h revision 1.13
1 /* $NetBSD: pte.h,v 1.13 1996/02/01 22:32:34 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This software was developed by the Computer Systems Engineering group 8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 9 * contributed to Berkeley. 10 * 11 * All advertising materials mentioning features or use of this software 12 * must display the following acknowledgement: 13 * This product includes software developed by the University of 14 * California, Lawrence Berkeley Laboratory. 15 * 16 * Redistribution and use in source and binary forms, with or without 17 * modification, are permitted provided that the following conditions 18 * are met: 19 * 1. Redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer. 21 * 2. Redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution. 24 * 3. All advertising materials mentioning features or use of this software 25 * must display the following acknowledgement: 26 * This product includes software developed by the University of 27 * California, Berkeley and its contributors. 28 * 4. Neither the name of the University nor the names of its contributors 29 * may be used to endorse or promote products derived from this software 30 * without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 35 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 38 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 39 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 40 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 41 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 42 * SUCH DAMAGE. 43 * 44 * @(#)pte.h 8.1 (Berkeley) 6/11/93 45 */ 46 47 /* 48 * Sun-4 (sort of) and 4c (SparcStation) Page Table Entries 49 * (Sun call them `Page Map Entries'). 50 */ 51 52 #ifndef _LOCORE 53 /* 54 * Segment maps contain `pmeg' (Page Map Entry Group) numbers. 55 * A PMEG is simply an index that names a group of 32 (sun4) or 56 * 64 (sun4c) PTEs. 57 * Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits 58 * to hold the hardware MMU resource number. 59 */ 60 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 61 /* 62 * Region maps contain `smeg' (Segment Entry Group) numbers. 63 * An SMEG is simply an index that names a group of 64 PMEGs. 64 */ 65 typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */ 66 #endif 67 68 /* 69 * Address translation works as follows: 70 * 71 * (for sun4c and 2-level sun4) 72 * 1. test va<31:29> -- these must be 000 or 111 (or you get a fault) 73 * 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number; 74 * use this to index the segment maps, yielding a 7 or 9 bit value. 75 * (for 3-level sun4) 76 * 1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number; 77 * use this to index the region maps, yielding a 10 bit value. 78 * 2. take the value from (1) above and concatenate va<17:12> to 79 * get a `segment map entry' index. This gives a 9 bit value. 80 * (for sun4c) 81 * 3. take the value from (2) above and concatenate va<17:12> to 82 * get a `page map entry' index. This gives a 32-bit PTE. 83 * (for sun4) 84 * 3. take the value from (2 or 3) above and concatenate va<17:13> to 85 * get a `page map entry' index. This gives a 32-bit PTE. 86 * 87 * In other words: 88 * 89 * struct sun4_3_levelmmu_virtual_addr { 90 * u_int va_reg:8, (virtual region) 91 * va_seg:6, (virtual segment) 92 * va_pg:5, (virtual page within segment) 93 * va_off:13; (offset within page) 94 * }; 95 * struct sun4_virtual_addr { 96 * u_int :2, (required to be the same as bit 29) 97 * va_seg:12, (virtual segment) 98 * va_pg:5, (virtual page within segment) 99 * va_off:13; (offset within page) 100 * }; 101 * struct sun4c_virtual_addr { 102 * u_int :2, (required to be the same as bit 29) 103 * va_seg:12, (virtual segment) 104 * va_pg:6, (virtual page within segment) 105 * va_off:12; (offset within page) 106 * }; 107 * 108 * Then, given any `va': 109 * 110 * extern smeg_t regmap[16][1<<8]; (3-level MMU only) 111 * extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4) 112 * extern int ptetable[128][1<<6]; ([512][1<<5] for sun4) 113 * 114 * (the above being in the hardware, accessed as Alternate Address Spaces) 115 * 116 * if (mmu_3l) 117 * physreg = regmap[curr_ctx][va.va_reg]; 118 * physseg = segmap[physreg][va.va_seg]; 119 * else 120 * physseg = segmap[curr_ctx][va.va_seg]; 121 * pte = ptetable[physseg][va.va_pg]; 122 * if (!(pte & PG_V)) TRAP(); 123 * if (writing && !pte.pg_w) TRAP(); 124 * if (usermode && pte.pg_s) TRAP(); 125 * if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 126 * pte |= PG_U; (mark used/accessed) 127 * if (writing) pte |= PG_M; (mark modified) 128 * ptetable[physseg][va.va_pg] = pte; 129 * physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off; 130 */ 131 132 #if defined(MMU_3L) && !defined(SUN4) 133 #error "configuration error" 134 #endif 135 136 #if defined(MMU_3L) 137 extern int mmu_3l; 138 #endif 139 140 #define NBPRG (1 << 24) /* bytes per region */ 141 #define RGSHIFT 24 /* log2(NBPRG) */ 142 #define RGOFSET (NBPRG - 1) /* mask for region offset */ 143 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 144 145 #define NBPSG (1 << 18) /* bytes per segment */ 146 #define SGSHIFT 18 /* log2(NBPSG) */ 147 #define SGOFSET (NBPSG - 1) /* mask for segment offset */ 148 149 /* number of PTEs that map one segment (not number that fit in one segment!) */ 150 #if defined(SUN4) && defined(SUN4C) 151 extern int nptesg; 152 #define NPTESG nptesg /* (which someone will have to initialize) */ 153 #else 154 #define NPTESG (NBPSG / NBPG) 155 #endif 156 157 /* virtual address to virtual region number */ 158 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 159 160 /* virtual address to virtual segment number */ 161 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 162 163 /* virtual address to virtual page number, for Sun-4 and Sun-4c */ 164 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 165 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 166 167 /* truncate virtual address to region base */ 168 #define VA_ROUNDDOWNTOREG(va) ((int)(va) & ~RGOFSET) 169 170 /* truncate virtual address to segment base */ 171 #define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET) 172 173 /* virtual segment to virtual address (must sign extend on holy MMUs!) */ 174 #if defined(MMU_3L) 175 #define VRTOVA(vr) (mmu_3l \ 176 ? ((int)(vr) << RGSHIFT) \ 177 : (((int)(vr) << (RGSHIFT+2)) >> 2)) 178 #define VSTOVA(vr,vs) (mmu_3l \ 179 ? (((int)vr << RGSHIFT) + ((int)vs << SGSHIFT)) \ 180 : ((((int)vr << (RGSHIFT+2)) >> 2) + ((int)vs << SGSHIFT))) 181 #else 182 #define VRTOVA(vr) (((int)vr << (RGSHIFT+2)) >> 2) 183 #define VSTOVA(vr,vs) ((((int)vr << (RGSHIFT+2)) >> 2) + ((int)vs << SGSHIFT)) 184 #endif 185 186 extern int mmu_has_hole; 187 #define VA_INHOLE(va) (mmu_has_hole \ 188 ? ( (unsigned int)(((int)(va) >> PG_VSHIFT) + 1) > 1) \ 189 : 0) 190 191 /* Define the virtual address space hole */ 192 #define MMU_HOLE_START 0x20000000 193 #define MMU_HOLE_END 0xe0000000 194 195 #if defined(SUN4) && defined(SUN4C) 196 #define VA_VPG(va) (cputyp==CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va)) 197 #endif 198 #if defined(SUN4C) && !defined(SUN4) 199 #define VA_VPG(va) VA_SUN4C_VPG(va) 200 #endif 201 #if !defined(SUN4C) && defined(SUN4) 202 #define VA_VPG(va) VA_SUN4_VPG(va) 203 #endif 204 205 /* there is no `struct pte'; we just use `int' */ 206 #define PG_V 0x80000000 207 #define PG_PROT 0x60000000 /* both protection bits */ 208 #define PG_W 0x40000000 /* allowed to write */ 209 #define PG_S 0x20000000 /* supervisor only */ 210 #define PG_NC 0x10000000 /* non-cacheable */ 211 #define PG_TYPE 0x0c000000 /* both type bits */ 212 213 #define PG_OBMEM 0x00000000 /* on board memory */ 214 #define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */ 215 #ifdef SUN4 216 #define PG_VME16 0x08000000 /* 16-bit-data VME space */ 217 #define PG_VME32 0x0c000000 /* 32-bit-data VME space */ 218 #endif 219 220 #define PG_U 0x02000000 221 #define PG_M 0x01000000 222 #define PG_IOC 0x00800000 /* IO-cacheable */ 223 #define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */ 224 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 225 226 #define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */ 227 #define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */ 228 229 /*efine PG_NOACC 0 ** XXX */ 230 #define PG_KR 0x20000000 231 #define PG_KW 0x60000000 232 #define PG_URKR 0 233 #define PG_UW 0x40000000 234 235 #ifdef KGDB 236 /* but we will define one for gdb anyway */ 237 struct pte { 238 u_int pg_v:1, 239 pg_w:1, 240 pg_s:1, 241 pg_nc:1; 242 enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2; 243 u_int pg_u:1, 244 pg_m:1, 245 pg_mbz:5, 246 pg_pfnum:19; 247 }; 248 #endif 249 250 /* 251 * These are needed in the register window code 252 * to check the validity of (ostensible) user stack PTEs. 253 */ 254 #define PG_VSHIFT 29 /* (va>>vshift)==0 or -1 => valid */ 255 /* XXX fix this name, it is a va shift not a pte bit shift! */ 256 257 #define PG_PROTSHIFT 29 258 #define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */ 259 #define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */ 260 261 /* static __inline int PG_VALID(void *va) { 262 register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1); 263 } */ 264 265 #if defined(SUN4M) 266 267 /* 268 * Reference MMU PTE bits. 269 */ 270 #define SRPTE_PPN_MASK 0x07ffff00 271 #define SRPTE_PPN_SHIFT 8 272 #define SRPTE_CACHEABLE 0x00000080 /* Page is cacheable */ 273 #define SRPTE_MOD 0x00000040 /* Page is modified */ 274 #define SRPTE_REF 0x00000020 /* Page is referenced */ 275 #define SRPTE_ACCMASK 0x0000001c /* Access rights mask */ 276 #define SRPTE_ACCSHIFT 2 /* Access rights shift */ 277 #define SRPTE_TYPEMASK 0x00000003 /* PTE Type */ 278 #define SRPTE_PTE 0x00000002 /* A PTE (Page Table Entry) */ 279 #define SRPTE_PTP 0x00000001 /* A PTP (Page Table Pointer) */ 280 281 /* 282 * Reference MMU access permission bits. 283 * format: SRACC_sssuuu, 284 * where <sss> denote the supervisor rights 285 * and <uuu> denote the user rights 286 */ 287 #define SRACC_R__R__ 0 288 #define SRACC_RW_RW_ 1 289 #define SRACC_R_XR_X 2 290 #define SRACC_RWXRWX 3 291 #define SRACC___X__X 4 292 #define SRACC_RW_R__ 5 293 #define SRACC_R_X___ 6 294 #define SRACC_RWX___ 7 295 296 /* 297 * IOMMU PTE bits. 298 */ 299 #define IOPTE_PPN_MASK 0x07ffff00 300 #define IOPTE_PPN_SHIFT 8 301 #define IOPTE_RSVD 0x000000f1 302 #define IOPTE_WRITE 0x00000004 303 #define IOPTE_VALID 0x00000002 304 305 #endif /* SUN4M */ 306
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