pte.h revision 1.15
1 /* $NetBSD: pte.h,v 1.15 1996/03/31 22:06:55 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard University. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgements: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgements: 29 * This product includes software developed by Harvard University. 30 * This product includes software developed by the University of 31 * California, Berkeley and its contributors. 32 * 4. Neither the name of the University nor the names of its contributors 33 * may be used to endorse or promote products derived from this software 34 * without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 46 * SUCH DAMAGE. 47 * 48 * @(#)pte.h 8.1 (Berkeley) 6/11/93 49 * 50 * $Id: pte.h,v 1.15 1996/03/31 22:06:55 pk Exp $ 51 */ 52 53 /* 54 * Sun-4 (sort of), 4c (SparcStation), and 4m Page Table Entries 55 * (Sun calls them `Page Map Entries'). 56 */ 57 58 #ifndef _LOCORE 59 /* 60 * Segment maps contain `pmeg' (Page Map Entry Group) numbers. 61 * A PMEG is simply an index that names a group of 32 (sun4) or 62 * 64 (sun4c) PTEs. 63 * Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits 64 * to hold the hardware MMU resource number. 65 */ 66 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 67 /* 68 * Region maps contain `smeg' (Segment Entry Group) numbers. 69 * An SMEG is simply an index that names a group of 64 PMEGs. 70 */ 71 typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */ 72 #endif 73 74 /* 75 * Address translation works as follows: 76 * 77 * (for sun4c and 2-level sun4) 78 * 1. test va<31:29> -- these must be 000 or 111 (or you get a fault) 79 * 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number; 80 * use this to index the segment maps, yielding a 7 or 9 bit value. 81 * (for 3-level sun4) 82 * 1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number; 83 * use this to index the region maps, yielding a 10 bit value. 84 * 2. take the value from (1) above and concatenate va<17:12> to 85 * get a `segment map entry' index. This gives a 9 bit value. 86 * (for sun4c) 87 * 3. take the value from (2) above and concatenate va<17:12> to 88 * get a `page map entry' index. This gives a 32-bit PTE. 89 * (for sun4) 90 * 3. take the value from (2 or 3) above and concatenate va<17:13> to 91 * get a `page map entry' index. This gives a 32-bit PTE. 92 ** 93 * For sun4m: 94 * 1. Use context_reg<3:0> to index the context table (located at 95 * (context_reg << 2) | ((ctx_tbl_ptr_reg >> 2) << 6) ). This 96 * gives a 32-bit page-table-descriptor (PTP). 97 * 2. Use va<31:24> to index the region table located by the PTP from (1): 98 * PTP<31:6> << 10. This gives another PTP for the segment tables 99 * 3. Use va<23:18> to index the segment table located by the PTP from (2) 100 * as follows: PTP<31:4> << 8. This gives another PTP for the page tbl. 101 * 4. Use va<17:12> to index the page table given by (3)'s PTP: 102 * PTP<31:4> << 8. This gives a 32-bit PTE. 103 * 104 * In other words: 105 * 106 * struct sun4_3_levelmmu_virtual_addr { 107 * u_int va_reg:8, (virtual region) 108 * va_seg:6, (virtual segment) 109 * va_pg:5, (virtual page within segment) 110 * va_off:13; (offset within page) 111 * }; 112 * struct sun4_virtual_addr { 113 * u_int :2, (required to be the same as bit 29) 114 * va_seg:12, (virtual segment) 115 * va_pg:5, (virtual page within segment) 116 * va_off:13; (offset within page) 117 * }; 118 * struct sun4c_virtual_addr { 119 * u_int :2, (required to be the same as bit 29) 120 * va_seg:12, (virtual segment) 121 * va_pg:6, (virtual page within segment) 122 * va_off:12; (offset within page) 123 * }; 124 * 125 * struct sun4m_virtual_addr { 126 * u_int va_reg:8, (virtual region) 127 * va_seg:6, (virtual segment within region) 128 * va_pg:6, (virtual page within segment) 129 * va_off:12; (offset within page) 130 * }; 131 * 132 * Then, given any `va': 133 * 134 * extern smeg_t regmap[16][1<<8]; (3-level MMU only) 135 * extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4) 136 * extern int ptetable[128][1<<6]; ([512][1<<5] for sun4) 137 * 138 * extern u_int s4m_ctxmap[16]; (sun4m SRMMU only) 139 * extern u_int s4m_regmap[16][1<<8]; (sun4m SRMMU only) 140 * extern u_int s4m_segmap[1<<8][1<<6]; (sun4m SRMMU only) 141 * extern u_int s4m_pagmap[1<<14][1<<6]; (sun4m SRMMU only) 142 * 143 * (the above being in the hardware, accessed as Alternate Address Spaces on 144 * all machines but the Sun4m SRMMU, in which case the tables are in physical 145 * kernel memory. In the 4m architecture, the tables are not layed out as 146 * 2-dim arrays, but are sparsely allocated as needed, and point to each 147 * other.) 148 * 149 * if (cputyp==CPU_SUN4M) // SPARC Reference MMU 150 * regptp = s4m_ctxmap[curr_ctx]; 151 * if (!(regptp & SRMMU_TEPTD)) TRAP(); 152 * segptp = *(u_int *)(((regptp & ~0x3) << 4) | va.va_reg); 153 * if (!(segptp & SRMMU_TEPTD)) TRAP(); 154 * pagptp = *(u_int *)(((segptp & ~0x3) << 4) | va.va_seg); 155 * if (!(pagptp & SRMMU_TEPTD)) TRAP(); 156 * pte = *(u_int *)(((pagptp & ~0x3) << 4) | va.va_pg); 157 * if (!(pte & SRMMU_TEPTE)) TRAP(); // like PG_V 158 * if (usermode && PTE_PROT_LEVEL(pte) > 0x5) TRAP(); 159 * if (writing && !PTE_PROT_LEVEL_ALLOWS_WRITING(pte)) TRAP(); 160 * if (!(pte & SRMMU_PG_C)) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 161 * pte |= SRMMU_PG_U; 162 * if (writing) pte |= PG_M; 163 * physaddr = ((pte & SRMMU_PG_PFNUM) << SRMMU_PGSHIFT)|va.va_off; 164 * return; 165 * if (mmu_3l) 166 * physreg = regmap[curr_ctx][va.va_reg]; 167 * physseg = segmap[physreg][va.va_seg]; 168 * else 169 * physseg = segmap[curr_ctx][va.va_seg]; 170 * pte = ptetable[physseg][va.va_pg]; 171 * if (!(pte & PG_V)) TRAP(); 172 * if (writing && !pte.pg_w) TRAP(); 173 * if (usermode && pte.pg_s) TRAP(); 174 * if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 175 * pte |= PG_U; (mark used/accessed) 176 * if (writing) pte |= PG_M; (mark modified) 177 * ptetable[physseg][va.va_pg] = pte; 178 * physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off; 179 */ 180 181 #if defined(MMU_3L) && !defined(SUN4) 182 #error "configuration error" 183 #endif 184 185 #if defined(MMU_3L) 186 extern int mmu_3l; 187 #endif 188 189 #define NBPRG (1 << 24) /* bytes per region */ 190 #define RGSHIFT 24 /* log2(NBPRG) */ 191 #define RGOFSET (NBPRG - 1) /* mask for region offset */ 192 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 193 194 #define NBPSG (1 << 18) /* bytes per segment */ 195 #define SGSHIFT 18 /* log2(NBPSG) */ 196 #define SGOFSET (NBPSG - 1) /* mask for segment offset */ 197 198 /* number of PTEs that map one segment (not number that fit in one segment!) */ 199 #if defined(SUN4) && (defined(SUN4C) || defined(SUN4M)) 200 extern int nptesg; 201 #define NPTESG nptesg /* (which someone will have to initialize) */ 202 #else 203 #define NPTESG (NBPSG / NBPG) 204 #endif 205 206 /* virtual address to virtual region number */ 207 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 208 209 /* virtual address to virtual segment number */ 210 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 211 212 /* virtual address to virtual page number, for Sun-4 and Sun-4c */ 213 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 214 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 215 #define VA_SUN4M_VPG(va) (((int)(va) >> 12) & 63) 216 217 /* virtual address to offset within page */ 218 #define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF) 219 #define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF) 220 #define VA_SUN4M_OFF(va) (((int)(va)) & 0xFFF) 221 222 /* truncate virtual address to region base */ 223 #define VA_ROUNDDOWNTOREG(va) ((int)(va) & ~RGOFSET) 224 225 /* truncate virtual address to segment base */ 226 #define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET) 227 228 /* virtual segment to virtual address (must sign extend on holy MMUs!) */ 229 #if defined(SUN4M) && !(defined(SUN4C) || defined(SUN4)) 230 #define VRTOVA(vr) ((int)(vr) << RGSHIFT) 231 #define VSTOVA(vr,vs) (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT)) 232 #else 233 #if defined(MMU_3L) || defined(SUN4M) /* hairy.. */ 234 #if !defined(MMU_3L) 235 #define _PTE_HAIRY_3L_TEST (cputyp==CPU_SUN4M) 236 #elif !defined(SUN4M) 237 #define _PTE_HAIRY_3L_TEST (mmu_3l) 238 #else 239 #define _PTE_HAIRY_3L_TEST (mmu_3l || cputyp==CPU_SUN4M) 240 #endif 241 #define VRTOVA(vr) (_PTE_HAIRY_3L_TEST \ 242 ? ((int)(vr) << RGSHIFT) \ 243 : (((int)(vr) << (RGSHIFT+2)) >> 2)) 244 #define VSTOVA(vr,vs) (_PTE_HAIRY_3L_TEST \ 245 ? (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT)) \ 246 : ((((int)(vr) << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT))) 247 #else 248 #define VRTOVA(vr) (((int)(vr) << (RGSHIFT+2)) >> 2) 249 #define VSTOVA(vr,vs) ((((int)(vr) << (RGSHIFT+2)) >> 2) + \ 250 ((int)(vs) << SGSHIFT)) 251 #endif 252 #endif 253 254 extern int mmu_has_hole; 255 #define VA_INHOLE(va) (mmu_has_hole \ 256 ? ( (unsigned int)(((int)(va) >> PG_VSHIFT) + 1) > 1) \ 257 : 0) 258 259 /* Define the virtual address space hole */ 260 #define MMU_HOLE_START 0x20000000 261 #define MMU_HOLE_END 0xe0000000 262 263 #if defined(SUN4M) /* Optimization: sun4m, sun4c have same page */ 264 #if defined(SUN4) /* size, so they're used interchangeably */ 265 #define VA_VPG(va) (cputyp==CPU_SUN4 ? VA_SUN4_VPG(va) : VA_SUN4C_VPG(va)) 266 #define VA_OFF(VA) (cputyp==CPU_SUN4 ? VA_SUN4_OFF(va) : VA_SUN4C_OFF(va)) 267 #else 268 #define VA_VPG(va) VA_SUN4M_VPG(va) 269 #define VA_OFF(va) VA_SUN4M_OFF(va) 270 #endif /* defined SUN4 */ 271 #else /* 4m not defined */ 272 #if defined(SUN4) && defined(SUN4C) 273 #define VA_VPG(va) (cputyp==CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va)) 274 #define VA_OFF(va) (cputyp==CPU_SUN4C ? VA_SUN4C_OFF(va) : VA_SUN4_OFF(va)) 275 #endif 276 #if defined(SUN4C) && !defined(SUN4) 277 #define VA_VPG(va) VA_SUN4C_VPG(va) 278 #define VA_OFF(va) VA_SUN4C_OFF(va) 279 #endif 280 #if !defined(SUN4C) && defined(SUN4) 281 #define VA_VPG(va) VA_SUN4_VPG(va) 282 #define VA_OFF(va) VA_SUN4_OFF(va) 283 #endif 284 #endif /* defined 4m */ 285 286 /* there is no `struct pte'; we just use `int'; this is for non-4M only */ 287 #define PG_V 0x80000000 288 #define PG_PROT 0x60000000 /* both protection bits */ 289 #define PG_W 0x40000000 /* allowed to write */ 290 #define PG_S 0x20000000 /* supervisor only */ 291 #define PG_NC 0x10000000 /* non-cacheable */ 292 #define PG_TYPE 0x0c000000 /* both type bits */ 293 294 #define PG_OBMEM 0x00000000 /* on board memory */ 295 #define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */ 296 #define PG_VME16 0x08000000 /* 16-bit-data VME space */ 297 #define PG_VME32 0x0c000000 /* 32-bit-data VME space */ 298 #if defined(SUN4M) 299 #define PG_SUN4M_OBMEM 0x0 /* No type bits=>obmem on 4m */ 300 #define PG_SUN4M_OBIO 0xf /* obio maps to 0xf on 4M */ 301 #define SRMMU_PGTYPE 0xf0000000 /* Top 4 bits of pte PPN give type */ 302 #endif 303 304 #define PG_U 0x02000000 305 #define PG_M 0x01000000 306 #define PG_IOC 0x00800000 307 #define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */ 308 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 309 310 #define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */ 311 #define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */ 312 #define PG_M_SHIFT4M 5 /* shift to get SRMMU_PG_M,R on 4m */ 313 /*efine PG_NOACC 0 ** XXX */ 314 #define PG_KR 0x20000000 315 #define PG_KW 0x60000000 316 #define PG_URKR 0 317 #define PG_UW 0x40000000 318 319 #ifdef KGDB 320 /* but we will define one for gdb anyway */ 321 struct pte { 322 u_int pg_v:1, 323 pg_w:1, 324 pg_s:1, 325 pg_nc:1; 326 enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2; 327 u_int pg_u:1, 328 pg_m:1, 329 pg_mbz:5, 330 pg_pfnum:19; 331 }; 332 #if defined(SUN4M) 333 struct srmmu_pte { 334 u_int pg_pfnum:20, 335 pg_c:1, 336 pg_m:1, 337 pg_u:1; 338 enum pgprot { pprot_r_r, pprot_rw_rw, pprot_rx_rx, pprot_rwx_rwx, 339 pprot_x_x, pprot_r_rw, pprot_n_rx, pprot_n_rwx } 340 pg_prot:3; /* prot. bits: pprot_<user>_<supervisor> */ 341 u_int pg_must_be_2:2; 342 }; 343 #endif 344 #endif 345 346 /* 347 * These are needed in the register window code 348 * to check the validity of (ostensible) user stack PTEs. 349 */ 350 #define PG_VSHIFT 29 /* (va>>vshift)==0 or -1 => valid */ 351 /* XXX fix this name, it is a va shift not a pte bit shift! */ 352 353 #define PG_PROTSHIFT 29 354 #define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */ 355 #define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */ 356 357 /* %%%: Fix above and below for 4m? */ 358 359 /* static __inline int PG_VALID(void *va) { 360 register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1); 361 } */ 362 363 364 /* 365 * Here are the bit definitions for 4M/SRMMU pte's 366 */ 367 /* MMU TABLE ENTRIES */ 368 #define SRMMU_TEINVALID 0x0 /* invalid (serves as !valid bit) */ 369 #define SRMMU_TEPTD 0x1 /* Page Table Descriptor */ 370 #define SRMMU_TEPTE 0x2 /* Page Table Entry */ 371 #define SRMMU_TERES 0x3 /* reserved */ 372 #define SRMMU_TETYPE 0x3 /* mask for table entry type */ 373 /* PTE FIELDS */ 374 #define SRMMU_PPNMASK 0xFFFFFF00 375 #define SRMMU_PPNSHIFT 0x8 376 #define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */ 377 #define SRMMU_L1PPNSHFT 0x14 378 #define SRMMU_L1PPNMASK 0xFFF00000 379 #define SRMMU_L2PPNSHFT 0xE 380 #define SRMMU_L2PPNMASK 0xFC000 381 #define SRMMU_L3PPNSHFT 0x8 382 #define SRMMU_L3PPNMASK 0x3F00 383 /* PTE BITS */ 384 #define SRMMU_PG_C 0x80 /* cacheable */ 385 #define SRMMU_PG_M 0x40 /* modified (dirty) */ 386 #define SRMMU_PG_R 0x20 /* referenced */ 387 #define SRMMU_PGBITSMSK 0xE0 388 /* PTE PROTECTION */ 389 #define SRMMU_PROT_MASK 0x1C /* Mask protection bits out of pte */ 390 #define SRMMU_PROT_SHFT 0x2 391 #define PPROT_R_R 0x0 /* These are in the form: */ 392 #define PPROT_RW_RW 0x4 /* PPROT_<u>_<s> */ 393 #define PPROT_RX_RX 0x8 /* where <u> is the user-mode */ 394 #define PPROT_RWX_RWX 0xC /* permission, and <s> is the */ 395 #define PPROT_X_X 0x10 /* supervisor mode permission. */ 396 #define PPROT_R_RW 0x14 /* R=read, W=write, X=execute */ 397 #define PPROT_N_RX 0x18 /* N=none. */ 398 #define PPROT_N_RWX 0x1C 399 #define PPROT_WRITE 0x4 /* set iff write priv. allowed */ 400 #define PPROT_S 0x18 /* effective S bit */ 401 #define PPROT_U2S_OMASK 0x18 /* OR with prot. to revoke user priv */ 402 /* TABLE SIZES */ 403 #define SRMMU_L1SIZE 0x100 404 #define SRMMU_L2SIZE 0x40 405 #define SRMMU_L3SIZE 0x40 406 407 /* 408 * IOMMU PTE bits. 409 */ 410 #define IOPTE_PPN_MASK 0x07ffff00 411 #define IOPTE_PPN_SHIFT 8 412 #define IOPTE_RSVD 0x000000f1 413 #define IOPTE_WRITE 0x00000004 414 #define IOPTE_VALID 0x00000002 415
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