pte.h revision 1.25
1 /* $NetBSD: pte.h,v 1.25 2002/07/18 02:32:35 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgements: 15 * This product includes software developed by Harvard University. 16 * This product includes software developed by the University of 17 * California, Lawrence Berkeley Laboratory. 18 * 19 * Redistribution and use in source and binary forms, with or without 20 * modification, are permitted provided that the following conditions 21 * are met: 22 * 1. Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * 2. Redistributions in binary form must reproduce the above copyright 25 * notice, this list of conditions and the following disclaimer in the 26 * documentation and/or other materials provided with the distribution. 27 * 3. All advertising materials mentioning features or use of this software 28 * must display the following acknowledgements: 29 * This product includes software developed by Harvard University. 30 * This product includes software developed by the University of 31 * California, Berkeley and its contributors. 32 * 4. Neither the name of the University nor the names of its contributors 33 * may be used to endorse or promote products derived from this software 34 * without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 37 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 39 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 42 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 43 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 44 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 45 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 46 * SUCH DAMAGE. 47 * 48 * @(#)pte.h 8.1 (Berkeley) 6/11/93 49 */ 50 51 #if defined(_KERNEL_OPT) 52 #include "opt_sparc_arch.h" 53 #endif 54 55 /* 56 * Sun-4 (sort of), 4c (SparcStation), and 4m Page Table Entries 57 * (Sun calls them `Page Map Entries'). 58 */ 59 60 #ifndef _LOCORE 61 /* 62 * Segment maps contain `pmeg' (Page Map Entry Group) numbers. 63 * A PMEG is simply an index that names a group of 32 (sun4) or 64 * 64 (sun4c) PTEs. 65 * Depending on the CPU model, we need 7 (sun4c) to 10 (sun4/400) bits 66 * to hold the hardware MMU resource number. 67 */ 68 typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */ 69 /* 70 * Region maps contain `smeg' (Segment Entry Group) numbers. 71 * An SMEG is simply an index that names a group of 64 PMEGs. 72 */ 73 typedef u_char smeg_t; /* 8 bits needed per Sun-4 regmap entry */ 74 #endif 75 76 /* 77 * Address translation works as follows: 78 * 79 * (for sun4c and 2-level sun4) 80 * 1. test va<31:29> -- these must be 000 or 111 (or you get a fault) 81 * 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number; 82 * use this to index the segment maps, yielding a 7 or 9 bit value. 83 * (for 3-level sun4) 84 * 1. concatenate context_reg<3:0> and va<31:24> to get a 8 bit number; 85 * use this to index the region maps, yielding a 10 bit value. 86 * 2. take the value from (1) above and concatenate va<17:12> to 87 * get a `segment map entry' index. This gives a 9 bit value. 88 * (for sun4c) 89 * 3. take the value from (2) above and concatenate va<17:12> to 90 * get a `page map entry' index. This gives a 32-bit PTE. 91 * (for sun4) 92 * 3. take the value from (2 or 3) above and concatenate va<17:13> to 93 * get a `page map entry' index. This gives a 32-bit PTE. 94 ** 95 * For sun4m: 96 * 1. Use context_reg<3:0> to index the context table (located at 97 * (context_reg << 2) | ((ctx_tbl_ptr_reg >> 2) << 6) ). This 98 * gives a 32-bit page-table-descriptor (PTP). 99 * 2. Use va<31:24> to index the region table located by the PTP from (1): 100 * PTP<31:6> << 10. This gives another PTP for the segment tables 101 * 3. Use va<23:18> to index the segment table located by the PTP from (2) 102 * as follows: PTP<31:4> << 8. This gives another PTP for the page tbl. 103 * 4. Use va<17:12> to index the page table given by (3)'s PTP: 104 * PTP<31:4> << 8. This gives a 32-bit PTE. 105 * 106 * In other words: 107 * 108 * struct sun4_3_levelmmu_virtual_addr { 109 * u_int va_reg:8, (virtual region) 110 * va_seg:6, (virtual segment) 111 * va_pg:5, (virtual page within segment) 112 * va_off:13; (offset within page) 113 * }; 114 * struct sun4_virtual_addr { 115 * u_int :2, (required to be the same as bit 29) 116 * va_seg:12, (virtual segment) 117 * va_pg:5, (virtual page within segment) 118 * va_off:13; (offset within page) 119 * }; 120 * struct sun4c_virtual_addr { 121 * u_int :2, (required to be the same as bit 29) 122 * va_seg:12, (virtual segment) 123 * va_pg:6, (virtual page within segment) 124 * va_off:12; (offset within page) 125 * }; 126 * 127 * struct sun4m_virtual_addr { 128 * u_int va_reg:8, (virtual region) 129 * va_seg:6, (virtual segment within region) 130 * va_pg:6, (virtual page within segment) 131 * va_off:12; (offset within page) 132 * }; 133 * 134 * Then, given any `va': 135 * 136 * extern smeg_t regmap[16][1<<8]; (3-level MMU only) 137 * extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4) 138 * extern int ptetable[128][1<<6]; ([512][1<<5] for sun4) 139 * 140 * extern u_int s4m_ctxmap[16]; (sun4m SRMMU only) 141 * extern u_int s4m_regmap[16][1<<8]; (sun4m SRMMU only) 142 * extern u_int s4m_segmap[1<<8][1<<6]; (sun4m SRMMU only) 143 * extern u_int s4m_pagmap[1<<14][1<<6]; (sun4m SRMMU only) 144 * 145 * (the above being in the hardware, accessed as Alternate Address Spaces on 146 * all machines but the Sun4m SRMMU, in which case the tables are in physical 147 * kernel memory. In the 4m architecture, the tables are not layed out as 148 * 2-dim arrays, but are sparsely allocated as needed, and point to each 149 * other.) 150 * 151 * if (cputyp==CPU_SUN4M || cputyp==CPU_SUN4D) // SPARC Reference MMU 152 * regptp = s4m_ctxmap[curr_ctx]; 153 * if (!(regptp & SRMMU_TEPTD)) TRAP(); 154 * segptp = *(u_int *)(((regptp & ~0x3) << 4) | va.va_reg); 155 * if (!(segptp & SRMMU_TEPTD)) TRAP(); 156 * pagptp = *(u_int *)(((segptp & ~0x3) << 4) | va.va_seg); 157 * if (!(pagptp & SRMMU_TEPTD)) TRAP(); 158 * pte = *(u_int *)(((pagptp & ~0x3) << 4) | va.va_pg); 159 * if (!(pte & SRMMU_TEPTE)) TRAP(); // like PG_V 160 * if (usermode && PTE_PROT_LEVEL(pte) > 0x5) TRAP(); 161 * if (writing && !PTE_PROT_LEVEL_ALLOWS_WRITING(pte)) TRAP(); 162 * if (!(pte & SRMMU_PG_C)) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 163 * pte |= SRMMU_PG_U; 164 * if (writing) pte |= PG_M; 165 * physaddr = ((pte & SRMMU_PG_PFNUM) << SRMMU_PGSHIFT)|va.va_off; 166 * return; 167 * if (mmu_3l) 168 * physreg = regmap[curr_ctx][va.va_reg]; 169 * physseg = segmap[physreg][va.va_seg]; 170 * else 171 * physseg = segmap[curr_ctx][va.va_seg]; 172 * pte = ptetable[physseg][va.va_pg]; 173 * if (!(pte & PG_V)) TRAP(); 174 * if (writing && !pte.pg_w) TRAP(); 175 * if (usermode && pte.pg_s) TRAP(); 176 * if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 177 * pte |= PG_U; (mark used/accessed) 178 * if (writing) pte |= PG_M; (mark modified) 179 * ptetable[physseg][va.va_pg] = pte; 180 * physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off; 181 */ 182 183 #if defined(SUN4_MMU3L) && !defined(SUN4) 184 #error "configuration error" 185 #endif 186 187 #define NBPRG (1 << 24) /* bytes per region */ 188 #define RGSHIFT 24 /* log2(NBPRG) */ 189 #define RGOFSET (NBPRG - 1) /* mask for region offset */ 190 #define NSEGRG (NBPRG / NBPSG) /* segments per region */ 191 192 #define NBPSG (1 << 18) /* bytes per segment */ 193 #define SGSHIFT 18 /* log2(NBPSG) */ 194 #define SGOFSET (NBPSG - 1) /* mask for segment offset */ 195 196 /* number of PTEs that map one segment (not number that fit in one segment!) */ 197 #if defined(SUN4) && (defined(SUN4C) || defined(SUN4M) || defined(SUN4D)) 198 extern int nptesg; 199 #define NPTESG nptesg /* (which someone will have to initialize) */ 200 #else 201 #define NPTESG (NBPSG / NBPG) 202 #endif 203 204 /* virtual address to virtual region number */ 205 #define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255) 206 207 /* virtual address to virtual segment number */ 208 #define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63) 209 210 /* virtual address to virtual page number, for Sun-4 and Sun-4c */ 211 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 212 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 213 #define VA_SUN4M_VPG(va) (((int)(va) >> 12) & 63) 214 215 /* virtual address to offset within page */ 216 #define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF) 217 #define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF) 218 #define VA_SUN4M_OFF(va) (((int)(va)) & 0xFFF) 219 220 /* truncate virtual address to region base */ 221 #define VA_ROUNDDOWNTOREG(va) ((int)(va) & ~RGOFSET) 222 223 /* truncate virtual address to segment base */ 224 #define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET) 225 226 /* virtual segment to virtual address (must sign extend on holy MMUs!) */ 227 #define VRTOVA(vr) ((CPU_HAS_SRMMU || HASSUN4_MMU3L) \ 228 ? ((int)(vr) << RGSHIFT) \ 229 : (((int)(vr) << (RGSHIFT+2)) >> 2)) 230 #define VSTOVA(vr,vs) ((CPU_HAS_SRMMU || HASSUN4_MMU3L) \ 231 ? (((int)(vr) << RGSHIFT) + ((int)(vs) << SGSHIFT)) \ 232 : ((((int)(vr) << (RGSHIFT+2)) >> 2) + ((int)(vs) << SGSHIFT))) 233 234 extern int mmu_has_hole; 235 #define VA_INHOLE(va) (mmu_has_hole \ 236 ? ( (unsigned int)(((int)(va) >> PG_VSHIFT) + 1) > 1) \ 237 : 0) 238 239 /* Define the virtual address space hole */ 240 #define MMU_HOLE_START 0x20000000 241 #define MMU_HOLE_END 0xe0000000 242 243 #if defined(SUN4M) || defined(SUN4D) /* Optimization: sun4m, sun4d, sun4c 244 have same page size, so they're 245 used interchangeably */ 246 #if defined(SUN4) 247 #define VA_VPG(va) (cputyp==CPU_SUN4 ? VA_SUN4_VPG(va) : VA_SUN4C_VPG(va)) 248 #define VA_OFF(va) (cputyp==CPU_SUN4 ? VA_SUN4_OFF(va) : VA_SUN4C_OFF(va)) 249 #else 250 #define VA_VPG(va) VA_SUN4M_VPG(va) 251 #define VA_OFF(va) VA_SUN4M_OFF(va) 252 #endif /* defined SUN4 */ 253 #else /* 4m/4d not defined */ 254 #if defined(SUN4) && defined(SUN4C) 255 #define VA_VPG(va) (cputyp==CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va)) 256 #define VA_OFF(va) (cputyp==CPU_SUN4C ? VA_SUN4C_OFF(va) : VA_SUN4_OFF(va)) 257 #endif 258 #if defined(SUN4C) && !defined(SUN4) 259 #define VA_VPG(va) VA_SUN4C_VPG(va) 260 #define VA_OFF(va) VA_SUN4C_OFF(va) 261 #endif 262 #if !defined(SUN4C) && defined(SUN4) 263 #define VA_VPG(va) VA_SUN4_VPG(va) 264 #define VA_OFF(va) VA_SUN4_OFF(va) 265 #endif 266 #endif /* defined 4m */ 267 268 /* there is no `struct pte'; we just use `int'; this is for non-4M only */ 269 #define PG_V 0x80000000 270 #define PG_PROT 0x60000000 /* both protection bits */ 271 #define PG_W 0x40000000 /* allowed to write */ 272 #define PG_S 0x20000000 /* supervisor only */ 273 #define PG_NC 0x10000000 /* non-cacheable */ 274 #define PG_TYPE 0x0c000000 /* both type bits */ 275 276 #define PG_OBMEM 0x00000000 /* on board memory */ 277 #define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */ 278 #define PG_VME16 0x08000000 /* 16-bit-data VME space */ 279 #define PG_VME32 0x0c000000 /* 32-bit-data VME space */ 280 #if defined(SUN4M) || defined(SUN4D) 281 #define PG_SUN4M_OBMEM 0x0 /* No type bits=>obmem on 4m */ 282 #define PG_SUN4M_OBIO 0xf /* obio maps to 0xf on 4M */ 283 #define SRMMU_PGTYPE 0xf0000000 /* Top 4 bits of pte PPN give type */ 284 #endif 285 286 #define PG_U 0x02000000 287 #define PG_M 0x01000000 288 #define PG_IOC 0x00800000 289 #define PG_MBZ 0x00780000 /* unused; must be zero (oh really?) */ 290 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 291 292 #define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */ 293 #define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */ 294 #define PG_M_SHIFT4M 5 /* shift to get SRMMU_PG_M,R on 4m */ 295 /*efine PG_NOACC 0 ** XXX */ 296 #define PG_KR 0x20000000 297 #define PG_KW 0x60000000 298 #define PG_URKR 0 299 #define PG_UW 0x40000000 300 301 #ifdef KGDB 302 /* but we will define one for gdb anyway */ 303 struct pte { 304 u_int pg_v:1, 305 pg_w:1, 306 pg_s:1, 307 pg_nc:1; 308 enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2; 309 u_int pg_u:1, 310 pg_m:1, 311 pg_mbz:5, 312 pg_pfnum:19; 313 }; 314 #if defined(SUN4M) || defined(SUN4D) 315 struct srmmu_pte { 316 u_int pg_pfnum:20, 317 pg_c:1, 318 pg_m:1, 319 pg_u:1; 320 enum pgprot { pprot_r_r, pprot_rw_rw, pprot_rx_rx, pprot_rwx_rwx, 321 pprot_x_x, pprot_r_rw, pprot_n_rx, pprot_n_rwx } 322 pg_prot:3; /* prot. bits: pprot_<user>_<supervisor> */ 323 u_int pg_must_be_2:2; 324 }; 325 #endif 326 #endif 327 328 /* 329 * These are needed in the register window code 330 * to check the validity of (ostensible) user stack PTEs. 331 */ 332 #define PG_VSHIFT 29 /* (va>>vshift)==0 or -1 => valid */ 333 /* XXX fix this name, it is a va shift not a pte bit shift! */ 334 335 #define PG_PROTSHIFT 29 336 #define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */ 337 #define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */ 338 339 /* %%%: Fix above and below for 4m? */ 340 341 /* static __inline int PG_VALID(void *va) { 342 register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1); 343 } */ 344 345 346 /* 347 * Here are the bit definitions for 4M/SRMMU pte's 348 */ 349 /* MMU TABLE ENTRIES */ 350 #define SRMMU_TEINVALID 0x0 /* invalid (serves as !valid bit) */ 351 #define SRMMU_TEPTD 0x1 /* Page Table Descriptor */ 352 #define SRMMU_TEPTE 0x2 /* Page Table Entry */ 353 #define SRMMU_TERES 0x3 /* reserved */ 354 #define SRMMU_TETYPE 0x3 /* mask for table entry type */ 355 /* PTE FIELDS */ 356 #define SRMMU_PPNMASK 0xFFFFFF00 357 #define SRMMU_PPNSHIFT 0x8 358 #define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */ 359 #define SRMMU_L1PPNSHFT 0x14 360 #define SRMMU_L1PPNMASK 0xFFF00000 361 #define SRMMU_L2PPNSHFT 0xE 362 #define SRMMU_L2PPNMASK 0xFC000 363 #define SRMMU_L3PPNSHFT 0x8 364 #define SRMMU_L3PPNMASK 0x3F00 365 /* PTE BITS */ 366 #define SRMMU_PG_C 0x80 /* cacheable */ 367 #define SRMMU_PG_M 0x40 /* modified (dirty) */ 368 #define SRMMU_PG_R 0x20 /* referenced */ 369 #define SRMMU_PGBITSMSK 0xE0 370 /* PTE PROTECTION */ 371 #define SRMMU_PROT_MASK 0x1C /* Mask protection bits out of pte */ 372 #define SRMMU_PROT_SHFT 0x2 373 #define PPROT_R_R 0x0 /* These are in the form: */ 374 #define PPROT_RW_RW 0x4 /* PPROT_<u>_<s> */ 375 #define PPROT_RX_RX 0x8 /* where <u> is the user-mode */ 376 #define PPROT_RWX_RWX 0xC /* permission, and <s> is the */ 377 #define PPROT_X_X 0x10 /* supervisor mode permission. */ 378 #define PPROT_R_RW 0x14 /* R=read, W=write, X=execute */ 379 #define PPROT_N_RX 0x18 /* N=none. */ 380 #define PPROT_N_RWX 0x1C 381 #define PPROT_WRITE 0x4 /* set iff write priv. allowed */ 382 #define PPROT_S 0x18 /* effective S bit */ 383 #define PPROT_U2S_OMASK 0x18 /* OR with prot. to revoke user priv */ 384 /* TABLE SIZES */ 385 #define SRMMU_L1SIZE 0x100 386 #define SRMMU_L2SIZE 0x40 387 #define SRMMU_L3SIZE 0x40 388 389 #define SRMMU_PTE_BITS "\177\020" \ 390 "f\0\2TYPE\0=\1PTD\0=\2PTE\0f\2\3PROT\0" \ 391 "=\0R_R\0=\4RW_RW\0=\10RX_RX\0=\14RWX_RWX\0=\20X_X\0=\24R_RW\0" \ 392 "=\30N_RX\0=\34N_RWX\0" \ 393 "b\5R\0b\6M\0b\7C\0f\10\30PFN\0" 394 395 /* 396 * IOMMU PTE bits. 397 */ 398 #define IOPTE_PPN_MASK 0x07ffff00 399 #define IOPTE_PPN_SHIFT 8 400 #define IOPTE_RSVD 0x000000f1 401 #define IOPTE_WRITE 0x00000004 402 #define IOPTE_VALID 0x00000002 403 404 #define IOMMU_PTE_BITS "\177\020" \ 405 "f\10\23PPN\0b\2W\0b\1V\0" 406 407 408 #if defined(_KERNEL) || defined(_STANDALONE) 409 /* 410 * Macros to get and set the processor context. 411 */ 412 #define getcontext4() lduba(AC_CONTEXT, ASI_CONTROL) 413 #define getcontext4m() lda(SRMMU_CXR, ASI_SRMMU) 414 #define getcontext() (CPU_HAS_SRMMU ? getcontext4m() \ 415 : getcontext4()) 416 417 #define setcontext4(c) stba(AC_CONTEXT, ASI_CONTROL, c) 418 #define setcontext4m(c) sta(SRMMU_CXR, ASI_SRMMU, c) 419 #define setcontext(c) (CPU_HAS_SRMMU ? setcontext4m(c) \ 420 : setcontext4(c)) 421 422 /* sun4/sun4c access to MMU-resident PTEs */ 423 #define getpte4(va) lda(va, ASI_PTE) 424 #define setpte4(va, pte) sta(va, ASI_PTE, pte) 425 426 /* sun4m TLB probe */ 427 #define getpte4m(va) lda((va & 0xFFFFF000) | ASI_SRMMUFP_L3, \ 428 ASI_SRMMUFP) 429 430 #endif /* _KERNEL || _STANDALONE */ 431
Indexes created Mon Sep 29 21:09:56 GMT 2025