pte.h revision 1.3
1 /* 2 * Copyright (c) 1992, 1993 3 * The Regents of the University of California. All rights reserved. 4 * 5 * This software was developed by the Computer Systems Engineering group 6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 7 * contributed to Berkeley. 8 * 9 * All advertising materials mentioning features or use of this software 10 * must display the following acknowledgement: 11 * This product includes software developed by the University of 12 * California, Lawrence Berkeley Laboratory. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions 16 * are met: 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in the 21 * documentation and/or other materials provided with the distribution. 22 * 3. All advertising materials mentioning features or use of this software 23 * must display the following acknowledgement: 24 * This product includes software developed by the University of 25 * California, Berkeley and its contributors. 26 * 4. Neither the name of the University nor the names of its contributors 27 * may be used to endorse or promote products derived from this software 28 * without specific prior written permission. 29 * 30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 40 * SUCH DAMAGE. 41 * 42 * @(#)pte.h 8.1 (Berkeley) 6/11/93 43 * 44 * from: Header: pte.h,v 1.5 92/11/26 02:04:43 torek Exp 45 * $Id: pte.h,v 1.3 1994/09/25 20:50:26 deraadt Exp $ 46 */ 47 48 /* 49 * Sun-4 (sort of) and 4c (SparcStation) Page Table Entries 50 * (Sun call them `Page Map Entries'). 51 */ 52 53 #ifndef LOCORE 54 /* 55 * Segment maps contain `pmeg' (Page Map Entry Group) numbers. 56 * A PMEG is simply an index that names a group of 32 (sun4) or 57 * 64 (sun4c) PTEs. 58 */ 59 typedef u_short pmeg_t; /* 9 bits needed per Sun-4 segmap entry */ 60 #if notdef 61 #ifdef SUN4 62 typedef u_short pmeg_t; /* 9 bits needed per Sun-4 segmap entry */ 63 #else 64 typedef u_char pmeg_t; /* 7 bits needed per Sun-4c segmap entry */ 65 #endif 66 #endif 67 #endif 68 69 /* 70 * Address translation works as follows: 71 * 72 * 1. test va<31:29> -- these must be 000 or 111 (or you get a fault) 73 * 2. concatenate context_reg<2:0> and va<29:18> to get a 15 bit number; 74 * use this to index the segment maps, yeilding a 7 or 9 bit value. 75 * (for sun4c) 76 * 3. take the value from (2) above and concatenate va<17:12> to 77 * get a `page map entry' index. This gives a 32-bit PTE. 78 * (for sun4) 79 * 3. take the value from (2) above and concatenate va<17:13> to 80 * get a `page map entry' index. This gives a 32-bit PTE. 81 * 82 * In other words: 83 * 84 * struct sun4_virtual_addr { 85 * u_int :2, (required to be the same as bit 29) 86 * va_seg:12, (virtual segment) 87 * va_pg:5, (virtual page within segment) 88 * va_off:13; (offset within page) 89 * }; 90 * struct sun4c_virtual_addr { 91 * u_int :2, (required to be the same as bit 29) 92 * va_seg:12, (virtual segment) 93 * va_pg:6, (virtual page within segment) 94 * va_off:12; (offset within page) 95 * }; 96 * 97 * Then, given any `va': 98 * 99 * extern pmeg_t segmap[8][1<<12]; ([16][1<<12] for sun4) 100 * extern int ptetable[128][1<<6]; ([512][1<<5] for sun4) 101 * 102 * (the above being in the hardware, accessed as Alternate Address Spaces) 103 * 104 * physseg = segmap[curr_ctx][va.va_seg]; 105 * pte = ptetable[physseg][va.va_pg]; 106 * if (!(pte & PG_V)) TRAP(); 107 * if (writing && !pte.pg_w) TRAP(); 108 * if (usermode && pte.pg_s) TRAP(); 109 * if (pte & PG_NC) DO_NOT_USE_CACHE_FOR_THIS_ACCESS(); 110 * pte |= PG_U; (mark used/accessed) 111 * if (writing) pte |= PG_M; (mark modified) 112 * ptetable[physseg][va.va_pg] = pte; 113 * physadr = ((pte & PG_PFNUM) << PGSHIFT) | va.va_off; 114 */ 115 116 #define NBPSG (1 << 18) /* bytes per segment */ 117 #define SGSHIFT 18 /* log2(NBPSG) */ 118 #define SGOFSET (NBPSG - 1) /* mask for segment offset */ 119 120 /* number of PTEs that map one segment (not number that fit in one segment!) */ 121 #if defined(SUN4) && defined(SUN4C) 122 extern int nptesg; 123 #define NPTESG nptesg /* (which someone will have to init) */ 124 #else 125 #define NPTESG (NBPSG / NBPG) 126 #endif 127 128 /* virtual address to virtual segment number */ 129 #define VA_VSEG(va) (((int)(va) >> SGSHIFT) & 0xfff) 130 131 /* virtual address to virtual page number, for Sun-4 and Sun-4c */ 132 #define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31) 133 #define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63) 134 135 /* truncate virtual address to segment base */ 136 #define VA_ROUNDDOWNTOSEG(va) ((int)(va) & ~SGOFSET) 137 138 /* virtual segment to virtual address (must sign extend!) */ 139 #define VSTOVA(vseg) (((int)(vseg) << 20) >> 2) 140 141 #ifdef SUN4 142 #ifdef SUN4C 143 #define VA_VPG(va) (cputyp == CPU_SUN4C ? VA_SUN4C_VPG(va) : VA_SUN4_VPG(va)) 144 #else /* sun4 and not sun4c */ 145 #define VA_VPG(va) VA_SUN4_VPG(va) 146 #endif 147 #else /* not sun4; must be 4c */ 148 #define VA_VPG(va) VA_SUN4C_VPG(va) 149 #endif 150 151 /* there is no `struct pte'; we just use `int' */ 152 #define PG_V 0x80000000 153 #define PG_PROT 0x60000000 /* both protection bits */ 154 #define PG_W 0x40000000 /* allowed to write */ 155 #define PG_S 0x20000000 /* supervisor only */ 156 #define PG_NC 0x10000000 /* non-cacheable */ 157 #define PG_TYPE 0x0c000000 /* both type bits */ 158 159 #define PG_OBMEM 0x00000000 /* on board memory */ 160 #define PG_OBIO 0x04000000 /* on board I/O (incl. Sbus on 4c) */ 161 #ifdef SUN4 162 #define PG_VME16 0x08000000 /* 16-bit-data VME space */ 163 #define PG_VME32 0x0c000000 /* 32-bit-data VME space */ 164 #endif 165 166 #define PG_U 0x02000000 167 #define PG_M 0x01000000 168 #define PG_MBZ 0x00f80000 /* unused; must be zero (oh really?) */ 169 #define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */ 170 171 #define PG_TNC_SHIFT 26 /* shift to get PG_TYPE + PG_NC */ 172 #define PG_M_SHIFT 24 /* shift to get PG_M, PG_U */ 173 174 /*efine PG_NOACC 0 ** XXX */ 175 #define PG_KR 0x20000000 176 #define PG_KW 0x60000000 177 #define PG_URKR 0 178 #define PG_UW 0x40000000 179 180 #ifdef KGDB 181 /* but we will define one for gdb anyway */ 182 struct pte { 183 u_int pg_v:1, 184 pg_w:1, 185 pg_s:1, 186 pg_nc:1; 187 enum pgtype { pg_obmem, pg_obio, pg_vme16, pg_vme32 } pg_type:2; 188 u_int pg_u:1, 189 pg_m:1, 190 pg_mbz:5, 191 pg_pfnum:19; 192 }; 193 #endif 194 195 /* 196 * These are needed in the register window code 197 * to check the validity of (ostensible) user stack PTEs. 198 */ 199 #define PG_VSHIFT 30 /* (va>>vshift)==0 or -1 => valid */ 200 /* XXX fix this name, it is a va shift not a pte bit shift! */ 201 202 #define PG_PROTSHIFT 29 203 #define PG_PROTUWRITE 6 /* PG_V,PG_W,!PG_S */ 204 #define PG_PROTUREAD 4 /* PG_V,!PG_W,!PG_S */ 205 206 /* static __inline int PG_VALID(void *va) { 207 register int t = va; t >>= PG_VSHIFT; return (t == 0 || t == -1); 208 } */ 209
Indexes created Fri Sep 26 20:09:58 GMT 2025