reg.h revision 1.2 1 /*
2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
9 * All advertising materials mentioning features or use of this software
10 * must display the following acknowledgement:
11 * This product includes software developed by the University of
12 * California, Lawrence Berkeley Laboratory.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the University of
25 * California, Berkeley and its contributors.
26 * 4. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
41 *
42 * @(#)reg.h 8.1 (Berkeley) 6/11/93
43 *
44 * from: Header: reg.h,v 1.8 92/11/26 02:04:44 torek Exp
45 * $Id: reg.h,v 1.2 1994/02/01 06:01:27 deraadt Exp $
46 */
47
48 #ifndef _MACHINE_REG_H_
49 #define _MACHINE_REG_H_
50
51 /*
52 * Registers passed to trap/syscall/etc.
53 * This structure is known to occupy exactly 80 bytes (see locore.s).
54 * Note, tf_global[0] is not actually written (since g0 is always 0).
55 * (The slot tf_global[0] is used to send a copy of %wim to kernel gdb.
56 * This is known as `cheating'.)
57 */
58 struct trapframe {
59 int tf_psr; /* psr */
60 int tf_pc; /* return pc */
61 int tf_npc; /* return npc */
62 int tf_y; /* %y register */
63 int tf_global[8]; /* global registers in trap's caller */
64 int tf_out[8]; /* output registers in trap's caller */
65 };
66
67 /*
68 * Register windows. Each stack pointer (%o6 aka %sp) in each window
69 * must ALWAYS point to some place at which it is safe to scribble on
70 * 64 bytes. (If not, your process gets mangled.) Furthermore, each
71 * stack pointer should be aligned on an 8-byte boundary (the kernel
72 * as currently coded allows arbitrary alignment, but with a hefty
73 * performance penalty).
74 */
75 struct rwindow {
76 int rw_local[8]; /* %l0..%l7 */
77 int rw_in[8]; /* %i0..%i7 */
78 };
79
80 struct reg {
81 int rw_local[8]; /* %l0..%l7 */
82 int rw_in[8]; /* %i0..%i7 */
83 };
84
85 #include <machine/fsr.h>
86
87 /*
88 * FP coprocessor registers.
89 *
90 * FP_QSIZE is the maximum coprocessor instruction queue depth
91 * of any implementation on which the kernel will run. David Hough:
92 * ``I'd suggest allowing 16 ... allowing an indeterminate variable
93 * size would be even better''. Of course, we cannot do that; we
94 * need to malloc these.
95 */
96 #define FP_QSIZE 16
97
98 struct fp_qentry {
99 int *fq_addr; /* the instruction's address */
100 int fq_instr; /* the instruction itself */
101 };
102 struct fpstate {
103 u_int fs_regs[32]; /* our view is 32 32-bit registers */
104 int fs_fsr; /* %fsr */
105 int fs_qsize; /* actual queue depth */
106 struct fp_qentry fs_queue[FP_QSIZE]; /* queue contents */
107 };
108
109 #endif /* _MACHINE_REG_H_ */
110