bsd_fdintr.s revision 1.10
1 /* $NetBSD: bsd_fdintr.s,v 1.10 1997/03/10 23:08:32 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Paul Kranenburg 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Paul Kranenburg. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef FDC_C_HANDLER 35 #include "assym.h" 36 #include <machine/param.h> 37 #include <machine/psl.h> 38 #include <sparc/sparc/intreg.h> 39 #include <sparc/sparc/auxreg.h> 40 #include <sparc/sparc/vaddrs.h> 41 #include <sparc/dev/fdreg.h> 42 #include <sparc/dev/fdvar.h> 43 44 #define FD_SET_SWINTR_4C \ 45 sethi %hi(INTRREG_VA), %l5; \ 46 ldub [%l5 + %lo(INTRREG_VA)], %l6; \ 47 or %l6, IE_L4, %l6; \ 48 stb %l6, [%l5 + %lo(INTRREG_VA)] 49 50 ! raise(0,PIL_AUSOFT) ! NOTE: CPU#0 and PIL_AUSOFT=4 51 #define FD_SET_SWINTR_4M \ 52 sethi %hi(1 << (16 + 4)), %l5; \ 53 set ICR_PI_SET, %l6; \ 54 st %l5, [%l6] 55 56 /* set software interrupt */ 57 #if (defined(SUN4) || defined(SUN4C)) && !defined(SUN4M) 58 #define FD_SET_SWINTR FD_SET_SWINTR_4C 59 #elif !(defined(SUN4) || defined(SUN4C)) && defined(SUN4M) 60 #define FD_SET_SWINTR FD_SET_SWINTR_4M 61 #else 62 #define FD_SET_SWINTR \ 63 sethi %hi(_cputyp), %l5; \ 64 ld [%l5 + %lo(_cputyp)], %l5; \ 65 cmp %l5, CPU_SUN4M; \ 66 be 8f; \ 67 FD_SET_SWINTR_4C; \ 68 ba,a 9f; \ 69 8: \ 70 FD_SET_SWINTR_4M; \ 71 9: 72 #endif 73 74 /* Timeout waiting for chip ready */ 75 #define POLL_TIMO 100000 76 77 /* 78 * register mnemonics. note overlapping assignments. 79 */ 80 #define R_fdc %l0 81 #define R_msr %l1 82 #define R_fifo %l2 83 #define R_buf %l3 84 #define R_tc %l4 85 #define R_stat %l3 86 #define R_nstat %l4 87 #define R_stcnt %l5 88 /* use %l6 and %l7 as short term temporaries */ 89 90 91 .seg "data" 92 .align 8 93 .global _fdciop 94 /* A save haven for three precious registers */ 95 save_l: 96 .word 0 97 .word 0 98 .word 0 99 /* Pointer to a `struct fdcio', set in fd.c */ 100 _fdciop: 101 .word 0 102 103 .seg "text" 104 .align 4 105 .global _fdchwintr 106 107 _fdchwintr: 108 set save_l, %l7 109 std %l0, [%l7] 110 st %l2, [%l7 + 8] 111 112 ! tally interrupt 113 sethi %hi(_cnt+V_INTR), %l7 114 ld [%l7 + %lo(_cnt+V_INTR)], %l6 115 inc %l6 116 st %l6, [%l7 + %lo(_cnt+V_INTR)] 117 118 ! load fdc, if it's NULL there's nothing to do: schedule soft interrupt 119 sethi %hi(_fdciop), %l7 120 ld [%l7 + %lo(_fdciop)], R_fdc 121 122 ! tally interrupt 123 ld [R_fdc + FDC_EVCNT], %l6 124 inc %l6 125 st %l6, [R_fdc + FDC_EVCNT] 126 127 ! load chips register addresses 128 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr 129 ld [R_fdc + FDC_REG_FIFO], R_fifo ! get chip FIFO reg addr 130 !!ld [R_fdc + FDC_REG_DOR], R_dor ! get chip DOR reg addr 131 132 ! find out what we are supposed to do 133 ld [R_fdc + FDC_ISTATE], %l7 ! examine flags 134 cmp %l7, ISTATE_SENSEI 135 be sensei 136 nop 137 cmp %l7, ISTATE_DMA 138 bne spurious 139 nop 140 141 ! pseudo DMA 142 ld [R_fdc + FDC_TC], R_tc ! residual count 143 ld [R_fdc + FDC_DATA], R_buf ! IO buffer 144 145 ldub [R_msr], %l7 ! get MSR value 146 nextc: 147 btst NE7_RQM, %l7 ! room in fifo? 148 bnz,a 0f 149 btst NE7_NDM, %l7 ! overrun? 150 151 ! we filled/emptied the FIFO; update fdc->sc_buf & fdc->sc_tc 152 st R_tc, [R_fdc + FDC_TC] 153 b x 154 st R_buf, [R_fdc + FDC_DATA] 155 156 0: 157 bz resultphase ! overrun/underrun 158 btst NE7_DIO, %l7 ! IO direction 159 bz 1f 160 deccc R_tc 161 ldub [R_fifo], %l7 ! reading: 162 b 2f 163 stb %l7, [R_buf] ! *fdc->sc_bufp = *reg_fifo 164 165 1: 166 ldub [R_buf], %l7 ! writing: 167 stb %l7, [R_fifo] ! *reg_fifo = *fdc->sc_bufp 168 2: 169 inc R_buf ! fdc->sc_bufp++ 170 bne,a nextc ! if (--fdc->sc_tc) goto ... 171 ldub [R_msr], %l7 ! get MSR value 172 173 ! xfer done: update fdc->sc_buf & fdc->sc_tc, mark istate DONE 174 st R_tc, [R_fdc + FDC_TC] 175 st R_buf, [R_fdc + FDC_DATA] 176 177 ! flip TC bit in auxreg 178 sethi %hi(_auxio_reg), %l6 179 ld [%l6 + %lo(_auxio_reg)], %l6 180 ldub [%l6], %l7 181 or %l7, AUXIO_MB1|AUXIO_FTC, %l7 182 stb %l7, [%l6] 183 184 ! we have some time to kill; anticipate on upcoming 185 ! result phase. 186 add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0] 187 mov -1, %l7 188 st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1; 189 190 ldub [%l6], %l7 191 andn %l7, AUXIO_FTC, %l7 192 or %l7, AUXIO_MB1, %l7 193 stb %l7, [%l6] 194 b resultphase1 195 nop 196 197 spurious: 198 mov ISTATE_SPURIOUS, %l7 199 st %l7, [R_fdc + FDC_ISTATE] 200 b,a ssi 201 202 sensei: 203 ldub [R_msr], %l7 204 set POLL_TIMO, %l6 205 1: deccc %l6 ! timeout? 206 be ssi 207 and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7 208 cmp %l7, NE7_RQM 209 bne,a 1b ! loop till chip ready 210 ldub [R_msr], %l7 211 mov NE7CMD_SENSEI, %l7 212 stb %l7, [R_fifo] 213 214 resultphase: 215 ! prepare for result phase 216 add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0] 217 mov -1, %l7 218 st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1; 219 220 resultphase1: 221 clr R_stcnt 222 ldub [R_msr], %l7 223 set POLL_TIMO, %l6 224 1: deccc %l6 ! timeout? 225 be ssi 226 and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7 227 cmp %l7, NE7_RQM 228 be 3f ! done 229 cmp %l7, (NE7_RQM | NE7_DIO | NE7_CB) 230 bne,a 1b ! loop till chip ready 231 ldub [R_msr], %l7 232 233 cmp R_stcnt, FDC_NSTATUS ! status overrun? 234 bge 2f ! if so, load but dont store 235 ldub [R_fifo], %l7 ! load the status byte 236 stb %l7, [R_stat] 237 inc R_stat 238 inc R_stcnt 239 2: b 1b 240 ldub [R_msr], %l7 241 242 3: 243 ! got status, update sc_nstat and mark istate DONE 244 st R_stcnt, [R_fdc + FDC_NSTAT] 245 mov ISTATE_DONE, %l7 246 st %l7, [R_fdc + FDC_ISTATE] 247 248 ssi: 249 ! set software interrupt 250 FD_SET_SWINTR 251 252 x: 253 /* 254 * Restore psr -- note: psr delay honored by pc restore loads. 255 */ 256 set save_l, %l7 257 ldd [%l7], %l0 258 mov %l0, %psr 259 nop 260 ld [%l7 + 8], %l2 261 jmp %l1 262 rett %l2 263 #endif 264
Indexes created Sun Sep 28 16:09:52 GMT 2025