bsd_fdintr.s revision 1.13
1 /* $NetBSD: bsd_fdintr.s,v 1.13 1998/02/10 14:11:50 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Paul Kranenburg 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Paul Kranenburg. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #include "opt_uvm.h" 35 36 #ifndef FDC_C_HANDLER 37 #include "assym.h" 38 #include <machine/param.h> 39 #include <machine/psl.h> 40 #include <sparc/sparc/intreg.h> 41 #include <sparc/sparc/auxreg.h> 42 #include <sparc/sparc/vaddrs.h> 43 #include <sparc/dev/fdreg.h> 44 #include <sparc/dev/fdvar.h> 45 46 #define FD_SET_SWINTR_4C \ 47 sethi %hi(INTRREG_VA), %l5; \ 48 ldub [%l5 + %lo(INTRREG_VA)], %l6; \ 49 or %l6, IE_L4, %l6; \ 50 stb %l6, [%l5 + %lo(INTRREG_VA)] 51 52 ! raise(0,PIL_AUSOFT) ! NOTE: CPU#0 and PIL_AUSOFT=4 53 #define FD_SET_SWINTR_4M \ 54 sethi %hi(1 << (16 + 4)), %l5; \ 55 set ICR_PI_SET, %l6; \ 56 st %l5, [%l6] 57 58 /* set software interrupt */ 59 #if (defined(SUN4) || defined(SUN4C)) && !defined(SUN4M) 60 #define FD_SET_SWINTR FD_SET_SWINTR_4C 61 #elif !(defined(SUN4) || defined(SUN4C)) && defined(SUN4M) 62 #define FD_SET_SWINTR FD_SET_SWINTR_4M 63 #else 64 #define FD_SET_SWINTR \ 65 sethi %hi(_cputyp), %l5; \ 66 ld [%l5 + %lo(_cputyp)], %l5; \ 67 cmp %l5, CPU_SUN4M; \ 68 be 8f; \ 69 FD_SET_SWINTR_4C; \ 70 ba,a 9f; \ 71 8: \ 72 FD_SET_SWINTR_4M; \ 73 9: 74 #endif 75 76 ! flip TC bit in auxreg 77 ! assumes %l6 remains unchanged between ASSERT and DEASSERT 78 #define FD_ASSERT_TC_4C \ 79 sethi %hi(AUXREG_VA), %l6; \ 80 ldub [%l6 + %lo(AUXREG_VA) + 3], %l7; \ 81 or %l7, AUXIO4C_MB1|AUXIO4C_FTC, %l7; \ 82 stb %l7, [%l6 + %lo(AUXREG_VA) + 3]; 83 84 #define FD_DEASSERT_TC_4C \ 85 ldub [%l6 + %lo(AUXREG_VA) + 3], %l7; \ 86 andn %l7, AUXIO4C_FTC, %l7; \ 87 or %l7, AUXIO4C_MB1, %l7; \ 88 stb %l7, [%l6 + %lo(AUXREG_VA) + 3]; 89 90 ! flip TC bit in auxreg 91 #define FD_ASSERT_TC_4M \ 92 sethi %hi(AUXREG_VA), %l6; \ 93 ldub [%l6 + %lo(AUXREG_VA) + 3], %l7; \ 94 or %l7, AUXIO4M_MB1|AUXIO4M_FTC, %l7; \ 95 stb %l7, [%l6 + %lo(AUXREG_VA) + 3]; 96 97 #define FD_DEASSERT_TC_4M 98 99 /* 100 * flip TC bit in auxreg 101 * assumes %l5 remains unchanged between ASSERT and DEASSERT 102 */ 103 #if (defined(SUN4) || defined(SUN4C)) && !defined(SUN4M) 104 #define FD_ASSERT_TC FD_ASSERT_TC_4C 105 #define FD_DEASSERT_TC FD_DEASSERT_TC_4C 106 #elif !(defined(SUN4) || defined(SUN4C)) && defined(SUN4M) 107 #define FD_ASSERT_TC FD_ASSERT_TC_4M 108 #define FD_DEASSERT_TC FD_DEASSERT_TC_4M 109 #else 110 #define FD_ASSERT_TC \ 111 sethi %hi(_cputyp), %l5; \ 112 ld [%l5 + %lo(_cputyp)], %l5; \ 113 cmp %l5, CPU_SUN4M; \ 114 be 8f; \ 115 nop; \ 116 FD_ASSERT_TC_4C; \ 117 ba,a 9f; \ 118 8: \ 119 FD_ASSERT_TC_4M; \ 120 9: 121 #define FD_DEASSERT_TC \ 122 cmp %l5, CPU_SUN4M; \ 123 be 8f; \ 124 nop; \ 125 FD_DEASSERT_TC_4C; \ 126 ba,a 9f; \ 127 8: \ 128 FD_DEASSERT_TC_4M; \ 129 9: 130 #endif 131 132 133 /* Timeout waiting for chip ready */ 134 #define POLL_TIMO 100000 135 136 /* 137 * register mnemonics. note overlapping assignments. 138 */ 139 #define R_fdc %l0 140 #define R_msr %l1 141 #define R_fifo %l2 142 #define R_buf %l3 143 #define R_tc %l4 144 #define R_stat %l3 145 #define R_nstat %l4 146 #define R_stcnt %l5 147 /* use %l6 and %l7 as short term temporaries */ 148 149 150 .seg "data" 151 .align 8 152 .global _fdciop 153 /* A save haven for three precious registers */ 154 save_l: 155 .word 0 156 .word 0 157 .word 0 158 /* Pointer to a `struct fdcio', set in fd.c */ 159 _fdciop: 160 .word 0 161 162 .seg "text" 163 .align 4 164 .global _fdchwintr 165 166 _fdchwintr: 167 set save_l, %l7 168 std %l0, [%l7] 169 st %l2, [%l7 + 8] 170 171 ! tally interrupt 172 #if defined(UVM) 173 sethi %hi(_uvmexp+V_INTR), %l7 174 ld [%l7 + %lo(_uvmexp+V_INTR)], %l6 175 inc %l6 176 st %l6, [%l7 + %lo(_uvmexp+V_INTR)] 177 #else 178 sethi %hi(_cnt+V_INTR), %l7 179 ld [%l7 + %lo(_cnt+V_INTR)], %l6 180 inc %l6 181 st %l6, [%l7 + %lo(_cnt+V_INTR)] 182 #endif 183 184 ! load fdc, if it's NULL there's nothing to do: schedule soft interrupt 185 sethi %hi(_fdciop), %l7 186 ld [%l7 + %lo(_fdciop)], R_fdc 187 188 ! tally interrupt 189 ld [R_fdc + FDC_EVCNT], %l6 190 inc %l6 191 st %l6, [R_fdc + FDC_EVCNT] 192 193 ! load chips register addresses 194 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr 195 ld [R_fdc + FDC_REG_FIFO], R_fifo ! get chip FIFO reg addr 196 !!ld [R_fdc + FDC_REG_DOR], R_dor ! get chip DOR reg addr 197 198 ! find out what we are supposed to do 199 ld [R_fdc + FDC_ISTATE], %l7 ! examine flags 200 cmp %l7, ISTATE_SENSEI 201 be sensei 202 nop 203 cmp %l7, ISTATE_DMA 204 bne spurious 205 nop 206 207 ! pseudo DMA 208 ld [R_fdc + FDC_TC], R_tc ! residual count 209 ld [R_fdc + FDC_DATA], R_buf ! IO buffer 210 211 ldub [R_msr], %l7 ! get MSR value 212 nextc: 213 btst NE7_RQM, %l7 ! room in fifo? 214 bnz,a 0f 215 btst NE7_NDM, %l7 ! overrun? 216 217 ! we filled/emptied the FIFO; update fdc->sc_buf & fdc->sc_tc 218 st R_tc, [R_fdc + FDC_TC] 219 b x 220 st R_buf, [R_fdc + FDC_DATA] 221 222 0: 223 bz resultphase ! overrun/underrun 224 btst NE7_DIO, %l7 ! IO direction 225 bz 1f 226 deccc R_tc 227 ldub [R_fifo], %l7 ! reading: 228 b 2f 229 stb %l7, [R_buf] ! *fdc->sc_bufp = *reg_fifo 230 231 1: 232 ldub [R_buf], %l7 ! writing: 233 stb %l7, [R_fifo] ! *reg_fifo = *fdc->sc_bufp 234 2: 235 inc R_buf ! fdc->sc_bufp++ 236 bne,a nextc ! if (--fdc->sc_tc) goto ... 237 ldub [R_msr], %l7 ! get MSR value 238 239 ! xfer done: update fdc->sc_buf & fdc->sc_tc, mark istate DONE 240 st R_tc, [R_fdc + FDC_TC] 241 st R_buf, [R_fdc + FDC_DATA] 242 243 ! flip TC bit in auxreg 244 FD_ASSERT_TC 245 246 ! we have some time to kill; anticipate on upcoming 247 ! result phase. 248 add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0] 249 mov -1, %l7 250 st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1; 251 252 FD_DEASSERT_TC 253 b,a resultphase1 254 255 spurious: 256 mov ISTATE_SPURIOUS, %l7 257 st %l7, [R_fdc + FDC_ISTATE] 258 b,a ssi 259 260 sensei: 261 ldub [R_msr], %l7 262 set POLL_TIMO, %l6 263 1: deccc %l6 ! timeout? 264 be ssi 265 and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7 266 cmp %l7, NE7_RQM 267 bne,a 1b ! loop till chip ready 268 ldub [R_msr], %l7 269 mov NE7CMD_SENSEI, %l7 270 stb %l7, [R_fifo] 271 272 resultphase: 273 ! prepare for result phase 274 add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0] 275 mov -1, %l7 276 st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1; 277 278 resultphase1: 279 clr R_stcnt 280 ldub [R_msr], %l7 281 set POLL_TIMO, %l6 282 1: deccc %l6 ! timeout? 283 be ssi 284 and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7 285 cmp %l7, NE7_RQM 286 be 3f ! done 287 cmp %l7, (NE7_RQM | NE7_DIO | NE7_CB) 288 bne,a 1b ! loop till chip ready 289 ldub [R_msr], %l7 290 291 cmp R_stcnt, FDC_NSTATUS ! status overrun? 292 bge 2f ! if so, load but dont store 293 ldub [R_fifo], %l7 ! load the status byte 294 stb %l7, [R_stat] 295 inc R_stat 296 inc R_stcnt 297 2: b 1b 298 ldub [R_msr], %l7 299 300 3: 301 ! got status, update sc_nstat and mark istate DONE 302 st R_stcnt, [R_fdc + FDC_NSTAT] 303 mov ISTATE_DONE, %l7 304 st %l7, [R_fdc + FDC_ISTATE] 305 306 ssi: 307 ! set software interrupt 308 FD_SET_SWINTR 309 310 x: 311 /* 312 * Restore psr -- note: psr delay honored by pc restore loads. 313 */ 314 set save_l, %l7 315 ldd [%l7], %l0 316 mov %l0, %psr 317 nop 318 ld [%l7 + 8], %l2 319 jmp %l1 320 rett %l2 321 #endif 322
Indexes created Fri Sep 26 20:09:58 GMT 2025