bsd_fdintr.s revision 1.2
1 /* 2 * Copyright (c) 1995 Paul Kranenburg 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Paul Kranenburg. 16 * 4. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * 30 * $NetBSD: bsd_fdintr.s,v 1.2 1995/03/02 20:47:11 pk Exp $ 31 */ 32 33 #ifndef FDC_C_HANDLER 34 #ifndef LOCORE 35 #define LOCORE 36 #endif 37 #include "assym.s" 38 #include <sparc/sparc/intreg.h> 39 #include <sparc/sparc/auxreg.h> 40 #include <sparc/sparc/vaddrs.h> 41 #include <sparc/dev/fdreg.h> 42 #include <sparc/dev/fdvar.h> 43 /* XXX this goes in a header file -- currently, it's hidden in locore.s */ 44 #define INTREG_ADDR 0xf8002000 45 46 /* Timeout waiting for chip ready */ 47 #define POLL_TIMO 100000 48 49 /* 50 * register mnemonics. note overlapping assignments. 51 */ 52 #define R_fdc %l0 53 #define R_msr %l1 54 #define R_fifo %l2 55 #define R_buf %l3 56 #define R_tc %l4 57 #define R_stat %l3 58 #define R_nstat %l4 59 #define R_stcnt %l5 60 /* use %l6 and %l7 as short term temporaries */ 61 62 63 .seg "data" 64 .align 8 65 .global _fdciop 66 /* A save haven for three precious registers */ 67 save_l: 68 .word 0 69 .word 0 70 .word 0 71 /* Pointer to a `struct fdcio', set in fd.c */ 72 _fdciop: 73 .word 0 74 75 .seg "text" 76 .align 4 77 .global _fdchwintr 78 79 _fdchwintr: 80 set save_l, %l7 81 std %l0, [%l7] 82 st %l2, [%l7 + 8] 83 84 ! tally interrupt 85 sethi %hi(_cnt+V_INTR), %l7 86 ld [%l7 + %lo(_cnt+V_INTR)], %l6 87 inc %l6 88 st %l6, [%l7 + %lo(_cnt+V_INTR)] 89 90 ! load fdc, if it's NULL there's nothing to do: schedule soft interrupt 91 sethi %hi(_fdciop), %l7 92 ld [%l7 + %lo(_fdciop)], R_fdc 93 94 ! load chips register addresses 95 ld [R_fdc + FDC_REG_MSR], R_msr ! get chip MSR reg addr 96 ld [R_fdc + FDC_REG_FIFO], R_fifo ! get chip FIFO reg addr 97 !!ld [R_fdc + FDC_REG_DOR], R_dor ! get chip DOR reg addr 98 99 ! find out what we are supposed to do 100 ld [R_fdc + FDC_ISTATE], %l7 ! examine flags 101 cmp %l7, ISTATE_SENSEI 102 be sensei 103 nop 104 cmp %l7, ISTATE_DMA 105 bne spurious 106 nop 107 108 ! pseudo DMA 109 ld [R_fdc + FDC_TC], R_tc ! residual count 110 ld [R_fdc + FDC_DATA], R_buf ! IO buffer 111 112 ldub [R_msr], %l7 ! get MSR value 113 nextc: 114 btst NE7_RQM, %l7 ! room in fifo? 115 bnz,a 0f 116 btst NE7_NDM, %l7 ! overrun? 117 118 ! we filled/emptied the FIFO; update fdc->sc_buf & fdc->sc_tc 119 st R_tc, [R_fdc + FDC_TC] 120 b x 121 st R_buf, [R_fdc + FDC_DATA] 122 123 0: 124 bz resultphase ! overrun/underrun 125 btst NE7_DIO, %l7 ! IO direction 126 bz 1f 127 deccc R_tc 128 ldub [R_fifo], %l7 ! reading: 129 b 2f 130 stb %l7, [R_buf] ! *fdc->sc_bufp = *reg_fifo 131 132 1: 133 ldub [R_buf], %l7 ! writing: 134 stb %l7, [R_fifo] ! *reg_fifo = *fdc->sc_bufp 135 2: 136 inc R_buf ! fdc->sc_bufp++ 137 bne,a nextc ! if (--fdc->sc_tc) goto ... 138 ldub [R_msr], %l7 ! get MSR value 139 140 ! xfer done: update fdc->sc_buf & fdc->sc_tc, mark istate IDLE 141 st R_tc, [R_fdc + FDC_TC] 142 st R_buf, [R_fdc + FDC_DATA] 143 144 ! flip TC bit in auxreg 145 sethi %hi(_auxio_reg), %l6 146 ld [%l6 + %lo(_auxio_reg)], %l6 147 ldub [%l6], %l7 148 or %l7, AUXIO_MB1|AUXIO_FTC, %l7 149 stb %l7, [%l6] 150 151 ! we have some time to kill; anticipate on upcoming 152 ! result phase. 153 add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0] 154 mov -1, %l7 155 st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1; 156 157 ldub [%l6], %l7 158 andn %l7, AUXIO_FTC, %l7 159 or %l7, AUXIO_MB1, %l7 160 stb %l7, [%l6] 161 b resultphase1 162 nop 163 164 spurious: 165 mov ISTATE_SPURIOUS, %l7 166 st %l7, [R_fdc + FDC_ISTATE] 167 b,a ssi 168 169 sensei: 170 ldub [R_msr], %l7 171 set POLL_TIMO, %l6 172 1: deccc %l6 ! timeout? 173 be ssi 174 and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7 175 cmp %l7, NE7_RQM 176 bne,a 1b ! loop till chip ready 177 ldub [R_msr], %l7 178 mov NE7CMD_SENSEI, %l7 179 stb %l7, [R_fifo] 180 181 resultphase: 182 ! prepare for result phase 183 add R_fdc, FDC_STATUS, R_stat ! &fdc->sc_status[0] 184 mov -1, %l7 185 st %l7, [R_fdc + FDC_NSTAT] ! fdc->sc_nstat = -1; 186 187 resultphase1: 188 clr R_stcnt 189 ldub [R_msr], %l7 190 set POLL_TIMO, %l6 191 1: deccc %l6 ! timeout? 192 be ssi 193 and %l7, (NE7_RQM | NE7_DIO | NE7_CB), %l7 194 cmp %l7, NE7_RQM 195 be 3f ! done 196 cmp %l7, (NE7_RQM | NE7_DIO | NE7_CB) 197 bne,a 1b ! loop till chip ready 198 ldub [R_msr], %l7 199 200 cmp R_stcnt, FDC_NSTATUS ! status overrun? 201 bge 2f ! if so, load but dont store 202 ldub [R_fifo], %l7 ! load the status byte 203 stb %l7, [R_stat] 204 inc R_stat 205 inc R_stcnt 206 2: b 1b 207 ldub [R_msr], %l7 208 209 3: 210 ! got status, update sc_nstat and mark istate IDLE 211 st R_stcnt, [R_fdc + FDC_NSTAT] 212 mov ISTATE_IDLE, %l7 213 st %l7, [R_fdc + FDC_ISTATE] 214 215 ssi: 216 ! set software interrupt 217 sethi %hi(INTREG_ADDR), %l7 218 ldsb [%l7 + %lo(INTREG_ADDR)], %l6 219 or %l6, IE_L4, %l6 220 stb %l6, [%l7 + %lo(INTREG_ADDR)] 221 222 x: 223 /* 224 * Restore psr -- note: psr delay honored by pc restore loads. 225 */ 226 set save_l, %l7 227 ldd [%l7], %l0 228 mov %l0, %psr 229 nop 230 ld [%l7 + 8], %l2 231 jmp %l1 232 rett %l2 233 #endif 234
Indexes created Thu Sep 25 16:09:42 GMT 2025