iommu.c revision 1.1
1 /* $NetBSD: iommu.c,v 1.1 1996/03/31 23:09:32 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard University. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <vm/vm.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/ctlreg.h> 46 #include <sparc/sparc/asm.h> 47 #include <sparc/sparc/vaddrs.h> 48 #include <sparc/sparc/iommureg.h> 49 50 struct iommu_softc { 51 struct device sc_dev; /* base device */ 52 struct iommureg *sc_reg; 53 u_int sc_pagesize; 54 u_int sc_range; 55 u_int sc_dvmabase; 56 iopte_t *sc_ptes; 57 int sc_hasiocache; 58 }; 59 struct iommu_softc *iommu_sc;/*XXX*/ 60 int has_iocache; 61 62 63 /* autoconfiguration driver */ 64 int iommu_print __P((void *, char *)); 65 void iommu_attach __P((struct device *, struct device *, void *)); 66 int iommu_match __P((struct device *, void *, void *)); 67 68 struct cfattach iommu_ca = { 69 sizeof(struct iommu_softc), iommu_match, iommu_attach 70 }; 71 72 struct cfdriver iommu_cd = { 73 NULL, "iommu", DV_DULL 74 }; 75 76 /* 77 * Print the location of some iommu-attached device (called just 78 * before attaching that device). If `iommu' is not NULL, the 79 * device was found but not configured; print the iommu as well. 80 * Return UNCONF (config_find ignores this if the device was configured). 81 */ 82 int 83 iommu_print(args, iommu) 84 void *args; 85 char *iommu; 86 { 87 register struct confargs *ca = args; 88 89 if (iommu) 90 printf("%s at %s", ca->ca_ra.ra_name, iommu); 91 return (UNCONF); 92 } 93 94 int 95 iommu_match(parent, vcf, aux) 96 struct device *parent; 97 void *vcf, *aux; 98 { 99 struct cfdata *cf = vcf; 100 register struct confargs *ca = aux; 101 register struct romaux *ra = &ca->ca_ra; 102 103 if (CPU_ISSUN4OR4C) 104 return (0); 105 return (strcmp(cf->cf_driver->cd_name, ra->ra_name) == 0); 106 } 107 108 /* 109 * Attach the iommu. 110 */ 111 void 112 iommu_attach(parent, self, aux) 113 struct device *parent; 114 struct device *self; 115 void *aux; 116 { 117 register struct iommu_softc *sc = (struct iommu_softc *)self; 118 struct confargs oca, *ca = aux; 119 register struct romaux *ra = &ca->ca_ra; 120 register int node; 121 register char *name; 122 register u_int pbase, pa; 123 register int i, mmupcrsav, s, wierdviking = 0; 124 register iopte_t *tpte_p; 125 extern u_int *kernel_iopte_table; 126 extern u_int kernel_iopte_table_pa; 127 128 /*XXX-GCC!*/mmupcrsav=0; 129 iommu_sc = sc; 130 /* 131 * XXX there is only one iommu, for now -- do not know how to 132 * address children on others 133 */ 134 if (sc->sc_dev.dv_unit > 0) { 135 printf(" unsupported\n"); 136 return; 137 } 138 node = ra->ra_node; 139 140 #if 0 141 if (ra->ra_vaddr) 142 sc->sc_reg = (struct iommureg *)ca->ca_ra.ra_vaddr; 143 #else 144 /* 145 * Map registers into our space. The PROM may have done this 146 * already, but I feel better if we have our own copy. Plus, the 147 * prom doesn't map the entire register set 148 * 149 * XXX struct iommureg is bigger than ra->ra_len; what are the 150 * other fields for? 151 */ 152 sc->sc_reg = (struct iommureg *) 153 mapdev(ra->ra_reg, 0, 0, ra->ra_len, ra->ra_iospace); 154 #endif 155 156 sc->sc_hasiocache = node_has_property(node, "cache-coherence?"); 157 has_iocache = sc->sc_hasiocache; /* Set global flag */ 158 159 sc->sc_pagesize = getpropint(node, "page-size", NBPG), 160 sc->sc_range = (1 << 24) << 161 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 162 #if 0 163 sc->sc_dvmabase = (0 - sc->sc_range); 164 #endif 165 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 166 (14 - IOMMU_BAR_IBASHFT); 167 168 /* 169 * Now we build our own copy of the IOMMU page tables. We need to 170 * do this since we're going to change the range to give us 64M of 171 * mappings, and thus we can move DVMA space down to 0xfd000000 to 172 * give us lots of space and to avoid bumping into the PROM, etc. 173 * 174 * XXX Note that this is rather messy. 175 */ 176 sc->sc_ptes = (iopte_t *) kernel_iopte_table; 177 178 /* 179 * Now discache the page tables so that the IOMMU sees our 180 * changes. 181 */ 182 kvm_uncache((caddr_t)sc->sc_ptes, 183 (((0 - DVMA4M_BASE)/sc->sc_pagesize) * sizeof(iopte_t)) / NBPG); 184 185 /* 186 * Ok. We've got to read in the original table using MMU bypass, 187 * and copy all of its entries to the appropriate place in our 188 * new table, even if the sizes are different. 189 * This is pretty easy since we know DVMA ends at 0xffffffff. 190 * 191 * XXX: PGOFSET, NBPG assume same page size as SRMMU 192 */ 193 if ((getpsr() & 0x40000000) && (!(lda(SRMMU_PCR,ASI_SRMMU) & 0x800))) { 194 wierdviking = 1; 195 sta(SRMMU_PCR, ASI_SRMMU, /* set MMU AC bit */ 196 ((mmupcrsav = lda(SRMMU_PCR,ASI_SRMMU)) | SRMMU_PCR_AC)); 197 } 198 199 for (tpte_p = &sc->sc_ptes[((0 - DVMA4M_BASE)/NBPG) - 1], 200 pa = (u_int)pbase - sizeof(iopte_t) + 201 ((u_int)sc->sc_range/NBPG)*sizeof(iopte_t); 202 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 203 tpte_p--, pa -= sizeof(iopte_t)) { 204 205 IOMMU_FLUSHPAGE(sc, 206 (tpte_p - &sc->sc_ptes[0])*NBPG + DVMA4M_BASE); 207 *tpte_p = lda(pa, ASI_BYPASS); 208 } 209 if (wierdviking) { /* restore mmu after bug-avoidance */ 210 sta(SRMMU_PCR, ASI_SRMMU, mmupcrsav); 211 } 212 213 /* 214 * Now we can install our new pagetable into the IOMMU 215 */ 216 sc->sc_range = 0 - DVMA4M_BASE; 217 sc->sc_dvmabase = DVMA4M_BASE; 218 219 /* calculate log2(sc->sc_range/16MB) */ 220 i = ffs(sc->sc_range/(1 << 24)) - 1; 221 if ((1 << i) != (sc->sc_range/(1 << 24))) 222 panic("bad iommu range: %d\n",i); 223 224 s = splhigh(); 225 IOMMU_FLUSHALL(sc); 226 227 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 228 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 229 sc->sc_reg->io_bar = (kernel_iopte_table_pa >> 4) & IOMMU_BAR_IBA; 230 231 IOMMU_FLUSHALL(sc); 232 splx(s); 233 234 printf(": version %x/%x, page-size %d, range %dMB\n", 235 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 236 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 237 sc->sc_pagesize, 238 sc->sc_range >> 20); 239 240 /* Propagate bootpath */ 241 if (ra->ra_bp != NULL && strcmp(ra->ra_bp->name, "iommu") == 0) 242 oca.ca_ra.ra_bp = ra->ra_bp + 1; 243 else 244 oca.ca_ra.ra_bp = NULL; 245 246 /* 247 * Loop through ROM children (expect Sbus among them). 248 */ 249 for (node = firstchild(node); node; node = nextsibling(node)) { 250 name = getpropstring(node, "name"); 251 if (!romprop(&oca.ca_ra, name, node)) 252 continue; 253 oca.ca_bustype = BUS_MAIN; /* ??? */ 254 (void) config_found(&sc->sc_dev, (void *)&oca, iommu_print); 255 } 256 } 257 258 void 259 iommu_enter(va, pa) 260 u_int va, pa; 261 { 262 struct iommu_softc *sc = iommu_sc; 263 int pte; 264 265 #ifdef DEBUG 266 if (va < sc->sc_dvmabase) 267 panic("iommu_enter: va 0x%x not in DVMA space",va); 268 #endif 269 270 pte = atop(pa) << IOPTE_PPNSHFT; 271 pte &= IOPTE_PPN; 272 pte |= IOPTE_V | IOPTE_W; 273 sc->sc_ptes[atop(va - sc->sc_dvmabase)] = pte; 274 IOMMU_FLUSHPAGE(sc, va); 275 } 276 277 /* 278 * iommu_clear: clears mappings created by iommu_enter 279 */ 280 void 281 iommu_remove(va, len) 282 register u_int va, len; 283 { 284 register struct iommu_softc *sc = iommu_sc; 285 286 #ifdef DEBUG 287 if (va < sc->sc_dvmabase) 288 panic("iommu_enter: va 0x%x not in DVMA space", va); 289 #endif 290 291 while (len > 0) { 292 #ifdef notyet 293 #ifdef DEBUG 294 if ((sc->sc_ptes[atop(va - sc->sc_dvmabase)] & IOPTE_V) == 0) 295 panic("iommu_clear: clearing invalid pte at va 0x%x", 296 va); 297 #endif 298 #endif 299 sc->sc_ptes[atop(va - sc->sc_dvmabase)] = 0; 300 sta(sc->sc_ptes + atop(va - sc->sc_dvmabase), ASI_BYPASS, 0); 301 IOMMU_FLUSHPAGE(sc, va); 302 len -= sc->sc_pagesize; 303 va += sc->sc_pagesize; 304 } 305 } 306 307 #if 0 /* These registers aren't there??? */ 308 void 309 iommu_error() 310 { 311 struct iommu_softc *sc = X; 312 struct iommureg *iop = sc->sc_reg; 313 314 printf("iommu: afsr %x, afar %x\n", iop->io_afsr, iop->io_afar); 315 printf("iommu: mfsr %x, mfar %x\n", iop->io_mfsr, iop->io_mfar); 316 } 317 int 318 iommu_alloc(va, len) 319 u_int va, len; 320 { 321 struct iommu_softc *sc = X; 322 int off, tva, pa, iovaddr, pte; 323 324 off = (int)va & PGOFSET; 325 len = round_page(len + off); 326 va -= off; 327 328 if ((int)sc->sc_dvmacur + len > 0) 329 sc->sc_dvmacur = sc->sc_dvmabase; 330 331 iovaddr = tva = sc->sc_dvmacur; 332 sc->sc_dvmacur += len; 333 while (len) { 334 pa = pmap_extract(pmap_kernel(), va); 335 336 #define IOMMU_PPNSHIFT 8 337 #define IOMMU_V 0x00000002 338 #define IOMMU_W 0x00000004 339 340 pte = atop(pa) << IOMMU_PPNSHIFT; 341 pte |= IOMMU_V | IOMMU_W; 342 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 343 sc->sc_reg->io_flushpage = tva; 344 len -= NBPG; 345 va += NBPG; 346 tva += NBPG; 347 } 348 return iovaddr + off; 349 } 350 #endif 351
Indexes created Tue Sep 30 20:09:53 GMT 2025