iommu.c revision 1.35
1 /* $NetBSD: iommu.c,v 1.35 1999/07/08 18:08:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/malloc.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <vm/vm.h> 46 #include <vm/vm_kern.h> 47 48 #include <uvm/uvm_extern.h> 49 #include <uvm/uvm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <machine/autoconf.h> 54 #include <machine/ctlreg.h> 55 #include <sparc/sparc/asm.h> 56 #include <sparc/sparc/vaddrs.h> 57 #include <sparc/sparc/cpuvar.h> 58 #include <sparc/sparc/iommureg.h> 59 #include <sparc/sparc/iommuvar.h> 60 61 struct iommu_softc { 62 struct device sc_dev; /* base device */ 63 struct iommureg *sc_reg; 64 u_int sc_pagesize; 65 u_int sc_range; 66 bus_addr_t sc_dvmabase; 67 iopte_t *sc_ptes; 68 int sc_hasiocache; 69 }; 70 struct iommu_softc *iommu_sc;/*XXX*/ 71 int has_iocache; 72 u_long dvma_cachealign; 73 74 /* 75 * Note: operations on the extent map are being protected with 76 * splhigh(), since we cannot predict at which interrupt priority 77 * our clients will run. 78 */ 79 struct extent *iommu_dvmamap; 80 81 82 /* autoconfiguration driver */ 83 int iommu_print __P((void *, const char *)); 84 void iommu_attach __P((struct device *, struct device *, void *)); 85 int iommu_match __P((struct device *, struct cfdata *, void *)); 86 87 struct cfattach iommu_ca = { 88 sizeof(struct iommu_softc), iommu_match, iommu_attach 89 }; 90 91 /* IOMMU DMA map functions */ 92 int iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 93 bus_size_t, struct proc *, int)); 94 int iommu_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, 95 struct mbuf *, int)); 96 int iommu_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, 97 struct uio *, int)); 98 int iommu_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 99 bus_dma_segment_t *, int, bus_size_t, int)); 100 void iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 101 void iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 102 bus_size_t, int)); 103 104 int iommu_dmamem_alloc __P((bus_dma_tag_t tag, bus_size_t size, 105 bus_size_t alignment, bus_size_t boundary, 106 bus_dma_segment_t *segs, int nsegs, int *rsegs, int flags)); 107 void iommu_dmamem_free __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 108 int nsegs)); 109 int iommu_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 110 int nsegs, size_t size, caddr_t *kvap, int flags)); 111 int iommu_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 112 int nsegs, int off, int prot, int flags)); 113 114 115 struct sparc_bus_dma_tag iommu_dma_tag = { 116 NULL, 117 _bus_dmamap_create, 118 _bus_dmamap_destroy, 119 iommu_dmamap_load, 120 iommu_dmamap_load_mbuf, 121 iommu_dmamap_load_uio, 122 iommu_dmamap_load_raw, 123 iommu_dmamap_unload, 124 iommu_dmamap_sync, 125 126 iommu_dmamem_alloc, 127 iommu_dmamem_free, 128 iommu_dmamem_map, 129 _bus_dmamem_unmap, 130 iommu_dmamem_mmap 131 }; 132 /* 133 * Print the location of some iommu-attached device (called just 134 * before attaching that device). If `iommu' is not NULL, the 135 * device was found but not configured; print the iommu as well. 136 * Return UNCONF (config_find ignores this if the device was configured). 137 */ 138 int 139 iommu_print(args, iommu) 140 void *args; 141 const char *iommu; 142 { 143 struct iommu_attach_args *ia = args; 144 145 if (iommu) 146 printf("%s at %s", ia->iom_name, iommu); 147 return (UNCONF); 148 } 149 150 int 151 iommu_match(parent, cf, aux) 152 struct device *parent; 153 struct cfdata *cf; 154 void *aux; 155 { 156 struct mainbus_attach_args *ma = aux; 157 158 if (CPU_ISSUN4OR4C) 159 return (0); 160 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 161 } 162 163 /* 164 * Attach the iommu. 165 */ 166 void 167 iommu_attach(parent, self, aux) 168 struct device *parent; 169 struct device *self; 170 void *aux; 171 { 172 #if defined(SUN4M) 173 struct iommu_softc *sc = (struct iommu_softc *)self; 174 struct mainbus_attach_args *ma = aux; 175 int node; 176 struct bootpath *bp; 177 bus_space_handle_t bh; 178 u_int pbase, pa; 179 int i, mmupcrsave, s; 180 iopte_t *tpte_p; 181 extern u_int *kernel_iopte_table; 182 extern u_int kernel_iopte_table_pa; 183 184 /*XXX-GCC!*/mmupcrsave=0; 185 iommu_sc = sc; 186 /* 187 * XXX there is only one iommu, for now -- do not know how to 188 * address children on others 189 */ 190 if (sc->sc_dev.dv_unit > 0) { 191 printf(" unsupported\n"); 192 return; 193 } 194 node = ma->ma_node; 195 196 #if 0 197 if (ra->ra_vaddr) 198 sc->sc_reg = (struct iommureg *)ca->ca_ra.ra_vaddr; 199 #else 200 /* 201 * Map registers into our space. The PROM may have done this 202 * already, but I feel better if we have our own copy. Plus, the 203 * prom doesn't map the entire register set 204 * 205 * XXX struct iommureg is bigger than ra->ra_len; what are the 206 * other fields for? 207 */ 208 if (bus_space_map2( 209 ma->ma_bustag, 210 ma->ma_iospace, 211 ma->ma_paddr, 212 sizeof(struct iommureg), 213 0, 214 0, 215 &bh) != 0) { 216 printf("iommu_attach: cannot map registers\n"); 217 return; 218 } 219 sc->sc_reg = (struct iommureg *)bh; 220 #endif 221 222 sc->sc_hasiocache = node_has_property(node, "cache-coherence?"); 223 if (CACHEINFO.c_enabled == 0) /* XXX - is this correct? */ 224 sc->sc_hasiocache = 0; 225 has_iocache = sc->sc_hasiocache; /* Set global flag */ 226 227 sc->sc_pagesize = getpropint(node, "page-size", NBPG), 228 sc->sc_range = (1 << 24) << 229 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 230 #if 0 231 sc->sc_dvmabase = (0 - sc->sc_range); 232 #endif 233 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 234 (14 - IOMMU_BAR_IBASHFT); 235 236 /* 237 * Now we build our own copy of the IOMMU page tables. We need to 238 * do this since we're going to change the range to give us 64M of 239 * mappings, and thus we can move DVMA space down to 0xfd000000 to 240 * give us lots of space and to avoid bumping into the PROM, etc. 241 * 242 * XXX Note that this is rather messy. 243 */ 244 sc->sc_ptes = (iopte_t *) kernel_iopte_table; 245 246 /* 247 * Now discache the page tables so that the IOMMU sees our 248 * changes. 249 */ 250 kvm_uncache((caddr_t)sc->sc_ptes, 251 (((0 - IOMMU_DVMA_BASE)/sc->sc_pagesize) * sizeof(iopte_t)) / NBPG); 252 253 /* 254 * Ok. We've got to read in the original table using MMU bypass, 255 * and copy all of its entries to the appropriate place in our 256 * new table, even if the sizes are different. 257 * This is pretty easy since we know DVMA ends at 0xffffffff. 258 * 259 * XXX: PGOFSET, NBPG assume same page size as SRMMU 260 */ 261 if (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc) { 262 /* set MMU AC bit */ 263 sta(SRMMU_PCR, ASI_SRMMU, 264 ((mmupcrsave = lda(SRMMU_PCR, ASI_SRMMU)) | VIKING_PCR_AC)); 265 } 266 267 for (tpte_p = &sc->sc_ptes[((0 - IOMMU_DVMA_BASE)/NBPG) - 1], 268 pa = (u_int)pbase - sizeof(iopte_t) + 269 ((u_int)sc->sc_range/NBPG)*sizeof(iopte_t); 270 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 271 tpte_p--, pa -= sizeof(iopte_t)) { 272 273 IOMMU_FLUSHPAGE(sc, 274 (tpte_p - &sc->sc_ptes[0])*NBPG + IOMMU_DVMA_BASE); 275 *tpte_p = lda(pa, ASI_BYPASS); 276 } 277 if (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc) { 278 /* restore mmu after bug-avoidance */ 279 sta(SRMMU_PCR, ASI_SRMMU, mmupcrsave); 280 } 281 282 /* 283 * Now we can install our new pagetable into the IOMMU 284 */ 285 sc->sc_range = 0 - IOMMU_DVMA_BASE; 286 sc->sc_dvmabase = IOMMU_DVMA_BASE; 287 288 /* calculate log2(sc->sc_range/16MB) */ 289 i = ffs(sc->sc_range/(1 << 24)) - 1; 290 if ((1 << i) != (sc->sc_range/(1 << 24))) 291 panic("bad iommu range: %d\n",i); 292 293 s = splhigh(); 294 IOMMU_FLUSHALL(sc); 295 296 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 297 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 298 sc->sc_reg->io_bar = (kernel_iopte_table_pa >> 4) & IOMMU_BAR_IBA; 299 300 IOMMU_FLUSHALL(sc); 301 splx(s); 302 303 printf(": version 0x%x/0x%x, page-size %d, range %dMB\n", 304 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 305 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 306 sc->sc_pagesize, 307 sc->sc_range >> 20); 308 309 /* Propagate bootpath */ 310 if (ma->ma_bp != NULL && strcmp(ma->ma_bp->name, "iommu") == 0) 311 bp = ma->ma_bp + 1; 312 else 313 bp = NULL; 314 315 iommu_dvmamap = extent_create("iommudvma", 316 IOMMU_DVMA_BASE, IOMMU_DVMA_END, 317 M_DEVBUF, 0, 0, EX_NOWAIT); 318 if (iommu_dvmamap == NULL) 319 panic("iommu: unable to allocate DVMA map"); 320 321 /* 322 * Loop through ROM children (expect Sbus among them). 323 */ 324 for (node = firstchild(node); node; node = nextsibling(node)) { 325 struct iommu_attach_args ia; 326 327 bzero(&ia, sizeof ia); 328 ia.iom_name = getpropstring(node, "name"); 329 330 /* Propagate BUS & DMA tags */ 331 ia.iom_bustag = ma->ma_bustag; 332 ia.iom_dmatag = &iommu_dma_tag; 333 334 ia.iom_node = node; 335 ia.iom_bp = bp; 336 337 ia.iom_reg = NULL; 338 getprop(node, "reg", sizeof(struct sbus_reg), 339 &ia.iom_nreg, (void **)&ia.iom_reg); 340 341 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 342 if (ia.iom_reg != NULL) 343 free(ia.iom_reg, M_DEVBUF); 344 } 345 #endif 346 } 347 348 void 349 iommu_enter(va, pa) 350 bus_addr_t va; 351 paddr_t pa; 352 { 353 struct iommu_softc *sc = iommu_sc; 354 int pte; 355 356 #ifdef DEBUG 357 if (va < sc->sc_dvmabase) 358 panic("iommu_enter: va 0x%lx not in DVMA space", (long)va); 359 #endif 360 361 pte = atop(pa) << IOPTE_PPNSHFT; 362 pte &= IOPTE_PPN; 363 pte |= IOPTE_V | IOPTE_W | (has_iocache ? IOPTE_C : 0); 364 sc->sc_ptes[atop(va - sc->sc_dvmabase)] = pte; 365 IOMMU_FLUSHPAGE(sc, va); 366 } 367 368 /* 369 * iommu_clear: clears mappings created by iommu_enter 370 */ 371 void 372 iommu_remove(va, len) 373 bus_addr_t va; 374 bus_size_t len; 375 { 376 struct iommu_softc *sc = iommu_sc; 377 u_int pagesz = sc->sc_pagesize; 378 bus_addr_t base = sc->sc_dvmabase; 379 380 #ifdef DEBUG 381 if (va < base) 382 panic("iommu_enter: va 0x%lx not in DVMA space", (long)va); 383 #endif 384 385 while ((long)len > 0) { 386 #ifdef notyet 387 #ifdef DEBUG 388 if ((sc->sc_ptes[atop(va - base)] & IOPTE_V) == 0) 389 panic("iommu_clear: clearing invalid pte at va 0x%lx", 390 (long)va); 391 #endif 392 #endif 393 sc->sc_ptes[atop(va - base)] = 0; 394 IOMMU_FLUSHPAGE(sc, va); 395 len -= pagesz; 396 va += pagesz; 397 } 398 } 399 400 #if 0 /* These registers aren't there??? */ 401 void 402 iommu_error() 403 { 404 struct iommu_softc *sc = X; 405 struct iommureg *iop = sc->sc_reg; 406 407 printf("iommu: afsr 0x%x, afar 0x%x\n", iop->io_afsr, iop->io_afar); 408 printf("iommu: mfsr 0x%x, mfar 0x%x\n", iop->io_mfsr, iop->io_mfar); 409 } 410 int 411 iommu_alloc(va, len) 412 u_int va, len; 413 { 414 struct iommu_softc *sc = X; 415 int off, tva, iovaddr, pte; 416 paddr_t pa; 417 418 off = (int)va & PGOFSET; 419 len = round_page(len + off); 420 va -= off; 421 422 if ((int)sc->sc_dvmacur + len > 0) 423 sc->sc_dvmacur = sc->sc_dvmabase; 424 425 iovaddr = tva = sc->sc_dvmacur; 426 sc->sc_dvmacur += len; 427 while (len) { 428 (void) pmap_extract(pmap_kernel(), va, &pa); 429 430 #define IOMMU_PPNSHIFT 8 431 #define IOMMU_V 0x00000002 432 #define IOMMU_W 0x00000004 433 434 pte = atop(pa) << IOMMU_PPNSHIFT; 435 pte |= IOMMU_V | IOMMU_W; 436 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 437 sc->sc_reg->io_flushpage = tva; 438 len -= NBPG; 439 va += NBPG; 440 tva += NBPG; 441 } 442 return iovaddr + off; 443 } 444 #endif 445 446 447 /* 448 * IOMMU DMA map functions. 449 */ 450 int 451 iommu_dmamap_load(t, map, buf, buflen, p, flags) 452 bus_dma_tag_t t; 453 bus_dmamap_t map; 454 void *buf; 455 bus_size_t buflen; 456 struct proc *p; 457 int flags; 458 { 459 bus_size_t sgsize; 460 bus_addr_t dva; 461 bus_addr_t boundary; 462 vaddr_t va = (vaddr_t)buf; 463 u_long align, voff; 464 pmap_t pmap; 465 int s, error; 466 467 /* 468 * Remember page offset, then truncate the buffer address to 469 * a page boundary. 470 */ 471 voff = va & PGOFSET; 472 va &= ~PGOFSET; 473 474 /* 475 * Make sure that on error condition we return "no valid mappings". 476 */ 477 map->dm_nsegs = 0; 478 479 if (buflen > map->_dm_size) 480 return (EINVAL); 481 482 sgsize = (buflen + voff + PGOFSET) & ~PGOFSET; 483 align = dvma_cachealign ? dvma_cachealign : NBPG; 484 boundary = map->_dm_boundary; 485 486 s = splhigh(); 487 error = extent_alloc1(iommu_dvmamap, sgsize, align, va & (align-1), 488 boundary, EX_NOWAIT, (u_long *)&dva); 489 splx(s); 490 491 if (error != 0) 492 return (error); 493 494 cpuinfo.cache_flush(buf, buflen); 495 496 /* 497 * We always use just one segment. 498 */ 499 map->dm_mapsize = buflen; 500 map->dm_nsegs = 1; 501 map->dm_segs[0].ds_addr = dva + voff; 502 map->dm_segs[0].ds_len = buflen; 503 504 if (p != NULL) 505 pmap = p->p_vmspace->vm_map.pmap; 506 else 507 pmap = pmap_kernel(); 508 509 for (; sgsize != 0; ) { 510 paddr_t pa; 511 /* 512 * Get the physical address for this page. 513 */ 514 (void) pmap_extract(pmap, va, &pa); 515 516 iommu_enter(dva, pa); 517 518 dva += NBPG; 519 va += NBPG; 520 sgsize -= NBPG; 521 } 522 523 return (0); 524 } 525 526 /* 527 * Like _bus_dmamap_load(), but for mbufs. 528 */ 529 int 530 iommu_dmamap_load_mbuf(t, map, m, flags) 531 bus_dma_tag_t t; 532 bus_dmamap_t map; 533 struct mbuf *m; 534 int flags; 535 { 536 537 panic("_bus_dmamap_load: not implemented"); 538 } 539 540 /* 541 * Like _bus_dmamap_load(), but for uios. 542 */ 543 int 544 iommu_dmamap_load_uio(t, map, uio, flags) 545 bus_dma_tag_t t; 546 bus_dmamap_t map; 547 struct uio *uio; 548 int flags; 549 { 550 551 panic("_bus_dmamap_load_uio: not implemented"); 552 } 553 554 /* 555 * Like _bus_dmamap_load(), but for raw memory allocated with 556 * bus_dmamem_alloc(). 557 */ 558 int 559 iommu_dmamap_load_raw(t, map, segs, nsegs, size, flags) 560 bus_dma_tag_t t; 561 bus_dmamap_t map; 562 bus_dma_segment_t *segs; 563 int nsegs; 564 bus_size_t size; 565 int flags; 566 { 567 568 panic("_bus_dmamap_load_raw: not implemented"); 569 } 570 571 /* 572 * Common function for unloading a DMA map. May be called by 573 * bus-specific DMA map unload functions. 574 */ 575 void 576 iommu_dmamap_unload(t, map) 577 bus_dma_tag_t t; 578 bus_dmamap_t map; 579 { 580 bus_addr_t addr; 581 bus_size_t len; 582 int s, error; 583 584 if (map->dm_nsegs != 1) 585 panic("_bus_dmamap_unload: nsegs = %d", map->dm_nsegs); 586 587 addr = map->dm_segs[0].ds_addr; 588 len = map->dm_segs[0].ds_len; 589 len = ((addr & PGOFSET) + len + PGOFSET) & ~PGOFSET; 590 addr &= ~PGOFSET; 591 592 iommu_remove(addr, len); 593 s = splhigh(); 594 error = extent_free(iommu_dvmamap, addr, len, EX_NOWAIT); 595 splx(s); 596 if (error != 0) 597 printf("warning: %ld of DVMA space lost\n", (long)len); 598 599 /* Mark the mappings as invalid. */ 600 map->dm_mapsize = 0; 601 map->dm_nsegs = 0; 602 } 603 604 /* 605 * Common function for DMA map synchronization. May be called 606 * by bus-specific DMA map synchronization functions. 607 */ 608 void 609 iommu_dmamap_sync(t, map, offset, len, ops) 610 bus_dma_tag_t t; 611 bus_dmamap_t map; 612 bus_addr_t offset; 613 bus_size_t len; 614 int ops; 615 { 616 617 /* 618 * XXX Should flush CPU write buffers. 619 */ 620 } 621 622 /* 623 * Common function for DMA-safe memory allocation. May be called 624 * by bus-specific DMA memory allocation functions. 625 */ 626 int 627 iommu_dmamem_alloc(t, size, alignment, boundary, segs, nsegs, rsegs, flags) 628 bus_dma_tag_t t; 629 bus_size_t size, alignment, boundary; 630 bus_dma_segment_t *segs; 631 int nsegs; 632 int *rsegs; 633 int flags; 634 { 635 paddr_t pa; 636 bus_addr_t dva; 637 vm_page_t m; 638 int s, error; 639 struct pglist *mlist; 640 641 size = round_page(size); 642 error = _bus_dmamem_alloc_common(t, size, alignment, boundary, 643 segs, nsegs, rsegs, flags); 644 if (error != 0) 645 return (error); 646 647 s = splhigh(); 648 error = extent_alloc(iommu_dvmamap, size, alignment, boundary, 649 (flags & BUS_DMA_NOWAIT) == 0 650 ? EX_WAITOK : EX_NOWAIT, 651 (u_long *)&dva); 652 splx(s); 653 if (error != 0) 654 return (error); 655 656 /* 657 * Compute the location, size, and number of segments actually 658 * returned by the VM code. 659 */ 660 segs[0].ds_addr = dva; 661 segs[0].ds_len = size; 662 *rsegs = 1; 663 664 mlist = segs[0]._ds_mlist; 665 /* Map memory into DVMA space */ 666 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 667 pa = VM_PAGE_TO_PHYS(m); 668 669 iommu_enter(dva, pa); 670 dva += PAGE_SIZE; 671 } 672 673 return (0); 674 } 675 676 /* 677 * Common function for freeing DMA-safe memory. May be called by 678 * bus-specific DMA memory free functions. 679 */ 680 void 681 iommu_dmamem_free(t, segs, nsegs) 682 bus_dma_tag_t t; 683 bus_dma_segment_t *segs; 684 int nsegs; 685 { 686 bus_addr_t addr; 687 bus_size_t len; 688 int s, error; 689 690 if (nsegs != 1) 691 panic("bus_dmamem_free: nsegs = %d", nsegs); 692 693 addr = segs[0].ds_addr; 694 len = segs[0].ds_len; 695 696 iommu_remove(addr, len); 697 s = splhigh(); 698 error = extent_free(iommu_dvmamap, addr, len, EX_NOWAIT); 699 splx(s); 700 if (error != 0) 701 printf("warning: %ld of DVMA space lost\n", (long)len); 702 /* 703 * Return the list of pages back to the VM system. 704 */ 705 _bus_dmamem_free_common(t, segs, nsegs); 706 } 707 708 /* 709 * Common function for mapping DMA-safe memory. May be called by 710 * bus-specific DMA memory map functions. 711 */ 712 int 713 iommu_dmamem_map(t, segs, nsegs, size, kvap, flags) 714 bus_dma_tag_t t; 715 bus_dma_segment_t *segs; 716 int nsegs; 717 size_t size; 718 caddr_t *kvap; 719 int flags; 720 { 721 vm_page_t m; 722 vaddr_t va, sva; 723 bus_addr_t addr; 724 struct pglist *mlist; 725 int cbit; 726 size_t oversize; 727 u_long align; 728 729 if (nsegs != 1) 730 panic("iommu_dmamem_map: nsegs = %d", nsegs); 731 732 cbit = has_iocache ? 0 : PMAP_NC; 733 align = dvma_cachealign ? dvma_cachealign : PAGE_SIZE; 734 735 size = round_page(size); 736 737 /* 738 * Find a region of kernel virtual addresses that can accomodate 739 * our aligment requirements. 740 */ 741 oversize = size + align - PAGE_SIZE; 742 sva = uvm_km_valloc(kernel_map, oversize); 743 if (sva == 0) 744 return (ENOMEM); 745 746 /* Compute start of aligned region */ 747 va = sva; 748 va += ((segs[0].ds_addr & (align - 1)) + align - va) & (align - 1); 749 750 /* Return excess virtual addresses */ 751 if (va != sva) 752 (void)uvm_unmap(kernel_map, sva, va); 753 if (va + size != sva + oversize) 754 (void)uvm_unmap(kernel_map, va + size, sva + oversize); 755 756 757 *kvap = (caddr_t)va; 758 mlist = segs[0]._ds_mlist; 759 760 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 761 762 if (size == 0) 763 panic("iommu_dmamem_map: size botch"); 764 765 addr = VM_PAGE_TO_PHYS(m); 766 pmap_enter(pmap_kernel(), va, addr | cbit, 767 VM_PROT_READ | VM_PROT_WRITE, TRUE, 768 VM_PROT_READ | VM_PROT_WRITE); 769 #if 0 770 if (flags & BUS_DMA_COHERENT) 771 /* XXX */; 772 #endif 773 va += PAGE_SIZE; 774 size -= PAGE_SIZE; 775 } 776 777 return (0); 778 } 779 780 /* 781 * Common functin for mmap(2)'ing DMA-safe memory. May be called by 782 * bus-specific DMA mmap(2)'ing functions. 783 */ 784 int 785 iommu_dmamem_mmap(t, segs, nsegs, off, prot, flags) 786 bus_dma_tag_t t; 787 bus_dma_segment_t *segs; 788 int nsegs, off, prot, flags; 789 { 790 791 panic("_bus_dmamem_mmap: not implemented"); 792 } 793
Indexes created Tue Sep 30 20:09:53 GMT 2025