iommu.c revision 1.44
1 /* $NetBSD: iommu.c,v 1.44 2000/05/30 03:26:34 cjs Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/malloc.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <vm/vm.h> 46 #include <vm/vm_kern.h> 47 48 #include <uvm/uvm_extern.h> 49 #include <uvm/uvm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <machine/autoconf.h> 54 #include <machine/ctlreg.h> 55 #include <sparc/sparc/asm.h> 56 #include <sparc/sparc/vaddrs.h> 57 #include <sparc/sparc/cpuvar.h> 58 #include <sparc/sparc/iommureg.h> 59 #include <sparc/sparc/iommuvar.h> 60 61 struct iommu_softc { 62 struct device sc_dev; /* base device */ 63 struct iommureg *sc_reg; 64 u_int sc_pagesize; 65 u_int sc_range; 66 bus_addr_t sc_dvmabase; 67 iopte_t *sc_ptes; 68 int sc_hasiocache; 69 }; 70 struct iommu_softc *iommu_sc;/*XXX*/ 71 int has_iocache; 72 u_long dvma_cachealign; 73 74 /* 75 * Note: operations on the extent map are being protected with 76 * splhigh(), since we cannot predict at which interrupt priority 77 * our clients will run. 78 */ 79 struct extent *iommu_dvmamap; 80 81 82 /* autoconfiguration driver */ 83 int iommu_print __P((void *, const char *)); 84 void iommu_attach __P((struct device *, struct device *, void *)); 85 int iommu_match __P((struct device *, struct cfdata *, void *)); 86 87 static void iommu_copy_prom_entries __P((struct iommu_softc *)); 88 89 struct cfattach iommu_ca = { 90 sizeof(struct iommu_softc), iommu_match, iommu_attach 91 }; 92 93 /* IOMMU DMA map functions */ 94 int iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 95 bus_size_t, struct proc *, int)); 96 int iommu_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, 97 struct mbuf *, int)); 98 int iommu_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, 99 struct uio *, int)); 100 int iommu_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 101 bus_dma_segment_t *, int, bus_size_t, int)); 102 void iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 103 void iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 104 bus_size_t, int)); 105 106 int iommu_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 107 int nsegs, size_t size, caddr_t *kvap, int flags)); 108 int iommu_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 109 int nsegs, int off, int prot, int flags)); 110 int iommu_dvma_alloc(bus_dmamap_t, vaddr_t, bus_size_t, int, 111 bus_addr_t *, bus_size_t *); 112 113 114 struct sparc_bus_dma_tag iommu_dma_tag = { 115 NULL, 116 _bus_dmamap_create, 117 _bus_dmamap_destroy, 118 iommu_dmamap_load, 119 iommu_dmamap_load_mbuf, 120 iommu_dmamap_load_uio, 121 iommu_dmamap_load_raw, 122 iommu_dmamap_unload, 123 iommu_dmamap_sync, 124 125 _bus_dmamem_alloc, 126 _bus_dmamem_free, 127 iommu_dmamem_map, 128 _bus_dmamem_unmap, 129 iommu_dmamem_mmap 130 }; 131 /* 132 * Print the location of some iommu-attached device (called just 133 * before attaching that device). If `iommu' is not NULL, the 134 * device was found but not configured; print the iommu as well. 135 * Return UNCONF (config_find ignores this if the device was configured). 136 */ 137 int 138 iommu_print(args, iommu) 139 void *args; 140 const char *iommu; 141 { 142 struct iommu_attach_args *ia = args; 143 144 if (iommu) 145 printf("%s at %s", ia->iom_name, iommu); 146 return (UNCONF); 147 } 148 149 int 150 iommu_match(parent, cf, aux) 151 struct device *parent; 152 struct cfdata *cf; 153 void *aux; 154 { 155 struct mainbus_attach_args *ma = aux; 156 157 if (CPU_ISSUN4OR4C) 158 return (0); 159 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 160 } 161 162 /* 163 * Attach the iommu. 164 */ 165 void 166 iommu_attach(parent, self, aux) 167 struct device *parent; 168 struct device *self; 169 void *aux; 170 { 171 #if defined(SUN4M) 172 struct iommu_softc *sc = (struct iommu_softc *)self; 173 struct mainbus_attach_args *ma = aux; 174 bus_space_handle_t bh; 175 int node; 176 int i, s; 177 u_int iopte_table_pa; 178 struct pglist mlist; 179 u_int size; 180 vm_page_t m; 181 vaddr_t va; 182 183 iommu_sc = sc; 184 /* 185 * XXX there is only one iommu, for now -- do not know how to 186 * address children on others 187 */ 188 if (sc->sc_dev.dv_unit > 0) { 189 printf(" unsupported\n"); 190 return; 191 } 192 node = ma->ma_node; 193 194 /* 195 * Map registers into our space. The PROM may have done this 196 * already, but I feel better if we have our own copy. Plus, the 197 * prom doesn't map the entire register set. 198 * 199 * XXX struct iommureg is bigger than ra->ra_len; what are the 200 * other fields for? 201 */ 202 if (bus_space_map2( 203 ma->ma_bustag, 204 ma->ma_iospace, 205 ma->ma_paddr, 206 sizeof(struct iommureg), 207 0, 208 0, 209 &bh) != 0) { 210 printf("iommu_attach: cannot map registers\n"); 211 return; 212 } 213 sc->sc_reg = (struct iommureg *)bh; 214 215 sc->sc_hasiocache = node_has_property(node, "cache-coherence?"); 216 if (CACHEINFO.c_enabled == 0) /* XXX - is this correct? */ 217 sc->sc_hasiocache = 0; 218 has_iocache = sc->sc_hasiocache; /* Set global flag */ 219 220 sc->sc_pagesize = getpropint(node, "page-size", NBPG), 221 222 /* 223 * Allocate memory for I/O pagetables. 224 * This takes 64K of contiguous physical memory to map 64M of 225 * DVMA space (starting at IOMMU_DVMA_BASE). 226 * The table must be aligned on a (-IOMMU_DVMA_BASE/pagesize) 227 * boundary (i.e. 64K for 64M of DVMA space). 228 */ 229 230 size = ((0 - IOMMU_DVMA_BASE) / sc->sc_pagesize) * sizeof(iopte_t); 231 TAILQ_INIT(&mlist); 232 if (uvm_pglistalloc(size, vm_first_phys, vm_first_phys+vm_num_phys, 233 size, 0, &mlist, 1, 0) != 0) 234 panic("iommu_attach: no memory"); 235 236 va = uvm_km_valloc(kernel_map, size); 237 if (va == 0) 238 panic("iommu_attach: no memory"); 239 240 sc->sc_ptes = (iopte_t *)va; 241 242 m = TAILQ_FIRST(&mlist); 243 iopte_table_pa = VM_PAGE_TO_PHYS(m); 244 245 /* Map the pages */ 246 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 247 paddr_t pa = VM_PAGE_TO_PHYS(m); 248 pmap_enter(pmap_kernel(), va, pa | PMAP_NC, 249 VM_PROT_READ|VM_PROT_WRITE, 250 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 251 va += NBPG; 252 } 253 254 /* 255 * Copy entries from current IOMMU table. 256 * XXX - Why do we need to do this? 257 */ 258 iommu_copy_prom_entries(sc); 259 260 /* 261 * Now we can install our new pagetable into the IOMMU 262 */ 263 sc->sc_range = 0 - IOMMU_DVMA_BASE; 264 sc->sc_dvmabase = IOMMU_DVMA_BASE; 265 266 /* calculate log2(sc->sc_range/16MB) */ 267 i = ffs(sc->sc_range/(1 << 24)) - 1; 268 if ((1 << i) != (sc->sc_range/(1 << 24))) 269 panic("iommu: bad range: %d\n", i); 270 271 s = splhigh(); 272 IOMMU_FLUSHALL(sc); 273 274 /* Load range and physical address of PTEs */ 275 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 276 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 277 sc->sc_reg->io_bar = (iopte_table_pa >> 4) & IOMMU_BAR_IBA; 278 279 IOMMU_FLUSHALL(sc); 280 splx(s); 281 282 printf(": version 0x%x/0x%x, page-size %d, range %dMB\n", 283 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 284 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 285 sc->sc_pagesize, 286 sc->sc_range >> 20); 287 288 iommu_dvmamap = extent_create("iommudvma", 289 IOMMU_DVMA_BASE, IOMMU_DVMA_END, 290 M_DEVBUF, 0, 0, EX_NOWAIT); 291 if (iommu_dvmamap == NULL) 292 panic("iommu: unable to allocate DVMA map"); 293 294 /* 295 * Loop through ROM children (expect Sbus among them). 296 */ 297 for (node = firstchild(node); node; node = nextsibling(node)) { 298 struct iommu_attach_args ia; 299 300 bzero(&ia, sizeof ia); 301 ia.iom_name = getpropstring(node, "name"); 302 303 /* Propagate BUS & DMA tags */ 304 ia.iom_bustag = ma->ma_bustag; 305 ia.iom_dmatag = &iommu_dma_tag; 306 307 ia.iom_node = node; 308 309 ia.iom_reg = NULL; 310 getprop(node, "reg", sizeof(struct sbus_reg), 311 &ia.iom_nreg, (void **)&ia.iom_reg); 312 313 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 314 if (ia.iom_reg != NULL) 315 free(ia.iom_reg, M_DEVBUF); 316 } 317 #endif 318 } 319 320 static void 321 iommu_copy_prom_entries(sc) 322 struct iommu_softc *sc; 323 { 324 u_int pbase, pa; 325 u_int range; 326 iopte_t *tpte_p; 327 u_int pagesz = sc->sc_pagesize; 328 int use_ac = (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc); 329 u_int mmupcr_save; 330 331 /* 332 * We read in the original table using MMU bypass and copy all 333 * of its entries to the appropriate place in our new table, 334 * even if the sizes are different. 335 * This is pretty easy since we know DVMA ends at 0xffffffff. 336 */ 337 338 range = (1 << 24) << 339 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 340 341 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 342 (14 - IOMMU_BAR_IBASHFT); 343 344 if (use_ac) { 345 /* 346 * Set MMU AC bit so we'll still read from the cache 347 * in by-pass mode. 348 */ 349 mmupcr_save = lda(SRMMU_PCR, ASI_SRMMU); 350 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save | VIKING_PCR_AC); 351 } else 352 mmupcr_save = 0; /* XXX - avoid GCC `unintialized' warning */ 353 354 /* Flush entire IOMMU TLB before messing with the in-memory tables */ 355 IOMMU_FLUSHALL(sc); 356 357 /* 358 * tpte_p = top of our PTE table 359 * pa = top of current PTE table 360 * Then work downwards and copy entries until we hit the bottom 361 * of either table. 362 */ 363 for (tpte_p = &sc->sc_ptes[((0 - IOMMU_DVMA_BASE)/pagesz) - 1], 364 pa = (u_int)pbase + (range/pagesz - 1)*sizeof(iopte_t); 365 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 366 tpte_p--, pa -= sizeof(iopte_t)) { 367 368 *tpte_p = lda(pa, ASI_BYPASS); 369 } 370 371 if (use_ac) { 372 /* restore mmu after bug-avoidance */ 373 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save); 374 } 375 } 376 377 void 378 iommu_enter(dva, pa) 379 bus_addr_t dva; 380 paddr_t pa; 381 { 382 struct iommu_softc *sc = iommu_sc; 383 int pte; 384 385 /* This routine relies on the fact that sc->sc_pagesize == PAGE_SIZE */ 386 387 #ifdef DIAGNOSTIC 388 if (dva < sc->sc_dvmabase) 389 panic("iommu_enter: dva 0x%lx not in DVMA space", (long)dva); 390 #endif 391 392 pte = atop(pa) << IOPTE_PPNSHFT; 393 pte &= IOPTE_PPN; 394 pte |= IOPTE_V | IOPTE_W | (has_iocache ? IOPTE_C : 0); 395 sc->sc_ptes[atop(dva - sc->sc_dvmabase)] = pte; 396 IOMMU_FLUSHPAGE(sc, dva); 397 } 398 399 /* 400 * iommu_clear: clears mappings created by iommu_enter 401 */ 402 void 403 iommu_remove(dva, len) 404 bus_addr_t dva; 405 bus_size_t len; 406 { 407 struct iommu_softc *sc = iommu_sc; 408 u_int pagesz = sc->sc_pagesize; 409 bus_addr_t base = sc->sc_dvmabase; 410 411 #ifdef DEBUG 412 if (dva < base) 413 panic("iommu_remove: va 0x%lx not in DVMA space", (long)dva); 414 #endif 415 416 while ((long)len > 0) { 417 #ifdef notyet 418 #ifdef DEBUG 419 if ((sc->sc_ptes[atop(dva - base)] & IOPTE_V) == 0) 420 panic("iommu_remove: clearing invalid pte at dva 0x%lx", 421 (long)dva); 422 #endif 423 #endif 424 sc->sc_ptes[atop(dva - base)] = 0; 425 IOMMU_FLUSHPAGE(sc, dva); 426 len -= pagesz; 427 dva += pagesz; 428 } 429 } 430 431 #if 0 /* These registers aren't there??? */ 432 void 433 iommu_error() 434 { 435 struct iommu_softc *sc = X; 436 struct iommureg *iop = sc->sc_reg; 437 438 printf("iommu: afsr 0x%x, afar 0x%x\n", iop->io_afsr, iop->io_afar); 439 printf("iommu: mfsr 0x%x, mfar 0x%x\n", iop->io_mfsr, iop->io_mfar); 440 } 441 int 442 iommu_alloc(va, len) 443 u_int va, len; 444 { 445 struct iommu_softc *sc = X; 446 int off, tva, iovaddr, pte; 447 paddr_t pa; 448 449 off = (int)va & PGOFSET; 450 len = round_page(len + off); 451 va -= off; 452 453 if ((int)sc->sc_dvmacur + len > 0) 454 sc->sc_dvmacur = sc->sc_dvmabase; 455 456 iovaddr = tva = sc->sc_dvmacur; 457 sc->sc_dvmacur += len; 458 while (len) { 459 (void) pmap_extract(pmap_kernel(), va, &pa); 460 461 #define IOMMU_PPNSHIFT 8 462 #define IOMMU_V 0x00000002 463 #define IOMMU_W 0x00000004 464 465 pte = atop(pa) << IOMMU_PPNSHIFT; 466 pte |= IOMMU_V | IOMMU_W; 467 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 468 sc->sc_reg->io_flushpage = tva; 469 len -= NBPG; 470 va += NBPG; 471 tva += NBPG; 472 } 473 return iovaddr + off; 474 } 475 #endif 476 477 478 /* 479 * Internal routine to allocate space in the IOMMU map. 480 */ 481 int 482 iommu_dvma_alloc(map, va, len, flags, dvap, sgsizep) 483 bus_dmamap_t map; 484 vaddr_t va; 485 bus_size_t len; 486 int flags; 487 bus_addr_t *dvap; 488 bus_size_t *sgsizep; 489 { 490 bus_size_t sgsize; 491 u_long align, voff; 492 u_long ex_start, ex_end; 493 int s, error; 494 int pagesz = PAGE_SIZE; 495 496 /* 497 * Remember page offset, then truncate the buffer address to 498 * a page boundary. 499 */ 500 voff = va & (pagesz - 1); 501 va &= -pagesz; 502 503 if (len > map->_dm_size) 504 return (EINVAL); 505 506 sgsize = (len + voff + pagesz - 1) & -pagesz; 507 align = dvma_cachealign ? dvma_cachealign : pagesz; 508 509 s = splhigh(); 510 511 /* Check `24 address bits' in the map's attributes */ 512 if ((map->_dm_flags & BUS_DMA_24BIT) != 0) { 513 ex_start = D24_DVMA_BASE; 514 ex_end = D24_DVMA_END; 515 } else { 516 ex_start = iommu_dvmamap->ex_start; 517 ex_end = iommu_dvmamap->ex_end; 518 } 519 error = extent_alloc_subregion1(iommu_dvmamap, 520 ex_start, ex_end, 521 sgsize, align, va & (align-1), 522 map->_dm_boundary, 523 (flags & BUS_DMA_NOWAIT) == 0 524 ? EX_WAITOK : EX_NOWAIT, 525 (u_long *)dvap); 526 splx(s); 527 528 *sgsizep = sgsize; 529 return (error); 530 } 531 532 /* 533 * IOMMU DMA map functions. 534 */ 535 int 536 iommu_dmamap_load(t, map, buf, buflen, p, flags) 537 bus_dma_tag_t t; 538 bus_dmamap_t map; 539 void *buf; 540 bus_size_t buflen; 541 struct proc *p; 542 int flags; 543 { 544 bus_size_t sgsize; 545 bus_addr_t dva; 546 vaddr_t va = (vaddr_t)buf; 547 int pagesz = PAGE_SIZE; 548 pmap_t pmap; 549 int error; 550 551 /* 552 * Make sure that on error condition we return "no valid mappings". 553 */ 554 map->dm_nsegs = 0; 555 556 /* Allocate IOMMU resources */ 557 if ((error = iommu_dvma_alloc(map, va, buflen, flags, 558 &dva, &sgsize)) != 0) 559 return (error); 560 561 cpuinfo.cache_flush(buf, buflen); /* XXX - move to bus_dma_sync? */ 562 563 /* 564 * We always use just one segment. 565 */ 566 map->dm_mapsize = buflen; 567 map->dm_nsegs = 1; 568 map->dm_segs[0].ds_addr = dva + (va & (pagesz - 1)); 569 map->dm_segs[0].ds_len = buflen; 570 map->dm_segs[0]._ds_sgsize = sgsize; 571 572 if (p != NULL) 573 pmap = p->p_vmspace->vm_map.pmap; 574 else 575 pmap = pmap_kernel(); 576 577 for (; sgsize != 0; ) { 578 paddr_t pa; 579 /* 580 * Get the physical address for this page. 581 */ 582 (void) pmap_extract(pmap, va, &pa); 583 584 iommu_enter(dva, pa); 585 586 dva += pagesz; 587 va += pagesz; 588 sgsize -= pagesz; 589 } 590 591 return (0); 592 } 593 594 /* 595 * Like _bus_dmamap_load(), but for mbufs. 596 */ 597 int 598 iommu_dmamap_load_mbuf(t, map, m, flags) 599 bus_dma_tag_t t; 600 bus_dmamap_t map; 601 struct mbuf *m; 602 int flags; 603 { 604 605 panic("_bus_dmamap_load_mbuf: not implemented"); 606 } 607 608 /* 609 * Like _bus_dmamap_load(), but for uios. 610 */ 611 int 612 iommu_dmamap_load_uio(t, map, uio, flags) 613 bus_dma_tag_t t; 614 bus_dmamap_t map; 615 struct uio *uio; 616 int flags; 617 { 618 619 panic("_bus_dmamap_load_uio: not implemented"); 620 } 621 622 /* 623 * Like _bus_dmamap_load(), but for raw memory allocated with 624 * bus_dmamem_alloc(). 625 */ 626 int 627 iommu_dmamap_load_raw(t, map, segs, nsegs, size, flags) 628 bus_dma_tag_t t; 629 bus_dmamap_t map; 630 bus_dma_segment_t *segs; 631 int nsegs; 632 bus_size_t size; 633 int flags; 634 { 635 vm_page_t m; 636 paddr_t pa; 637 bus_addr_t dva; 638 bus_size_t sgsize; 639 struct pglist *mlist; 640 int pagesz = PAGE_SIZE; 641 int error; 642 643 map->dm_nsegs = 0; 644 645 /* Allocate IOMMU resources */ 646 if ((error = iommu_dvma_alloc(map, segs[0]._ds_va, size, 647 flags, &dva, &sgsize)) != 0) 648 return (error); 649 650 /* 651 * Note DVMA address in case bus_dmamem_map() is called later. 652 * It can then insure cache coherency by choosing a KVA that 653 * is aligned to `ds_addr'. 654 */ 655 segs[0].ds_addr = dva; 656 segs[0].ds_len = size; 657 658 map->dm_segs[0].ds_addr = dva; 659 map->dm_segs[0].ds_len = size; 660 map->dm_segs[0]._ds_sgsize = sgsize; 661 662 /* Map physical pages into IOMMU */ 663 mlist = segs[0]._ds_mlist; 664 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 665 if (sgsize == 0) 666 panic("iommu_dmamap_load_raw: size botch"); 667 pa = VM_PAGE_TO_PHYS(m); 668 iommu_enter(dva, pa); 669 dva += pagesz; 670 sgsize -= pagesz; 671 } 672 673 map->dm_nsegs = 1; 674 map->dm_mapsize = size; 675 676 return (0); 677 } 678 679 /* 680 * Unload an IOMMU DMA map. 681 */ 682 void 683 iommu_dmamap_unload(t, map) 684 bus_dma_tag_t t; 685 bus_dmamap_t map; 686 { 687 bus_dma_segment_t *segs = map->dm_segs; 688 int nsegs = map->dm_nsegs; 689 bus_addr_t dva; 690 bus_size_t len; 691 int i, s, error; 692 693 for (i = 0; i < nsegs; i++) { 694 dva = segs[i].ds_addr & -PAGE_SIZE; 695 len = segs[i]._ds_sgsize; 696 697 iommu_remove(dva, len); 698 s = splhigh(); 699 error = extent_free(iommu_dvmamap, dva, len, EX_NOWAIT); 700 splx(s); 701 if (error != 0) 702 printf("warning: %ld of DVMA space lost\n", (long)len); 703 } 704 705 /* Mark the mappings as invalid. */ 706 map->dm_mapsize = 0; 707 map->dm_nsegs = 0; 708 } 709 710 /* 711 * DMA map synchronization. 712 */ 713 void 714 iommu_dmamap_sync(t, map, offset, len, ops) 715 bus_dma_tag_t t; 716 bus_dmamap_t map; 717 bus_addr_t offset; 718 bus_size_t len; 719 int ops; 720 { 721 722 /* 723 * XXX Should flush CPU write buffers. 724 */ 725 } 726 727 /* 728 * Map DMA-safe memory. 729 */ 730 int 731 iommu_dmamem_map(t, segs, nsegs, size, kvap, flags) 732 bus_dma_tag_t t; 733 bus_dma_segment_t *segs; 734 int nsegs; 735 size_t size; 736 caddr_t *kvap; 737 int flags; 738 { 739 vm_page_t m; 740 vaddr_t va; 741 bus_addr_t addr; 742 struct pglist *mlist; 743 int cbit; 744 u_long align; 745 int pagesz = PAGE_SIZE; 746 747 if (nsegs != 1) 748 panic("iommu_dmamem_map: nsegs = %d", nsegs); 749 750 cbit = has_iocache ? 0 : PMAP_NC; 751 align = dvma_cachealign ? dvma_cachealign : pagesz; 752 753 size = round_page(size); 754 755 /* 756 * In case the segment has already been loaded by 757 * iommu_dmamap_load_raw(), find a region of kernel virtual 758 * addresses that can accomodate our aligment requirements. 759 */ 760 va = _bus_dma_valloc_skewed(size, 0, align, 761 segs[0].ds_addr & (align - 1)); 762 if (va == 0) 763 return (ENOMEM); 764 765 segs[0]._ds_va = va; 766 *kvap = (caddr_t)va; 767 768 /* 769 * Map the pages allocated in _bus_dmamem_alloc() to the 770 * kernel virtual address space. 771 */ 772 mlist = segs[0]._ds_mlist; 773 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 774 775 if (size == 0) 776 panic("iommu_dmamem_map: size botch"); 777 778 addr = VM_PAGE_TO_PHYS(m); 779 pmap_enter(pmap_kernel(), va, addr | cbit, 780 VM_PROT_READ | VM_PROT_WRITE, 781 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 782 #if 0 783 if (flags & BUS_DMA_COHERENT) 784 /* XXX */; 785 #endif 786 va += pagesz; 787 size -= pagesz; 788 } 789 790 return (0); 791 } 792 793 /* 794 * mmap(2)'ing DMA-safe memory. 795 */ 796 int 797 iommu_dmamem_mmap(t, segs, nsegs, off, prot, flags) 798 bus_dma_tag_t t; 799 bus_dma_segment_t *segs; 800 int nsegs, off, prot, flags; 801 { 802 803 panic("_bus_dmamem_mmap: not implemented"); 804 } 805
Indexes created Tue Sep 30 20:09:53 GMT 2025