iommu.c revision 1.45
1 /* $NetBSD: iommu.c,v 1.45 2000/06/24 22:47:45 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/malloc.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 #include <vm/vm.h> 46 #include <vm/vm_kern.h> 47 48 #include <uvm/uvm_extern.h> 49 #include <uvm/uvm.h> 50 51 #define _SPARC_BUS_DMA_PRIVATE 52 #include <machine/bus.h> 53 #include <machine/autoconf.h> 54 #include <machine/ctlreg.h> 55 #include <sparc/sparc/asm.h> 56 #include <sparc/sparc/vaddrs.h> 57 #include <sparc/sparc/cpuvar.h> 58 #include <sparc/sparc/iommureg.h> 59 #include <sparc/sparc/iommuvar.h> 60 61 struct iommu_softc { 62 struct device sc_dev; /* base device */ 63 struct iommureg *sc_reg; 64 u_int sc_pagesize; 65 u_int sc_range; 66 bus_addr_t sc_dvmabase; 67 iopte_t *sc_ptes; 68 int sc_hasiocache; 69 }; 70 struct iommu_softc *iommu_sc;/*XXX*/ 71 int has_iocache; 72 u_long dvma_cachealign; 73 74 /* 75 * Note: operations on the extent map are being protected with 76 * splhigh(), since we cannot predict at which interrupt priority 77 * our clients will run. 78 */ 79 struct extent *iommu_dvmamap; 80 81 82 /* autoconfiguration driver */ 83 int iommu_print __P((void *, const char *)); 84 void iommu_attach __P((struct device *, struct device *, void *)); 85 int iommu_match __P((struct device *, struct cfdata *, void *)); 86 87 static void iommu_copy_prom_entries __P((struct iommu_softc *)); 88 89 struct cfattach iommu_ca = { 90 sizeof(struct iommu_softc), iommu_match, iommu_attach 91 }; 92 93 /* IOMMU DMA map functions */ 94 int iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 95 bus_size_t, int, bus_dmamap_t *)); 96 int iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 97 bus_size_t, struct proc *, int)); 98 int iommu_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, 99 struct mbuf *, int)); 100 int iommu_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, 101 struct uio *, int)); 102 int iommu_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 103 bus_dma_segment_t *, int, bus_size_t, int)); 104 void iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 105 void iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 106 bus_size_t, int)); 107 108 int iommu_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 109 int nsegs, size_t size, caddr_t *kvap, int flags)); 110 int iommu_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 111 int nsegs, int off, int prot, int flags)); 112 int iommu_dvma_alloc(bus_dmamap_t, vaddr_t, bus_size_t, int, 113 bus_addr_t *, bus_size_t *); 114 115 116 struct sparc_bus_dma_tag iommu_dma_tag = { 117 NULL, 118 iommu_dmamap_create, 119 _bus_dmamap_destroy, 120 iommu_dmamap_load, 121 iommu_dmamap_load_mbuf, 122 iommu_dmamap_load_uio, 123 iommu_dmamap_load_raw, 124 iommu_dmamap_unload, 125 iommu_dmamap_sync, 126 127 _bus_dmamem_alloc, 128 _bus_dmamem_free, 129 iommu_dmamem_map, 130 _bus_dmamem_unmap, 131 iommu_dmamem_mmap 132 }; 133 /* 134 * Print the location of some iommu-attached device (called just 135 * before attaching that device). If `iommu' is not NULL, the 136 * device was found but not configured; print the iommu as well. 137 * Return UNCONF (config_find ignores this if the device was configured). 138 */ 139 int 140 iommu_print(args, iommu) 141 void *args; 142 const char *iommu; 143 { 144 struct iommu_attach_args *ia = args; 145 146 if (iommu) 147 printf("%s at %s", ia->iom_name, iommu); 148 return (UNCONF); 149 } 150 151 int 152 iommu_match(parent, cf, aux) 153 struct device *parent; 154 struct cfdata *cf; 155 void *aux; 156 { 157 struct mainbus_attach_args *ma = aux; 158 159 if (CPU_ISSUN4OR4C) 160 return (0); 161 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 162 } 163 164 /* 165 * Attach the iommu. 166 */ 167 void 168 iommu_attach(parent, self, aux) 169 struct device *parent; 170 struct device *self; 171 void *aux; 172 { 173 #if defined(SUN4M) 174 struct iommu_softc *sc = (struct iommu_softc *)self; 175 struct mainbus_attach_args *ma = aux; 176 bus_space_handle_t bh; 177 int node; 178 int i, s; 179 u_int iopte_table_pa; 180 struct pglist mlist; 181 u_int size; 182 vm_page_t m; 183 vaddr_t va; 184 185 iommu_sc = sc; 186 /* 187 * XXX there is only one iommu, for now -- do not know how to 188 * address children on others 189 */ 190 if (sc->sc_dev.dv_unit > 0) { 191 printf(" unsupported\n"); 192 return; 193 } 194 node = ma->ma_node; 195 196 /* 197 * Map registers into our space. The PROM may have done this 198 * already, but I feel better if we have our own copy. Plus, the 199 * prom doesn't map the entire register set. 200 * 201 * XXX struct iommureg is bigger than ra->ra_len; what are the 202 * other fields for? 203 */ 204 if (bus_space_map2( 205 ma->ma_bustag, 206 ma->ma_iospace, 207 ma->ma_paddr, 208 sizeof(struct iommureg), 209 0, 210 0, 211 &bh) != 0) { 212 printf("iommu_attach: cannot map registers\n"); 213 return; 214 } 215 sc->sc_reg = (struct iommureg *)bh; 216 217 sc->sc_hasiocache = node_has_property(node, "cache-coherence?"); 218 if (CACHEINFO.c_enabled == 0) /* XXX - is this correct? */ 219 sc->sc_hasiocache = 0; 220 has_iocache = sc->sc_hasiocache; /* Set global flag */ 221 222 sc->sc_pagesize = getpropint(node, "page-size", NBPG), 223 224 /* 225 * Allocate memory for I/O pagetables. 226 * This takes 64K of contiguous physical memory to map 64M of 227 * DVMA space (starting at IOMMU_DVMA_BASE). 228 * The table must be aligned on a (-IOMMU_DVMA_BASE/pagesize) 229 * boundary (i.e. 64K for 64M of DVMA space). 230 */ 231 232 size = ((0 - IOMMU_DVMA_BASE) / sc->sc_pagesize) * sizeof(iopte_t); 233 TAILQ_INIT(&mlist); 234 if (uvm_pglistalloc(size, vm_first_phys, vm_first_phys+vm_num_phys, 235 size, 0, &mlist, 1, 0) != 0) 236 panic("iommu_attach: no memory"); 237 238 va = uvm_km_valloc(kernel_map, size); 239 if (va == 0) 240 panic("iommu_attach: no memory"); 241 242 sc->sc_ptes = (iopte_t *)va; 243 244 m = TAILQ_FIRST(&mlist); 245 iopte_table_pa = VM_PAGE_TO_PHYS(m); 246 247 /* Map the pages */ 248 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 249 paddr_t pa = VM_PAGE_TO_PHYS(m); 250 pmap_enter(pmap_kernel(), va, pa | PMAP_NC, 251 VM_PROT_READ|VM_PROT_WRITE, 252 VM_PROT_READ|VM_PROT_WRITE|PMAP_WIRED); 253 va += NBPG; 254 } 255 256 /* 257 * Copy entries from current IOMMU table. 258 * XXX - Why do we need to do this? 259 */ 260 iommu_copy_prom_entries(sc); 261 262 /* 263 * Now we can install our new pagetable into the IOMMU 264 */ 265 sc->sc_range = 0 - IOMMU_DVMA_BASE; 266 sc->sc_dvmabase = IOMMU_DVMA_BASE; 267 268 /* calculate log2(sc->sc_range/16MB) */ 269 i = ffs(sc->sc_range/(1 << 24)) - 1; 270 if ((1 << i) != (sc->sc_range/(1 << 24))) 271 panic("iommu: bad range: %d\n", i); 272 273 s = splhigh(); 274 IOMMU_FLUSHALL(sc); 275 276 /* Load range and physical address of PTEs */ 277 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 278 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 279 sc->sc_reg->io_bar = (iopte_table_pa >> 4) & IOMMU_BAR_IBA; 280 281 IOMMU_FLUSHALL(sc); 282 splx(s); 283 284 printf(": version 0x%x/0x%x, page-size %d, range %dMB\n", 285 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 286 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 287 sc->sc_pagesize, 288 sc->sc_range >> 20); 289 290 iommu_dvmamap = extent_create("iommudvma", 291 IOMMU_DVMA_BASE, IOMMU_DVMA_END, 292 M_DEVBUF, 0, 0, EX_NOWAIT); 293 if (iommu_dvmamap == NULL) 294 panic("iommu: unable to allocate DVMA map"); 295 296 /* 297 * Loop through ROM children (expect Sbus among them). 298 */ 299 for (node = firstchild(node); node; node = nextsibling(node)) { 300 struct iommu_attach_args ia; 301 302 bzero(&ia, sizeof ia); 303 ia.iom_name = getpropstring(node, "name"); 304 305 /* Propagate BUS & DMA tags */ 306 ia.iom_bustag = ma->ma_bustag; 307 ia.iom_dmatag = &iommu_dma_tag; 308 309 ia.iom_node = node; 310 311 ia.iom_reg = NULL; 312 getprop(node, "reg", sizeof(struct sbus_reg), 313 &ia.iom_nreg, (void **)&ia.iom_reg); 314 315 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 316 if (ia.iom_reg != NULL) 317 free(ia.iom_reg, M_DEVBUF); 318 } 319 #endif 320 } 321 322 static void 323 iommu_copy_prom_entries(sc) 324 struct iommu_softc *sc; 325 { 326 u_int pbase, pa; 327 u_int range; 328 iopte_t *tpte_p; 329 u_int pagesz = sc->sc_pagesize; 330 int use_ac = (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc); 331 u_int mmupcr_save; 332 333 /* 334 * We read in the original table using MMU bypass and copy all 335 * of its entries to the appropriate place in our new table, 336 * even if the sizes are different. 337 * This is pretty easy since we know DVMA ends at 0xffffffff. 338 */ 339 340 range = (1 << 24) << 341 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 342 343 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 344 (14 - IOMMU_BAR_IBASHFT); 345 346 if (use_ac) { 347 /* 348 * Set MMU AC bit so we'll still read from the cache 349 * in by-pass mode. 350 */ 351 mmupcr_save = lda(SRMMU_PCR, ASI_SRMMU); 352 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save | VIKING_PCR_AC); 353 } else 354 mmupcr_save = 0; /* XXX - avoid GCC `unintialized' warning */ 355 356 /* Flush entire IOMMU TLB before messing with the in-memory tables */ 357 IOMMU_FLUSHALL(sc); 358 359 /* 360 * tpte_p = top of our PTE table 361 * pa = top of current PTE table 362 * Then work downwards and copy entries until we hit the bottom 363 * of either table. 364 */ 365 for (tpte_p = &sc->sc_ptes[((0 - IOMMU_DVMA_BASE)/pagesz) - 1], 366 pa = (u_int)pbase + (range/pagesz - 1)*sizeof(iopte_t); 367 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 368 tpte_p--, pa -= sizeof(iopte_t)) { 369 370 *tpte_p = lda(pa, ASI_BYPASS); 371 } 372 373 if (use_ac) { 374 /* restore mmu after bug-avoidance */ 375 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save); 376 } 377 } 378 379 void 380 iommu_enter(dva, pa) 381 bus_addr_t dva; 382 paddr_t pa; 383 { 384 struct iommu_softc *sc = iommu_sc; 385 int pte; 386 387 /* This routine relies on the fact that sc->sc_pagesize == PAGE_SIZE */ 388 389 #ifdef DIAGNOSTIC 390 if (dva < sc->sc_dvmabase) 391 panic("iommu_enter: dva 0x%lx not in DVMA space", (long)dva); 392 #endif 393 394 pte = atop(pa) << IOPTE_PPNSHFT; 395 pte &= IOPTE_PPN; 396 pte |= IOPTE_V | IOPTE_W | (has_iocache ? IOPTE_C : 0); 397 sc->sc_ptes[atop(dva - sc->sc_dvmabase)] = pte; 398 IOMMU_FLUSHPAGE(sc, dva); 399 } 400 401 /* 402 * iommu_clear: clears mappings created by iommu_enter 403 */ 404 void 405 iommu_remove(dva, len) 406 bus_addr_t dva; 407 bus_size_t len; 408 { 409 struct iommu_softc *sc = iommu_sc; 410 u_int pagesz = sc->sc_pagesize; 411 bus_addr_t base = sc->sc_dvmabase; 412 413 #ifdef DEBUG 414 if (dva < base) 415 panic("iommu_remove: va 0x%lx not in DVMA space", (long)dva); 416 #endif 417 418 while ((long)len > 0) { 419 #ifdef notyet 420 #ifdef DEBUG 421 if ((sc->sc_ptes[atop(dva - base)] & IOPTE_V) == 0) 422 panic("iommu_remove: clearing invalid pte at dva 0x%lx", 423 (long)dva); 424 #endif 425 #endif 426 sc->sc_ptes[atop(dva - base)] = 0; 427 IOMMU_FLUSHPAGE(sc, dva); 428 len -= pagesz; 429 dva += pagesz; 430 } 431 } 432 433 #if 0 /* These registers aren't there??? */ 434 void 435 iommu_error() 436 { 437 struct iommu_softc *sc = X; 438 struct iommureg *iop = sc->sc_reg; 439 440 printf("iommu: afsr 0x%x, afar 0x%x\n", iop->io_afsr, iop->io_afar); 441 printf("iommu: mfsr 0x%x, mfar 0x%x\n", iop->io_mfsr, iop->io_mfar); 442 } 443 int 444 iommu_alloc(va, len) 445 u_int va, len; 446 { 447 struct iommu_softc *sc = X; 448 int off, tva, iovaddr, pte; 449 paddr_t pa; 450 451 off = (int)va & PGOFSET; 452 len = round_page(len + off); 453 va -= off; 454 455 if ((int)sc->sc_dvmacur + len > 0) 456 sc->sc_dvmacur = sc->sc_dvmabase; 457 458 iovaddr = tva = sc->sc_dvmacur; 459 sc->sc_dvmacur += len; 460 while (len) { 461 (void) pmap_extract(pmap_kernel(), va, &pa); 462 463 #define IOMMU_PPNSHIFT 8 464 #define IOMMU_V 0x00000002 465 #define IOMMU_W 0x00000004 466 467 pte = atop(pa) << IOMMU_PPNSHIFT; 468 pte |= IOMMU_V | IOMMU_W; 469 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 470 sc->sc_reg->io_flushpage = tva; 471 len -= NBPG; 472 va += NBPG; 473 tva += NBPG; 474 } 475 return iovaddr + off; 476 } 477 #endif 478 479 480 /* 481 * IOMMU DMA map functions 482 */ 483 int 484 iommu_dmamap_create(t, size, nsegments, maxsegsz, boundary, flags, dmamp) 485 bus_dma_tag_t t; 486 bus_size_t size; 487 int nsegments; 488 bus_size_t maxsegsz; 489 bus_size_t boundary; 490 int flags; 491 bus_dmamap_t *dmamp; 492 { 493 bus_dmamap_t map; 494 int error; 495 496 if ((error = _bus_dmamap_create(t, size, nsegments, maxsegsz, 497 boundary, flags, &map)) != 0) 498 return (error); 499 500 if ((flags & BUS_DMA_24BIT) != 0) { 501 /* Limit this map to the range usable by `24-bit' devices */ 502 map->_dm_ex_start = D24_DVMA_BASE; 503 map->_dm_ex_end = D24_DVMA_END; 504 } else { 505 /* Enable allocations from the entire map */ 506 map->_dm_ex_start = iommu_dvmamap->ex_start; 507 map->_dm_ex_end = iommu_dvmamap->ex_end; 508 } 509 510 *dmamp = map; 511 return (0); 512 } 513 514 /* 515 * Internal routine to allocate space in the IOMMU map. 516 */ 517 int 518 iommu_dvma_alloc(map, va, len, flags, dvap, sgsizep) 519 bus_dmamap_t map; 520 vaddr_t va; 521 bus_size_t len; 522 int flags; 523 bus_addr_t *dvap; 524 bus_size_t *sgsizep; 525 { 526 bus_size_t sgsize; 527 u_long align, voff; 528 #if 0 529 u_long ex_start, ex_end; 530 #endif 531 int s, error; 532 int pagesz = PAGE_SIZE; 533 534 /* 535 * Remember page offset, then truncate the buffer address to 536 * a page boundary. 537 */ 538 voff = va & (pagesz - 1); 539 va &= -pagesz; 540 541 if (len > map->_dm_size) 542 return (EINVAL); 543 544 sgsize = (len + voff + pagesz - 1) & -pagesz; 545 align = dvma_cachealign ? dvma_cachealign : map->_dm_align; 546 547 s = splhigh(); 548 549 #if 0 550 /* Check `24 address bits' in the map's attributes */ 551 if ((map->_dm_flags & BUS_DMA_24BIT) != 0) { 552 ex_start = D24_DVMA_BASE; 553 ex_end = D24_DVMA_END; 554 } else { 555 ex_start = iommu_dvmamap->ex_start; 556 ex_end = iommu_dvmamap->ex_end; 557 } 558 #endif 559 error = extent_alloc_subregion1(iommu_dvmamap, 560 map->_dm_ex_start, map->_dm_ex_end, 561 sgsize, align, va & (align-1), 562 map->_dm_boundary, 563 (flags & BUS_DMA_NOWAIT) == 0 564 ? EX_WAITOK : EX_NOWAIT, 565 (u_long *)dvap); 566 splx(s); 567 568 *sgsizep = sgsize; 569 return (error); 570 } 571 572 /* 573 * IOMMU DMA map functions. 574 */ 575 int 576 iommu_dmamap_load(t, map, buf, buflen, p, flags) 577 bus_dma_tag_t t; 578 bus_dmamap_t map; 579 void *buf; 580 bus_size_t buflen; 581 struct proc *p; 582 int flags; 583 { 584 bus_size_t sgsize; 585 bus_addr_t dva; 586 vaddr_t va = (vaddr_t)buf; 587 int pagesz = PAGE_SIZE; 588 pmap_t pmap; 589 int error; 590 591 /* 592 * Make sure that on error condition we return "no valid mappings". 593 */ 594 map->dm_nsegs = 0; 595 596 /* Allocate IOMMU resources */ 597 if ((error = iommu_dvma_alloc(map, va, buflen, flags, 598 &dva, &sgsize)) != 0) 599 return (error); 600 601 cpuinfo.cache_flush(buf, buflen); /* XXX - move to bus_dma_sync? */ 602 603 /* 604 * We always use just one segment. 605 */ 606 map->dm_mapsize = buflen; 607 map->dm_nsegs = 1; 608 map->dm_segs[0].ds_addr = dva + (va & (pagesz - 1)); 609 map->dm_segs[0].ds_len = buflen; 610 map->dm_segs[0]._ds_sgsize = sgsize; 611 612 if (p != NULL) 613 pmap = p->p_vmspace->vm_map.pmap; 614 else 615 pmap = pmap_kernel(); 616 617 for (; sgsize != 0; ) { 618 paddr_t pa; 619 /* 620 * Get the physical address for this page. 621 */ 622 (void) pmap_extract(pmap, va, &pa); 623 624 iommu_enter(dva, pa); 625 626 dva += pagesz; 627 va += pagesz; 628 sgsize -= pagesz; 629 } 630 631 return (0); 632 } 633 634 /* 635 * Like _bus_dmamap_load(), but for mbufs. 636 */ 637 int 638 iommu_dmamap_load_mbuf(t, map, m, flags) 639 bus_dma_tag_t t; 640 bus_dmamap_t map; 641 struct mbuf *m; 642 int flags; 643 { 644 645 panic("_bus_dmamap_load_mbuf: not implemented"); 646 } 647 648 /* 649 * Like _bus_dmamap_load(), but for uios. 650 */ 651 int 652 iommu_dmamap_load_uio(t, map, uio, flags) 653 bus_dma_tag_t t; 654 bus_dmamap_t map; 655 struct uio *uio; 656 int flags; 657 { 658 659 panic("_bus_dmamap_load_uio: not implemented"); 660 } 661 662 /* 663 * Like _bus_dmamap_load(), but for raw memory allocated with 664 * bus_dmamem_alloc(). 665 */ 666 int 667 iommu_dmamap_load_raw(t, map, segs, nsegs, size, flags) 668 bus_dma_tag_t t; 669 bus_dmamap_t map; 670 bus_dma_segment_t *segs; 671 int nsegs; 672 bus_size_t size; 673 int flags; 674 { 675 vm_page_t m; 676 paddr_t pa; 677 bus_addr_t dva; 678 bus_size_t sgsize; 679 struct pglist *mlist; 680 int pagesz = PAGE_SIZE; 681 int error; 682 683 map->dm_nsegs = 0; 684 685 /* Allocate IOMMU resources */ 686 if ((error = iommu_dvma_alloc(map, segs[0]._ds_va, size, 687 flags, &dva, &sgsize)) != 0) 688 return (error); 689 690 /* 691 * Note DVMA address in case bus_dmamem_map() is called later. 692 * It can then insure cache coherency by choosing a KVA that 693 * is aligned to `ds_addr'. 694 */ 695 segs[0].ds_addr = dva; 696 segs[0].ds_len = size; 697 698 map->dm_segs[0].ds_addr = dva; 699 map->dm_segs[0].ds_len = size; 700 map->dm_segs[0]._ds_sgsize = sgsize; 701 702 /* Map physical pages into IOMMU */ 703 mlist = segs[0]._ds_mlist; 704 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 705 if (sgsize == 0) 706 panic("iommu_dmamap_load_raw: size botch"); 707 pa = VM_PAGE_TO_PHYS(m); 708 iommu_enter(dva, pa); 709 dva += pagesz; 710 sgsize -= pagesz; 711 } 712 713 map->dm_nsegs = 1; 714 map->dm_mapsize = size; 715 716 return (0); 717 } 718 719 /* 720 * Unload an IOMMU DMA map. 721 */ 722 void 723 iommu_dmamap_unload(t, map) 724 bus_dma_tag_t t; 725 bus_dmamap_t map; 726 { 727 bus_dma_segment_t *segs = map->dm_segs; 728 int nsegs = map->dm_nsegs; 729 bus_addr_t dva; 730 bus_size_t len; 731 int i, s, error; 732 733 for (i = 0; i < nsegs; i++) { 734 dva = segs[i].ds_addr & -PAGE_SIZE; 735 len = segs[i]._ds_sgsize; 736 737 iommu_remove(dva, len); 738 s = splhigh(); 739 error = extent_free(iommu_dvmamap, dva, len, EX_NOWAIT); 740 splx(s); 741 if (error != 0) 742 printf("warning: %ld of DVMA space lost\n", (long)len); 743 } 744 745 /* Mark the mappings as invalid. */ 746 map->dm_mapsize = 0; 747 map->dm_nsegs = 0; 748 } 749 750 /* 751 * DMA map synchronization. 752 */ 753 void 754 iommu_dmamap_sync(t, map, offset, len, ops) 755 bus_dma_tag_t t; 756 bus_dmamap_t map; 757 bus_addr_t offset; 758 bus_size_t len; 759 int ops; 760 { 761 762 /* 763 * XXX Should flush CPU write buffers. 764 */ 765 } 766 767 /* 768 * Map DMA-safe memory. 769 */ 770 int 771 iommu_dmamem_map(t, segs, nsegs, size, kvap, flags) 772 bus_dma_tag_t t; 773 bus_dma_segment_t *segs; 774 int nsegs; 775 size_t size; 776 caddr_t *kvap; 777 int flags; 778 { 779 vm_page_t m; 780 vaddr_t va; 781 bus_addr_t addr; 782 struct pglist *mlist; 783 int cbit; 784 u_long align; 785 int pagesz = PAGE_SIZE; 786 787 if (nsegs != 1) 788 panic("iommu_dmamem_map: nsegs = %d", nsegs); 789 790 cbit = has_iocache ? 0 : PMAP_NC; 791 align = dvma_cachealign ? dvma_cachealign : pagesz; 792 793 size = round_page(size); 794 795 /* 796 * In case the segment has already been loaded by 797 * iommu_dmamap_load_raw(), find a region of kernel virtual 798 * addresses that can accomodate our aligment requirements. 799 */ 800 va = _bus_dma_valloc_skewed(size, 0, align, 801 segs[0].ds_addr & (align - 1)); 802 if (va == 0) 803 return (ENOMEM); 804 805 segs[0]._ds_va = va; 806 *kvap = (caddr_t)va; 807 808 /* 809 * Map the pages allocated in _bus_dmamem_alloc() to the 810 * kernel virtual address space. 811 */ 812 mlist = segs[0]._ds_mlist; 813 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 814 815 if (size == 0) 816 panic("iommu_dmamem_map: size botch"); 817 818 addr = VM_PAGE_TO_PHYS(m); 819 pmap_enter(pmap_kernel(), va, addr | cbit, 820 VM_PROT_READ | VM_PROT_WRITE, 821 VM_PROT_READ | VM_PROT_WRITE | PMAP_WIRED); 822 #if 0 823 if (flags & BUS_DMA_COHERENT) 824 /* XXX */; 825 #endif 826 va += pagesz; 827 size -= pagesz; 828 } 829 830 return (0); 831 } 832 833 /* 834 * mmap(2)'ing DMA-safe memory. 835 */ 836 int 837 iommu_dmamem_mmap(t, segs, nsegs, off, prot, flags) 838 bus_dma_tag_t t; 839 bus_dma_segment_t *segs; 840 int nsegs, off, prot, flags; 841 { 842 843 panic("_bus_dmamem_mmap: not implemented"); 844 } 845
Indexes created Wed Oct 01 07:09:59 GMT 2025