iommu.c revision 1.5
1 /* $NetBSD: iommu.c,v 1.5 1996/08/27 21:57:31 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <vm/vm.h> 43 44 #include <machine/autoconf.h> 45 #include <machine/ctlreg.h> 46 #include <sparc/sparc/asm.h> 47 #include <sparc/sparc/vaddrs.h> 48 #include <sparc/sparc/iommureg.h> 49 50 struct iommu_softc { 51 struct device sc_dev; /* base device */ 52 struct iommureg *sc_reg; 53 u_int sc_pagesize; 54 u_int sc_range; 55 u_int sc_dvmabase; 56 iopte_t *sc_ptes; 57 int sc_hasiocache; 58 }; 59 struct iommu_softc *iommu_sc;/*XXX*/ 60 int has_iocache; 61 62 63 /* autoconfiguration driver */ 64 int iommu_print __P((void *, const char *)); 65 void iommu_attach __P((struct device *, struct device *, void *)); 66 int iommu_match __P((struct device *, void *, void *)); 67 68 struct cfattach iommu_ca = { 69 sizeof(struct iommu_softc), iommu_match, iommu_attach 70 }; 71 72 struct cfdriver iommu_cd = { 73 NULL, "iommu", DV_DULL 74 }; 75 76 /* 77 * Print the location of some iommu-attached device (called just 78 * before attaching that device). If `iommu' is not NULL, the 79 * device was found but not configured; print the iommu as well. 80 * Return UNCONF (config_find ignores this if the device was configured). 81 */ 82 int 83 iommu_print(args, iommu) 84 void *args; 85 const char *iommu; 86 { 87 register struct confargs *ca = args; 88 89 if (iommu) 90 printf("%s at %s", ca->ca_ra.ra_name, iommu); 91 return (UNCONF); 92 } 93 94 int 95 iommu_match(parent, vcf, aux) 96 struct device *parent; 97 void *vcf, *aux; 98 { 99 struct cfdata *cf = vcf; 100 register struct confargs *ca = aux; 101 register struct romaux *ra = &ca->ca_ra; 102 103 if (CPU_ISSUN4OR4C) 104 return (0); 105 return (strcmp(cf->cf_driver->cd_name, ra->ra_name) == 0); 106 } 107 108 /* 109 * Attach the iommu. 110 */ 111 void 112 iommu_attach(parent, self, aux) 113 struct device *parent; 114 struct device *self; 115 void *aux; 116 { 117 #if defined(SUN4M) 118 register struct iommu_softc *sc = (struct iommu_softc *)self; 119 struct confargs oca, *ca = aux; 120 register struct romaux *ra = &ca->ca_ra; 121 register int node; 122 register char *name; 123 register u_int pbase, pa; 124 register int i, mmupcrsav, s, wierdviking = 0; 125 register iopte_t *tpte_p; 126 extern u_int *kernel_iopte_table; 127 extern u_int kernel_iopte_table_pa; 128 129 /*XXX-GCC!*/mmupcrsav=0; 130 iommu_sc = sc; 131 /* 132 * XXX there is only one iommu, for now -- do not know how to 133 * address children on others 134 */ 135 if (sc->sc_dev.dv_unit > 0) { 136 printf(" unsupported\n"); 137 return; 138 } 139 node = ra->ra_node; 140 141 #if 0 142 if (ra->ra_vaddr) 143 sc->sc_reg = (struct iommureg *)ca->ca_ra.ra_vaddr; 144 #else 145 /* 146 * Map registers into our space. The PROM may have done this 147 * already, but I feel better if we have our own copy. Plus, the 148 * prom doesn't map the entire register set 149 * 150 * XXX struct iommureg is bigger than ra->ra_len; what are the 151 * other fields for? 152 */ 153 sc->sc_reg = (struct iommureg *) 154 mapdev(ra->ra_reg, 0, 0, ra->ra_len, ra->ra_iospace); 155 #endif 156 157 sc->sc_hasiocache = node_has_property(node, "cache-coherence?"); 158 has_iocache = sc->sc_hasiocache; /* Set global flag */ 159 160 sc->sc_pagesize = getpropint(node, "page-size", NBPG), 161 sc->sc_range = (1 << 24) << 162 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 163 #if 0 164 sc->sc_dvmabase = (0 - sc->sc_range); 165 #endif 166 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 167 (14 - IOMMU_BAR_IBASHFT); 168 169 /* 170 * Now we build our own copy of the IOMMU page tables. We need to 171 * do this since we're going to change the range to give us 64M of 172 * mappings, and thus we can move DVMA space down to 0xfd000000 to 173 * give us lots of space and to avoid bumping into the PROM, etc. 174 * 175 * XXX Note that this is rather messy. 176 */ 177 sc->sc_ptes = (iopte_t *) kernel_iopte_table; 178 179 /* 180 * Now discache the page tables so that the IOMMU sees our 181 * changes. 182 */ 183 kvm_uncache((caddr_t)sc->sc_ptes, 184 (((0 - DVMA4M_BASE)/sc->sc_pagesize) * sizeof(iopte_t)) / NBPG); 185 186 /* 187 * Ok. We've got to read in the original table using MMU bypass, 188 * and copy all of its entries to the appropriate place in our 189 * new table, even if the sizes are different. 190 * This is pretty easy since we know DVMA ends at 0xffffffff. 191 * 192 * XXX: PGOFSET, NBPG assume same page size as SRMMU 193 */ 194 if ((getpsr() & 0x40000000) && (!(lda(SRMMU_PCR,ASI_SRMMU) & 0x800))) { 195 wierdviking = 1; 196 sta(SRMMU_PCR, ASI_SRMMU, /* set MMU AC bit */ 197 ((mmupcrsav = lda(SRMMU_PCR,ASI_SRMMU)) | SRMMU_PCR_AC)); 198 } 199 200 for (tpte_p = &sc->sc_ptes[((0 - DVMA4M_BASE)/NBPG) - 1], 201 pa = (u_int)pbase - sizeof(iopte_t) + 202 ((u_int)sc->sc_range/NBPG)*sizeof(iopte_t); 203 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 204 tpte_p--, pa -= sizeof(iopte_t)) { 205 206 IOMMU_FLUSHPAGE(sc, 207 (tpte_p - &sc->sc_ptes[0])*NBPG + DVMA4M_BASE); 208 *tpte_p = lda(pa, ASI_BYPASS); 209 } 210 if (wierdviking) { /* restore mmu after bug-avoidance */ 211 sta(SRMMU_PCR, ASI_SRMMU, mmupcrsav); 212 } 213 214 /* 215 * Now we can install our new pagetable into the IOMMU 216 */ 217 sc->sc_range = 0 - DVMA4M_BASE; 218 sc->sc_dvmabase = DVMA4M_BASE; 219 220 /* calculate log2(sc->sc_range/16MB) */ 221 i = ffs(sc->sc_range/(1 << 24)) - 1; 222 if ((1 << i) != (sc->sc_range/(1 << 24))) 223 panic("bad iommu range: %d\n",i); 224 225 s = splhigh(); 226 IOMMU_FLUSHALL(sc); 227 228 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 229 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 230 sc->sc_reg->io_bar = (kernel_iopte_table_pa >> 4) & IOMMU_BAR_IBA; 231 232 IOMMU_FLUSHALL(sc); 233 splx(s); 234 235 printf(": version %x/%x, page-size %d, range %dMB\n", 236 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 237 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 238 sc->sc_pagesize, 239 sc->sc_range >> 20); 240 241 /* Propagate bootpath */ 242 if (ra->ra_bp != NULL && strcmp(ra->ra_bp->name, "iommu") == 0) 243 oca.ca_ra.ra_bp = ra->ra_bp + 1; 244 else 245 oca.ca_ra.ra_bp = NULL; 246 247 /* 248 * Loop through ROM children (expect Sbus among them). 249 */ 250 for (node = firstchild(node); node; node = nextsibling(node)) { 251 name = getpropstring(node, "name"); 252 if (!romprop(&oca.ca_ra, name, node)) 253 continue; 254 oca.ca_bustype = BUS_MAIN; /* ??? */ 255 (void) config_found(&sc->sc_dev, (void *)&oca, iommu_print); 256 } 257 #endif 258 } 259 260 void 261 iommu_enter(va, pa) 262 u_int va, pa; 263 { 264 struct iommu_softc *sc = iommu_sc; 265 int pte; 266 267 #ifdef DEBUG 268 if (va < sc->sc_dvmabase) 269 panic("iommu_enter: va 0x%x not in DVMA space",va); 270 #endif 271 272 pte = atop(pa) << IOPTE_PPNSHFT; 273 pte &= IOPTE_PPN; 274 pte |= IOPTE_V | IOPTE_W | (has_iocache ? IOPTE_C : 0); 275 sc->sc_ptes[atop(va - sc->sc_dvmabase)] = pte; 276 IOMMU_FLUSHPAGE(sc, va); 277 } 278 279 /* 280 * iommu_clear: clears mappings created by iommu_enter 281 */ 282 void 283 iommu_remove(va, len) 284 register u_int va, len; 285 { 286 register struct iommu_softc *sc = iommu_sc; 287 288 #ifdef DEBUG 289 if (va < sc->sc_dvmabase) 290 panic("iommu_enter: va 0x%x not in DVMA space", va); 291 #endif 292 293 while (len > 0) { 294 #ifdef notyet 295 #ifdef DEBUG 296 if ((sc->sc_ptes[atop(va - sc->sc_dvmabase)] & IOPTE_V) == 0) 297 panic("iommu_clear: clearing invalid pte at va 0x%x", 298 va); 299 #endif 300 #endif 301 sc->sc_ptes[atop(va - sc->sc_dvmabase)] = 0; 302 sta(sc->sc_ptes + atop(va - sc->sc_dvmabase), ASI_BYPASS, 0); 303 IOMMU_FLUSHPAGE(sc, va); 304 len -= sc->sc_pagesize; 305 va += sc->sc_pagesize; 306 } 307 } 308 309 #if 0 /* These registers aren't there??? */ 310 void 311 iommu_error() 312 { 313 struct iommu_softc *sc = X; 314 struct iommureg *iop = sc->sc_reg; 315 316 printf("iommu: afsr %x, afar %x\n", iop->io_afsr, iop->io_afar); 317 printf("iommu: mfsr %x, mfar %x\n", iop->io_mfsr, iop->io_mfar); 318 } 319 int 320 iommu_alloc(va, len) 321 u_int va, len; 322 { 323 struct iommu_softc *sc = X; 324 int off, tva, pa, iovaddr, pte; 325 326 off = (int)va & PGOFSET; 327 len = round_page(len + off); 328 va -= off; 329 330 if ((int)sc->sc_dvmacur + len > 0) 331 sc->sc_dvmacur = sc->sc_dvmabase; 332 333 iovaddr = tva = sc->sc_dvmacur; 334 sc->sc_dvmacur += len; 335 while (len) { 336 pa = pmap_extract(pmap_kernel(), va); 337 338 #define IOMMU_PPNSHIFT 8 339 #define IOMMU_V 0x00000002 340 #define IOMMU_W 0x00000004 341 342 pte = atop(pa) << IOMMU_PPNSHIFT; 343 pte |= IOMMU_V | IOMMU_W; 344 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 345 sc->sc_reg->io_flushpage = tva; 346 len -= NBPG; 347 va += NBPG; 348 tva += NBPG; 349 } 350 return iovaddr + off; 351 } 352 #endif 353
Indexes created Tue Sep 30 20:09:53 GMT 2025