iommu.c revision 1.57
1 /* $NetBSD: iommu.c,v 1.57 2001/09/26 20:53:08 eeh Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/param.h> 40 #include <sys/extent.h> 41 #include <sys/malloc.h> 42 #include <sys/queue.h> 43 #include <sys/systm.h> 44 #include <sys/device.h> 45 46 #include <uvm/uvm.h> 47 48 #define _SPARC_BUS_DMA_PRIVATE 49 #include <machine/bus.h> 50 #include <machine/autoconf.h> 51 #include <machine/ctlreg.h> 52 #include <sparc/sparc/asm.h> 53 #include <sparc/sparc/vaddrs.h> 54 #include <sparc/sparc/cpuvar.h> 55 #include <sparc/sparc/iommureg.h> 56 #include <sparc/sparc/iommuvar.h> 57 58 struct iommu_softc { 59 struct device sc_dev; /* base device */ 60 struct iommureg *sc_reg; 61 u_int sc_pagesize; 62 u_int sc_range; 63 bus_addr_t sc_dvmabase; 64 iopte_t *sc_ptes; 65 int sc_hasiocache; 66 }; 67 struct iommu_softc *iommu_sc;/*XXX*/ 68 int has_iocache; 69 u_long dvma_cachealign; 70 71 /* 72 * Note: operations on the extent map are being protected with 73 * splhigh(), since we cannot predict at which interrupt priority 74 * our clients will run. 75 */ 76 struct extent *iommu_dvmamap; 77 78 79 /* autoconfiguration driver */ 80 int iommu_print __P((void *, const char *)); 81 void iommu_attach __P((struct device *, struct device *, void *)); 82 int iommu_match __P((struct device *, struct cfdata *, void *)); 83 84 static void iommu_copy_prom_entries __P((struct iommu_softc *)); 85 86 struct cfattach iommu_ca = { 87 sizeof(struct iommu_softc), iommu_match, iommu_attach 88 }; 89 90 /* IOMMU DMA map functions */ 91 int iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 92 bus_size_t, int, bus_dmamap_t *)); 93 int iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 94 bus_size_t, struct proc *, int)); 95 int iommu_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, 96 struct mbuf *, int)); 97 int iommu_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, 98 struct uio *, int)); 99 int iommu_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 100 bus_dma_segment_t *, int, bus_size_t, int)); 101 void iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 102 void iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 103 bus_size_t, int)); 104 105 int iommu_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 106 int nsegs, size_t size, caddr_t *kvap, int flags)); 107 paddr_t iommu_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 108 int nsegs, off_t off, int prot, int flags)); 109 int iommu_dvma_alloc(bus_dmamap_t, vaddr_t, bus_size_t, int, 110 bus_addr_t *, bus_size_t *); 111 112 113 struct sparc_bus_dma_tag iommu_dma_tag = { 114 NULL, 115 iommu_dmamap_create, 116 _bus_dmamap_destroy, 117 iommu_dmamap_load, 118 iommu_dmamap_load_mbuf, 119 iommu_dmamap_load_uio, 120 iommu_dmamap_load_raw, 121 iommu_dmamap_unload, 122 iommu_dmamap_sync, 123 124 _bus_dmamem_alloc, 125 _bus_dmamem_free, 126 iommu_dmamem_map, 127 _bus_dmamem_unmap, 128 iommu_dmamem_mmap 129 }; 130 /* 131 * Print the location of some iommu-attached device (called just 132 * before attaching that device). If `iommu' is not NULL, the 133 * device was found but not configured; print the iommu as well. 134 * Return UNCONF (config_find ignores this if the device was configured). 135 */ 136 int 137 iommu_print(args, iommu) 138 void *args; 139 const char *iommu; 140 { 141 struct iommu_attach_args *ia = args; 142 143 if (iommu) 144 printf("%s at %s", ia->iom_name, iommu); 145 return (UNCONF); 146 } 147 148 int 149 iommu_match(parent, cf, aux) 150 struct device *parent; 151 struct cfdata *cf; 152 void *aux; 153 { 154 struct mainbus_attach_args *ma = aux; 155 156 if (CPU_ISSUN4OR4C) 157 return (0); 158 return (strcmp(cf->cf_driver->cd_name, ma->ma_name) == 0); 159 } 160 161 /* 162 * Attach the iommu. 163 */ 164 void 165 iommu_attach(parent, self, aux) 166 struct device *parent; 167 struct device *self; 168 void *aux; 169 { 170 #if defined(SUN4M) 171 struct iommu_softc *sc = (struct iommu_softc *)self; 172 struct mainbus_attach_args *ma = aux; 173 bus_space_handle_t bh; 174 int node; 175 int js1_implicit_iommu; 176 int i, s; 177 u_int iopte_table_pa; 178 struct pglist mlist; 179 u_int size; 180 struct vm_page *m; 181 vaddr_t va; 182 183 /* 184 * XXX there is only one iommu, for now -- do not know how to 185 * address children on others 186 */ 187 if (sc->sc_dev.dv_unit > 0) { 188 printf(" unsupported\n"); 189 return; 190 } 191 iommu_sc = sc; 192 193 /* 194 * JS1/OF device tree does not have an iommu node and sbus 195 * node is directly under root. mainbus_attach detects this 196 * and calls us with sbus node instead so that we can attach 197 * implicit iommu and attach that sbus node under it. 198 */ 199 node = ma->ma_node; 200 if (strcmp(PROM_getpropstring(node, "name"), "sbus") == 0) 201 js1_implicit_iommu = 1; 202 else 203 js1_implicit_iommu = 0; 204 205 /* 206 * Map registers into our space. The PROM may have done this 207 * already, but I feel better if we have our own copy. Plus, the 208 * prom doesn't map the entire register set. 209 * 210 * XXX struct iommureg is bigger than ra->ra_len; what are the 211 * other fields for? 212 */ 213 if (bus_space_map2( 214 ma->ma_bustag, 215 ma->ma_iospace, 216 ma->ma_paddr, 217 sizeof(struct iommureg), 218 0, 219 0, 220 &bh) != 0) { 221 printf("iommu_attach: cannot map registers\n"); 222 return; 223 } 224 sc->sc_reg = (struct iommureg *)bh; 225 226 sc->sc_hasiocache = js1_implicit_iommu ? 0 227 : node_has_property(node, "cache-coherence?"); 228 if (CACHEINFO.c_enabled == 0) /* XXX - is this correct? */ 229 sc->sc_hasiocache = 0; 230 has_iocache = sc->sc_hasiocache; /* Set global flag */ 231 232 sc->sc_pagesize = js1_implicit_iommu ? NBPG 233 : PROM_getpropint(node, "page-size", NBPG), 234 235 /* 236 * Allocate memory for I/O pagetables. 237 * This takes 64K of contiguous physical memory to map 64M of 238 * DVMA space (starting at IOMMU_DVMA_BASE). 239 * The table must be aligned on a (-IOMMU_DVMA_BASE/pagesize) 240 * boundary (i.e. 64K for 64M of DVMA space). 241 */ 242 243 size = ((0 - IOMMU_DVMA_BASE) / sc->sc_pagesize) * sizeof(iopte_t); 244 TAILQ_INIT(&mlist); 245 if (uvm_pglistalloc(size, vm_first_phys, vm_first_phys+vm_num_phys, 246 size, 0, &mlist, 1, 0) != 0) 247 panic("iommu_attach: no memory"); 248 249 va = uvm_km_valloc(kernel_map, size); 250 if (va == 0) 251 panic("iommu_attach: no memory"); 252 253 sc->sc_ptes = (iopte_t *)va; 254 255 m = TAILQ_FIRST(&mlist); 256 iopte_table_pa = VM_PAGE_TO_PHYS(m); 257 258 /* Map the pages */ 259 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 260 paddr_t pa = VM_PAGE_TO_PHYS(m); 261 pmap_enter(pmap_kernel(), va, pa | PMAP_NC, 262 VM_PROT_READ|VM_PROT_WRITE, PMAP_WIRED); 263 va += NBPG; 264 } 265 pmap_update(pmap_kernel()); 266 267 /* 268 * Copy entries from current IOMMU table. 269 * XXX - Why do we need to do this? 270 */ 271 iommu_copy_prom_entries(sc); 272 273 /* 274 * Now we can install our new pagetable into the IOMMU 275 */ 276 sc->sc_range = 0 - IOMMU_DVMA_BASE; 277 sc->sc_dvmabase = IOMMU_DVMA_BASE; 278 279 /* calculate log2(sc->sc_range/16MB) */ 280 i = ffs(sc->sc_range/(1 << 24)) - 1; 281 if ((1 << i) != (sc->sc_range/(1 << 24))) 282 panic("iommu: bad range: %d\n", i); 283 284 s = splhigh(); 285 IOMMU_FLUSHALL(sc); 286 287 /* Load range and physical address of PTEs */ 288 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 289 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 290 sc->sc_reg->io_bar = (iopte_table_pa >> 4) & IOMMU_BAR_IBA; 291 292 IOMMU_FLUSHALL(sc); 293 splx(s); 294 295 printf(": version 0x%x/0x%x, page-size %d, range %dMB\n", 296 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 297 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 298 sc->sc_pagesize, 299 sc->sc_range >> 20); 300 301 iommu_dvmamap = extent_create("iommudvma", 302 IOMMU_DVMA_BASE, IOMMU_DVMA_END, 303 M_DEVBUF, 0, 0, EX_NOWAIT); 304 if (iommu_dvmamap == NULL) 305 panic("iommu: unable to allocate DVMA map"); 306 307 /* 308 * If we are attaching implicit iommu on JS1/OF we do not have 309 * an iommu node to traverse, instead mainbus_attach passed us 310 * sbus node in ma.ma_node. Attach it as the only iommu child. 311 */ 312 if (js1_implicit_iommu) { 313 struct iommu_attach_args ia; 314 struct iommu_reg sbus_iommu_reg = { 0, 0x10001000, 0x28 }; 315 316 bzero(&ia, sizeof ia); 317 318 /* Propagate BUS & DMA tags */ 319 ia.iom_bustag = ma->ma_bustag; 320 ia.iom_dmatag = &iommu_dma_tag; 321 322 ia.iom_name = "sbus"; 323 ia.iom_node = node; 324 ia.iom_reg = &sbus_iommu_reg; 325 ia.iom_nreg = 1; 326 327 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 328 return; 329 } 330 331 /* 332 * Loop through ROM children (expect Sbus among them). 333 */ 334 for (node = firstchild(node); node; node = nextsibling(node)) { 335 struct iommu_attach_args ia; 336 337 bzero(&ia, sizeof ia); 338 ia.iom_name = PROM_getpropstring(node, "name"); 339 340 /* Propagate BUS & DMA tags */ 341 ia.iom_bustag = ma->ma_bustag; 342 ia.iom_dmatag = &iommu_dma_tag; 343 344 ia.iom_node = node; 345 346 ia.iom_reg = NULL; 347 PROM_getprop(node, "reg", sizeof(struct sbus_reg), 348 &ia.iom_nreg, (void **)&ia.iom_reg); 349 350 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 351 if (ia.iom_reg != NULL) 352 free(ia.iom_reg, M_DEVBUF); 353 } 354 #endif 355 } 356 357 static void 358 iommu_copy_prom_entries(sc) 359 struct iommu_softc *sc; 360 { 361 u_int pbase, pa; 362 u_int range; 363 iopte_t *tpte_p; 364 u_int pagesz = sc->sc_pagesize; 365 int use_ac = (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc); 366 u_int mmupcr_save; 367 368 /* 369 * We read in the original table using MMU bypass and copy all 370 * of its entries to the appropriate place in our new table, 371 * even if the sizes are different. 372 * This is pretty easy since we know DVMA ends at 0xffffffff. 373 */ 374 375 range = (1 << 24) << 376 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 377 378 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 379 (14 - IOMMU_BAR_IBASHFT); 380 381 if (use_ac) { 382 /* 383 * Set MMU AC bit so we'll still read from the cache 384 * in by-pass mode. 385 */ 386 mmupcr_save = lda(SRMMU_PCR, ASI_SRMMU); 387 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save | VIKING_PCR_AC); 388 } else 389 mmupcr_save = 0; /* XXX - avoid GCC `unintialized' warning */ 390 391 /* Flush entire IOMMU TLB before messing with the in-memory tables */ 392 IOMMU_FLUSHALL(sc); 393 394 /* 395 * tpte_p = top of our PTE table 396 * pa = top of current PTE table 397 * Then work downwards and copy entries until we hit the bottom 398 * of either table. 399 */ 400 for (tpte_p = &sc->sc_ptes[((0 - IOMMU_DVMA_BASE)/pagesz) - 1], 401 pa = (u_int)pbase + (range/pagesz - 1)*sizeof(iopte_t); 402 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 403 tpte_p--, pa -= sizeof(iopte_t)) { 404 405 *tpte_p = lda(pa, ASI_BYPASS); 406 } 407 408 if (use_ac) { 409 /* restore mmu after bug-avoidance */ 410 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save); 411 } 412 } 413 414 void 415 iommu_enter(dva, pa) 416 bus_addr_t dva; 417 paddr_t pa; 418 { 419 struct iommu_softc *sc = iommu_sc; 420 int pte; 421 422 /* This routine relies on the fact that sc->sc_pagesize == PAGE_SIZE */ 423 424 #ifdef DIAGNOSTIC 425 if (dva < sc->sc_dvmabase) 426 panic("iommu_enter: dva 0x%lx not in DVMA space", (long)dva); 427 #endif 428 429 pte = atop(pa) << IOPTE_PPNSHFT; 430 pte &= IOPTE_PPN; 431 pte |= IOPTE_V | IOPTE_W | (has_iocache ? IOPTE_C : 0); 432 sc->sc_ptes[atop(dva - sc->sc_dvmabase)] = pte; 433 IOMMU_FLUSHPAGE(sc, dva); 434 } 435 436 /* 437 * iommu_clear: clears mappings created by iommu_enter 438 */ 439 void 440 iommu_remove(dva, len) 441 bus_addr_t dva; 442 bus_size_t len; 443 { 444 struct iommu_softc *sc = iommu_sc; 445 u_int pagesz = sc->sc_pagesize; 446 bus_addr_t base = sc->sc_dvmabase; 447 448 #ifdef DEBUG 449 if (dva < base) 450 panic("iommu_remove: va 0x%lx not in DVMA space", (long)dva); 451 #endif 452 453 while ((long)len > 0) { 454 #ifdef notyet 455 #ifdef DEBUG 456 if ((sc->sc_ptes[atop(dva - base)] & IOPTE_V) == 0) 457 panic("iommu_remove: clearing invalid pte at dva 0x%lx", 458 (long)dva); 459 #endif 460 #endif 461 sc->sc_ptes[atop(dva - base)] = 0; 462 IOMMU_FLUSHPAGE(sc, dva); 463 len -= pagesz; 464 dva += pagesz; 465 } 466 } 467 468 #if 0 /* These registers aren't there??? */ 469 void 470 iommu_error() 471 { 472 struct iommu_softc *sc = X; 473 struct iommureg *iop = sc->sc_reg; 474 475 printf("iommu: afsr 0x%x, afar 0x%x\n", iop->io_afsr, iop->io_afar); 476 printf("iommu: mfsr 0x%x, mfar 0x%x\n", iop->io_mfsr, iop->io_mfar); 477 } 478 int 479 iommu_alloc(va, len) 480 u_int va, len; 481 { 482 struct iommu_softc *sc = X; 483 int off, tva, iovaddr, pte; 484 paddr_t pa; 485 486 off = (int)va & PGOFSET; 487 len = round_page(len + off); 488 va -= off; 489 490 if ((int)sc->sc_dvmacur + len > 0) 491 sc->sc_dvmacur = sc->sc_dvmabase; 492 493 iovaddr = tva = sc->sc_dvmacur; 494 sc->sc_dvmacur += len; 495 while (len) { 496 (void) pmap_extract(pmap_kernel(), va, &pa); 497 498 #define IOMMU_PPNSHIFT 8 499 #define IOMMU_V 0x00000002 500 #define IOMMU_W 0x00000004 501 502 pte = atop(pa) << IOMMU_PPNSHIFT; 503 pte |= IOMMU_V | IOMMU_W; 504 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 505 sc->sc_reg->io_flushpage = tva; 506 len -= NBPG; 507 va += NBPG; 508 tva += NBPG; 509 } 510 return iovaddr + off; 511 } 512 #endif 513 514 515 /* 516 * IOMMU DMA map functions. 517 */ 518 int 519 iommu_dmamap_create(t, size, nsegments, maxsegsz, boundary, flags, dmamp) 520 bus_dma_tag_t t; 521 bus_size_t size; 522 int nsegments; 523 bus_size_t maxsegsz; 524 bus_size_t boundary; 525 int flags; 526 bus_dmamap_t *dmamp; 527 { 528 bus_dmamap_t map; 529 int error; 530 531 if ((error = _bus_dmamap_create(t, size, nsegments, maxsegsz, 532 boundary, flags, &map)) != 0) 533 return (error); 534 535 if ((flags & BUS_DMA_24BIT) != 0) { 536 /* Limit this map to the range usable by `24-bit' devices */ 537 map->_dm_ex_start = D24_DVMA_BASE; 538 map->_dm_ex_end = D24_DVMA_END; 539 } else { 540 /* Enable allocations from the entire map */ 541 map->_dm_ex_start = iommu_dvmamap->ex_start; 542 map->_dm_ex_end = iommu_dvmamap->ex_end; 543 } 544 545 *dmamp = map; 546 return (0); 547 } 548 549 /* 550 * Internal routine to allocate space in the IOMMU map. 551 */ 552 int 553 iommu_dvma_alloc(map, va, len, flags, dvap, sgsizep) 554 bus_dmamap_t map; 555 vaddr_t va; 556 bus_size_t len; 557 int flags; 558 bus_addr_t *dvap; 559 bus_size_t *sgsizep; 560 { 561 bus_size_t sgsize; 562 u_long align, voff, dvaddr; 563 int s, error; 564 int pagesz = PAGE_SIZE; 565 566 /* 567 * Remember page offset, then truncate the buffer address to 568 * a page boundary. 569 */ 570 voff = va & (pagesz - 1); 571 va &= -pagesz; 572 573 if (len > map->_dm_size) 574 return (EINVAL); 575 576 sgsize = (len + voff + pagesz - 1) & -pagesz; 577 align = dvma_cachealign ? dvma_cachealign : map->_dm_align; 578 579 s = splhigh(); 580 error = extent_alloc_subregion1(iommu_dvmamap, 581 map->_dm_ex_start, map->_dm_ex_end, 582 sgsize, align, va & (align-1), 583 map->_dm_boundary, 584 (flags & BUS_DMA_NOWAIT) == 0 585 ? EX_WAITOK : EX_NOWAIT, 586 &dvaddr); 587 splx(s); 588 *dvap = (bus_addr_t)dvaddr; 589 *sgsizep = sgsize; 590 return (error); 591 } 592 593 /* 594 * Prepare buffer for DMA transfer. 595 */ 596 int 597 iommu_dmamap_load(t, map, buf, buflen, p, flags) 598 bus_dma_tag_t t; 599 bus_dmamap_t map; 600 void *buf; 601 bus_size_t buflen; 602 struct proc *p; 603 int flags; 604 { 605 bus_size_t sgsize; 606 bus_addr_t dva; 607 vaddr_t va = (vaddr_t)buf; 608 int pagesz = PAGE_SIZE; 609 pmap_t pmap; 610 int error; 611 612 /* 613 * Make sure that on error condition we return "no valid mappings". 614 */ 615 map->dm_nsegs = 0; 616 617 /* Allocate IOMMU resources */ 618 if ((error = iommu_dvma_alloc(map, va, buflen, flags, 619 &dva, &sgsize)) != 0) 620 return (error); 621 622 cpuinfo.cache_flush(buf, buflen); /* XXX - move to bus_dma_sync? */ 623 624 /* 625 * We always use just one segment. 626 */ 627 map->dm_mapsize = buflen; 628 map->dm_nsegs = 1; 629 map->dm_segs[0].ds_addr = dva + (va & (pagesz - 1)); 630 map->dm_segs[0].ds_len = buflen; 631 map->dm_segs[0]._ds_sgsize = sgsize; 632 633 if (p != NULL) 634 pmap = p->p_vmspace->vm_map.pmap; 635 else 636 pmap = pmap_kernel(); 637 638 for (; sgsize != 0; ) { 639 paddr_t pa; 640 /* 641 * Get the physical address for this page. 642 */ 643 (void) pmap_extract(pmap, va, &pa); 644 645 iommu_enter(dva, pa); 646 647 dva += pagesz; 648 va += pagesz; 649 sgsize -= pagesz; 650 } 651 652 return (0); 653 } 654 655 /* 656 * Like _bus_dmamap_load(), but for mbufs. 657 */ 658 int 659 iommu_dmamap_load_mbuf(t, map, m, flags) 660 bus_dma_tag_t t; 661 bus_dmamap_t map; 662 struct mbuf *m; 663 int flags; 664 { 665 666 panic("_bus_dmamap_load_mbuf: not implemented"); 667 } 668 669 /* 670 * Like _bus_dmamap_load(), but for uios. 671 */ 672 int 673 iommu_dmamap_load_uio(t, map, uio, flags) 674 bus_dma_tag_t t; 675 bus_dmamap_t map; 676 struct uio *uio; 677 int flags; 678 { 679 680 panic("_bus_dmamap_load_uio: not implemented"); 681 } 682 683 /* 684 * Like _bus_dmamap_load(), but for raw memory allocated with 685 * bus_dmamem_alloc(). 686 */ 687 int 688 iommu_dmamap_load_raw(t, map, segs, nsegs, size, flags) 689 bus_dma_tag_t t; 690 bus_dmamap_t map; 691 bus_dma_segment_t *segs; 692 int nsegs; 693 bus_size_t size; 694 int flags; 695 { 696 struct vm_page *m; 697 paddr_t pa; 698 bus_addr_t dva; 699 bus_size_t sgsize; 700 struct pglist *mlist; 701 int pagesz = PAGE_SIZE; 702 int error; 703 704 map->dm_nsegs = 0; 705 706 /* Allocate IOMMU resources */ 707 if ((error = iommu_dvma_alloc(map, segs[0]._ds_va, size, 708 flags, &dva, &sgsize)) != 0) 709 return (error); 710 711 /* 712 * Note DVMA address in case bus_dmamem_map() is called later. 713 * It can then insure cache coherency by choosing a KVA that 714 * is aligned to `ds_addr'. 715 */ 716 segs[0].ds_addr = dva; 717 segs[0].ds_len = size; 718 719 map->dm_segs[0].ds_addr = dva; 720 map->dm_segs[0].ds_len = size; 721 map->dm_segs[0]._ds_sgsize = sgsize; 722 723 /* Map physical pages into IOMMU */ 724 mlist = segs[0]._ds_mlist; 725 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 726 if (sgsize == 0) 727 panic("iommu_dmamap_load_raw: size botch"); 728 pa = VM_PAGE_TO_PHYS(m); 729 iommu_enter(dva, pa); 730 dva += pagesz; 731 sgsize -= pagesz; 732 } 733 734 map->dm_nsegs = 1; 735 map->dm_mapsize = size; 736 737 return (0); 738 } 739 740 /* 741 * Unload an IOMMU DMA map. 742 */ 743 void 744 iommu_dmamap_unload(t, map) 745 bus_dma_tag_t t; 746 bus_dmamap_t map; 747 { 748 bus_dma_segment_t *segs = map->dm_segs; 749 int nsegs = map->dm_nsegs; 750 bus_addr_t dva; 751 bus_size_t len; 752 int i, s, error; 753 754 for (i = 0; i < nsegs; i++) { 755 dva = segs[i].ds_addr & -PAGE_SIZE; 756 len = segs[i]._ds_sgsize; 757 758 iommu_remove(dva, len); 759 s = splhigh(); 760 error = extent_free(iommu_dvmamap, dva, len, EX_NOWAIT); 761 splx(s); 762 if (error != 0) 763 printf("warning: %ld of DVMA space lost\n", (long)len); 764 } 765 766 /* Mark the mappings as invalid. */ 767 map->dm_mapsize = 0; 768 map->dm_nsegs = 0; 769 } 770 771 /* 772 * DMA map synchronization. 773 */ 774 void 775 iommu_dmamap_sync(t, map, offset, len, ops) 776 bus_dma_tag_t t; 777 bus_dmamap_t map; 778 bus_addr_t offset; 779 bus_size_t len; 780 int ops; 781 { 782 783 /* 784 * XXX Should flush CPU write buffers. 785 */ 786 } 787 788 /* 789 * Map DMA-safe memory. 790 */ 791 int 792 iommu_dmamem_map(t, segs, nsegs, size, kvap, flags) 793 bus_dma_tag_t t; 794 bus_dma_segment_t *segs; 795 int nsegs; 796 size_t size; 797 caddr_t *kvap; 798 int flags; 799 { 800 struct vm_page *m; 801 vaddr_t va; 802 bus_addr_t addr; 803 struct pglist *mlist; 804 int cbit; 805 u_long align; 806 int pagesz = PAGE_SIZE; 807 808 if (nsegs != 1) 809 panic("iommu_dmamem_map: nsegs = %d", nsegs); 810 811 cbit = has_iocache ? 0 : PMAP_NC; 812 align = dvma_cachealign ? dvma_cachealign : pagesz; 813 814 size = round_page(size); 815 816 /* 817 * In case the segment has already been loaded by 818 * iommu_dmamap_load_raw(), find a region of kernel virtual 819 * addresses that can accomodate our aligment requirements. 820 */ 821 va = _bus_dma_valloc_skewed(size, 0, align, 822 segs[0].ds_addr & (align - 1)); 823 if (va == 0) 824 return (ENOMEM); 825 826 segs[0]._ds_va = va; 827 *kvap = (caddr_t)va; 828 829 /* 830 * Map the pages allocated in _bus_dmamem_alloc() to the 831 * kernel virtual address space. 832 */ 833 mlist = segs[0]._ds_mlist; 834 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 835 836 if (size == 0) 837 panic("iommu_dmamem_map: size botch"); 838 839 addr = VM_PAGE_TO_PHYS(m); 840 pmap_enter(pmap_kernel(), va, addr | cbit, 841 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED); 842 #if 0 843 if (flags & BUS_DMA_COHERENT) 844 /* XXX */; 845 #endif 846 va += pagesz; 847 size -= pagesz; 848 } 849 pmap_update(pmap_kernel()); 850 851 return (0); 852 } 853 854 /* 855 * mmap(2)'ing DMA-safe memory. 856 */ 857 paddr_t 858 iommu_dmamem_mmap(t, segs, nsegs, off, prot, flags) 859 bus_dma_tag_t t; 860 bus_dma_segment_t *segs; 861 int nsegs; 862 off_t off; 863 int prot, flags; 864 { 865 866 panic("_bus_dmamem_mmap: not implemented"); 867 } 868
Indexes created Tue Sep 30 20:09:53 GMT 2025