iommu.c revision 1.78
1 /* $NetBSD: iommu.c,v 1.78 2004/03/17 17:04:59 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1995 Paul Kranenburg 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Aaron Brown and 19 * Harvard University. 20 * This product includes software developed by Paul Kranenburg. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: iommu.c,v 1.78 2004/03/17 17:04:59 pk Exp $"); 41 42 #include "opt_sparc_arch.h" 43 44 #include <sys/param.h> 45 #include <sys/extent.h> 46 #include <sys/malloc.h> 47 #include <sys/queue.h> 48 #include <sys/systm.h> 49 #include <sys/device.h> 50 #include <sys/proc.h> 51 52 #include <uvm/uvm.h> 53 54 #define _SPARC_BUS_DMA_PRIVATE 55 #include <machine/bus.h> 56 #include <machine/autoconf.h> 57 #include <machine/ctlreg.h> 58 #include <sparc/sparc/asm.h> 59 #include <sparc/sparc/vaddrs.h> 60 #include <sparc/sparc/cpuvar.h> 61 #include <sparc/sparc/iommureg.h> 62 #include <sparc/sparc/iommuvar.h> 63 64 struct iommu_softc { 65 struct device sc_dev; /* base device */ 66 struct iommureg *sc_reg; 67 u_int sc_pagesize; 68 u_int sc_range; 69 bus_addr_t sc_dvmabase; 70 iopte_t *sc_ptes; 71 int sc_hasiocache; 72 /* 73 * Note: operations on the extent map are being protected with 74 * splhigh(), since we cannot predict at which interrupt priority 75 * our clients will run. 76 */ 77 struct sparc_bus_dma_tag sc_dmatag; 78 struct extent *sc_dvmamap; 79 }; 80 static int has_iocache; 81 82 /* autoconfiguration driver */ 83 int iommu_print __P((void *, const char *)); 84 void iommu_attach __P((struct device *, struct device *, void *)); 85 int iommu_match __P((struct device *, struct cfdata *, void *)); 86 87 #if defined(SUN4M) 88 static void iommu_copy_prom_entries __P((struct iommu_softc *)); 89 #endif 90 91 CFATTACH_DECL(iommu, sizeof(struct iommu_softc), 92 iommu_match, iommu_attach, NULL, NULL); 93 94 /* IOMMU DMA map functions */ 95 int iommu_dmamap_create __P((bus_dma_tag_t, bus_size_t, int, bus_size_t, 96 bus_size_t, int, bus_dmamap_t *)); 97 int iommu_dmamap_load __P((bus_dma_tag_t, bus_dmamap_t, void *, 98 bus_size_t, struct proc *, int)); 99 int iommu_dmamap_load_mbuf __P((bus_dma_tag_t, bus_dmamap_t, 100 struct mbuf *, int)); 101 int iommu_dmamap_load_uio __P((bus_dma_tag_t, bus_dmamap_t, 102 struct uio *, int)); 103 int iommu_dmamap_load_raw __P((bus_dma_tag_t, bus_dmamap_t, 104 bus_dma_segment_t *, int, bus_size_t, int)); 105 void iommu_dmamap_unload __P((bus_dma_tag_t, bus_dmamap_t)); 106 void iommu_dmamap_sync __P((bus_dma_tag_t, bus_dmamap_t, bus_addr_t, 107 bus_size_t, int)); 108 109 int iommu_dmamem_map __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 110 int nsegs, size_t size, caddr_t *kvap, int flags)); 111 paddr_t iommu_dmamem_mmap __P((bus_dma_tag_t tag, bus_dma_segment_t *segs, 112 int nsegs, off_t off, int prot, int flags)); 113 int iommu_dvma_alloc(struct iommu_softc *, bus_dmamap_t, vaddr_t, 114 bus_size_t, int, bus_addr_t *, bus_size_t *); 115 116 /* 117 * Print the location of some iommu-attached device (called just 118 * before attaching that device). If `iommu' is not NULL, the 119 * device was found but not configured; print the iommu as well. 120 * Return UNCONF (config_find ignores this if the device was configured). 121 */ 122 int 123 iommu_print(args, iommu) 124 void *args; 125 const char *iommu; 126 { 127 struct iommu_attach_args *ia = args; 128 129 if (iommu) 130 aprint_normal("%s at %s", ia->iom_name, iommu); 131 return (UNCONF); 132 } 133 134 int 135 iommu_match(parent, cf, aux) 136 struct device *parent; 137 struct cfdata *cf; 138 void *aux; 139 { 140 struct mainbus_attach_args *ma = aux; 141 142 if (CPU_ISSUN4 || CPU_ISSUN4C) 143 return (0); 144 return (strcmp(cf->cf_name, ma->ma_name) == 0); 145 } 146 147 /* 148 * Attach the iommu. 149 */ 150 void 151 iommu_attach(parent, self, aux) 152 struct device *parent; 153 struct device *self; 154 void *aux; 155 { 156 #if defined(SUN4M) 157 struct iommu_softc *sc = (struct iommu_softc *)self; 158 struct mainbus_attach_args *ma = aux; 159 struct sparc_bus_dma_tag *dmat = &sc->sc_dmatag; 160 bus_space_handle_t bh; 161 int node; 162 int js1_implicit_iommu; 163 int i, s; 164 u_int iopte_table_pa; 165 struct pglist mlist; 166 u_int size; 167 struct vm_page *m; 168 vaddr_t va; 169 170 dmat->_cookie = sc; 171 dmat->_dmamap_create = iommu_dmamap_create; 172 dmat->_dmamap_destroy = _bus_dmamap_destroy; 173 dmat->_dmamap_load = iommu_dmamap_load; 174 dmat->_dmamap_load_mbuf = iommu_dmamap_load_mbuf; 175 dmat->_dmamap_load_uio = iommu_dmamap_load_uio; 176 dmat->_dmamap_load_raw = iommu_dmamap_load_raw; 177 dmat->_dmamap_unload = iommu_dmamap_unload; 178 dmat->_dmamap_sync = iommu_dmamap_sync; 179 180 dmat->_dmamem_alloc = _bus_dmamem_alloc; 181 dmat->_dmamem_free = _bus_dmamem_free; 182 dmat->_dmamem_map = iommu_dmamem_map; 183 dmat->_dmamem_unmap = _bus_dmamem_unmap; 184 dmat->_dmamem_mmap = iommu_dmamem_mmap; 185 186 /* 187 * JS1/OF device tree does not have an iommu node and sbus 188 * node is directly under root. mainbus_attach detects this 189 * and calls us with sbus node instead so that we can attach 190 * implicit iommu and attach that sbus node under it. 191 */ 192 node = ma->ma_node; 193 if (strcmp(prom_getpropstring(node, "name"), "sbus") == 0) 194 js1_implicit_iommu = 1; 195 else 196 js1_implicit_iommu = 0; 197 198 /* 199 * Map registers into our space. The PROM may have done this 200 * already, but I feel better if we have our own copy. Plus, the 201 * prom doesn't map the entire register set. 202 * 203 * XXX struct iommureg is bigger than ra->ra_len; what are the 204 * other fields for? 205 */ 206 if (bus_space_map(ma->ma_bustag, ma->ma_paddr, 207 sizeof(struct iommureg), 0, &bh) != 0) { 208 printf("iommu_attach: cannot map registers\n"); 209 return; 210 } 211 sc->sc_reg = (struct iommureg *)bh; 212 213 sc->sc_hasiocache = js1_implicit_iommu ? 0 214 : node_has_property(node, "cache-coherence?"); 215 if (CACHEINFO.c_enabled == 0) /* XXX - is this correct? */ 216 sc->sc_hasiocache = 0; 217 has_iocache = sc->sc_hasiocache; /* Set global flag */ 218 219 sc->sc_pagesize = js1_implicit_iommu ? PAGE_SIZE 220 : prom_getpropint(node, "page-size", PAGE_SIZE), 221 222 /* 223 * Allocate memory for I/O pagetables. 224 * This takes 64K of contiguous physical memory to map 64M of 225 * DVMA space (starting at IOMMU_DVMA_BASE). 226 * The table must be aligned on a (-IOMMU_DVMA_BASE/pagesize) 227 * boundary (i.e. 64K for 64M of DVMA space). 228 */ 229 230 size = ((0 - IOMMU_DVMA_BASE) / sc->sc_pagesize) * sizeof(iopte_t); 231 if (uvm_pglistalloc(size, vm_first_phys, vm_first_phys+vm_num_phys, 232 size, 0, &mlist, 1, 0) != 0) 233 panic("iommu_attach: no memory"); 234 235 va = uvm_km_valloc(kernel_map, size); 236 if (va == 0) 237 panic("iommu_attach: no memory"); 238 239 sc->sc_ptes = (iopte_t *)va; 240 241 m = TAILQ_FIRST(&mlist); 242 iopte_table_pa = VM_PAGE_TO_PHYS(m); 243 244 /* Map the pages */ 245 for (; m != NULL; m = TAILQ_NEXT(m,pageq)) { 246 paddr_t pa = VM_PAGE_TO_PHYS(m); 247 pmap_kenter_pa(va, pa | PMAP_NC, VM_PROT_READ | VM_PROT_WRITE); 248 va += PAGE_SIZE; 249 } 250 pmap_update(pmap_kernel()); 251 252 /* 253 * Copy entries from current IOMMU table. 254 * XXX - Why do we need to do this? 255 */ 256 iommu_copy_prom_entries(sc); 257 258 /* 259 * Now we can install our new pagetable into the IOMMU 260 */ 261 sc->sc_range = 0 - IOMMU_DVMA_BASE; 262 sc->sc_dvmabase = IOMMU_DVMA_BASE; 263 264 /* calculate log2(sc->sc_range/16MB) */ 265 i = ffs(sc->sc_range/(1 << 24)) - 1; 266 if ((1 << i) != (sc->sc_range/(1 << 24))) 267 panic("iommu: bad range: %d", i); 268 269 s = splhigh(); 270 IOMMU_FLUSHALL(sc); 271 272 /* Load range and physical address of PTEs */ 273 sc->sc_reg->io_cr = (sc->sc_reg->io_cr & ~IOMMU_CTL_RANGE) | 274 (i << IOMMU_CTL_RANGESHFT) | IOMMU_CTL_ME; 275 sc->sc_reg->io_bar = (iopte_table_pa >> 4) & IOMMU_BAR_IBA; 276 277 IOMMU_FLUSHALL(sc); 278 splx(s); 279 280 printf(": version 0x%x/0x%x, page-size %d, range %dMB\n", 281 (sc->sc_reg->io_cr & IOMMU_CTL_VER) >> 24, 282 (sc->sc_reg->io_cr & IOMMU_CTL_IMPL) >> 28, 283 sc->sc_pagesize, 284 sc->sc_range >> 20); 285 286 sc->sc_dvmamap = extent_create("iommudvma", 287 IOMMU_DVMA_BASE, IOMMU_DVMA_END, 288 M_DEVBUF, 0, 0, EX_NOWAIT); 289 if (sc->sc_dvmamap == NULL) 290 panic("iommu: unable to allocate DVMA map"); 291 292 /* 293 * If we are attaching implicit iommu on JS1/OF we do not have 294 * an iommu node to traverse, instead mainbus_attach passed us 295 * sbus node in ma.ma_node. Attach it as the only iommu child. 296 */ 297 if (js1_implicit_iommu) { 298 struct iommu_attach_args ia; 299 struct openprom_addr sbus_iommu_reg = { 0, 0x10001000, 0x28 }; 300 301 bzero(&ia, sizeof ia); 302 303 /* Propagate BUS & DMA tags */ 304 ia.iom_bustag = ma->ma_bustag; 305 ia.iom_dmatag = &sc->sc_dmatag; 306 307 ia.iom_name = "sbus"; 308 ia.iom_node = node; 309 ia.iom_reg = &sbus_iommu_reg; 310 ia.iom_nreg = 1; 311 312 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 313 return; 314 } 315 316 /* 317 * Loop through ROM children (expect Sbus among them). 318 */ 319 for (node = firstchild(node); node; node = nextsibling(node)) { 320 struct iommu_attach_args ia; 321 322 bzero(&ia, sizeof ia); 323 ia.iom_name = prom_getpropstring(node, "name"); 324 325 /* Propagate BUS & DMA tags */ 326 ia.iom_bustag = ma->ma_bustag; 327 ia.iom_dmatag = &sc->sc_dmatag; 328 329 ia.iom_node = node; 330 331 ia.iom_reg = NULL; 332 prom_getprop(node, "reg", sizeof(struct openprom_addr), 333 &ia.iom_nreg, &ia.iom_reg); 334 335 (void) config_found(&sc->sc_dev, (void *)&ia, iommu_print); 336 if (ia.iom_reg != NULL) 337 free(ia.iom_reg, M_DEVBUF); 338 } 339 #endif 340 } 341 342 #if defined(SUN4M) 343 static void 344 iommu_copy_prom_entries(sc) 345 struct iommu_softc *sc; 346 { 347 u_int pbase, pa; 348 u_int range; 349 iopte_t *tpte_p; 350 u_int pagesz = sc->sc_pagesize; 351 int use_ac = (cpuinfo.cpu_impl == 4 && cpuinfo.mxcc); 352 u_int mmupcr_save; 353 354 /* 355 * We read in the original table using MMU bypass and copy all 356 * of its entries to the appropriate place in our new table, 357 * even if the sizes are different. 358 * This is pretty easy since we know DVMA ends at 0xffffffff. 359 */ 360 361 range = (1 << 24) << 362 ((sc->sc_reg->io_cr & IOMMU_CTL_RANGE) >> IOMMU_CTL_RANGESHFT); 363 364 pbase = (sc->sc_reg->io_bar & IOMMU_BAR_IBA) << 365 (14 - IOMMU_BAR_IBASHFT); 366 367 if (use_ac) { 368 /* 369 * Set MMU AC bit so we'll still read from the cache 370 * in by-pass mode. 371 */ 372 mmupcr_save = lda(SRMMU_PCR, ASI_SRMMU); 373 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save | VIKING_PCR_AC); 374 } else 375 mmupcr_save = 0; /* XXX - avoid GCC `unintialized' warning */ 376 377 /* Flush entire IOMMU TLB before messing with the in-memory tables */ 378 IOMMU_FLUSHALL(sc); 379 380 /* 381 * tpte_p = top of our PTE table 382 * pa = top of current PTE table 383 * Then work downwards and copy entries until we hit the bottom 384 * of either table. 385 */ 386 for (tpte_p = &sc->sc_ptes[((0 - IOMMU_DVMA_BASE)/pagesz) - 1], 387 pa = (u_int)pbase + (range/pagesz - 1)*sizeof(iopte_t); 388 tpte_p >= &sc->sc_ptes[0] && pa >= (u_int)pbase; 389 tpte_p--, pa -= sizeof(iopte_t)) { 390 391 *tpte_p = lda(pa, ASI_BYPASS); 392 } 393 394 if (use_ac) { 395 /* restore mmu after bug-avoidance */ 396 sta(SRMMU_PCR, ASI_SRMMU, mmupcr_save); 397 } 398 } 399 #endif 400 401 static void 402 iommu_enter(struct iommu_softc *sc, bus_addr_t dva, paddr_t pa) 403 { 404 int pte; 405 406 /* This routine relies on the fact that sc->sc_pagesize == PAGE_SIZE */ 407 408 #ifdef DIAGNOSTIC 409 if (dva < sc->sc_dvmabase) 410 panic("iommu_enter: dva 0x%lx not in DVMA space", (long)dva); 411 #endif 412 413 pte = atop(pa) << IOPTE_PPNSHFT; 414 pte &= IOPTE_PPN; 415 pte |= IOPTE_V | IOPTE_W | (has_iocache ? IOPTE_C : 0); 416 sc->sc_ptes[atop(dva - sc->sc_dvmabase)] = pte; 417 IOMMU_FLUSHPAGE(sc, dva); 418 } 419 420 /* 421 * iommu_remove: removes mappings created by iommu_enter 422 */ 423 static void 424 iommu_remove(struct iommu_softc *sc, bus_addr_t dva, bus_size_t len) 425 { 426 u_int pagesz = sc->sc_pagesize; 427 bus_addr_t base = sc->sc_dvmabase; 428 429 #ifdef DEBUG 430 if (dva < base) 431 panic("iommu_remove: va 0x%lx not in DVMA space", (long)dva); 432 #endif 433 434 while ((long)len > 0) { 435 #ifdef notyet 436 #ifdef DEBUG 437 if ((sc->sc_ptes[atop(dva - base)] & IOPTE_V) == 0) 438 panic("iommu_remove: clearing invalid pte at dva 0x%lx", 439 (long)dva); 440 #endif 441 #endif 442 sc->sc_ptes[atop(dva - base)] = 0; 443 IOMMU_FLUSHPAGE(sc, dva); 444 len -= pagesz; 445 dva += pagesz; 446 } 447 } 448 449 #if 0 /* These registers aren't there??? */ 450 void 451 iommu_error() 452 { 453 struct iommu_softc *sc = X; 454 struct iommureg *iop = sc->sc_reg; 455 456 printf("iommu: afsr 0x%x, afar 0x%x\n", iop->io_afsr, iop->io_afar); 457 printf("iommu: mfsr 0x%x, mfar 0x%x\n", iop->io_mfsr, iop->io_mfar); 458 } 459 int 460 iommu_alloc(va, len) 461 u_int va, len; 462 { 463 struct iommu_softc *sc = X; 464 int off, tva, iovaddr, pte; 465 paddr_t pa; 466 467 off = (int)va & PGOFSET; 468 len = round_page(len + off); 469 va -= off; 470 471 if ((int)sc->sc_dvmacur + len > 0) 472 sc->sc_dvmacur = sc->sc_dvmabase; 473 474 iovaddr = tva = sc->sc_dvmacur; 475 sc->sc_dvmacur += len; 476 while (len) { 477 (void) pmap_extract(pmap_kernel(), va, &pa); 478 479 #define IOMMU_PPNSHIFT 8 480 #define IOMMU_V 0x00000002 481 #define IOMMU_W 0x00000004 482 483 pte = atop(pa) << IOMMU_PPNSHIFT; 484 pte |= IOMMU_V | IOMMU_W; 485 sta(sc->sc_ptes + atop(tva - sc->sc_dvmabase), ASI_BYPASS, pte); 486 sc->sc_reg->io_flushpage = tva; 487 len -= PAGE_SIZE; 488 va += PAGE_SIZE; 489 tva += PAGE_SIZE; 490 } 491 return iovaddr + off; 492 } 493 #endif 494 495 496 /* 497 * IOMMU DMA map functions. 498 */ 499 int 500 iommu_dmamap_create(t, size, nsegments, maxsegsz, boundary, flags, dmamp) 501 bus_dma_tag_t t; 502 bus_size_t size; 503 int nsegments; 504 bus_size_t maxsegsz; 505 bus_size_t boundary; 506 int flags; 507 bus_dmamap_t *dmamp; 508 { 509 struct iommu_softc *sc = t->_cookie; 510 bus_dmamap_t map; 511 int error; 512 513 if ((error = _bus_dmamap_create(t, size, nsegments, maxsegsz, 514 boundary, flags, &map)) != 0) 515 return (error); 516 517 if ((flags & BUS_DMA_24BIT) != 0) { 518 /* Limit this map to the range usable by `24-bit' devices */ 519 map->_dm_ex_start = D24_DVMA_BASE; 520 map->_dm_ex_end = D24_DVMA_END; 521 } else { 522 /* Enable allocations from the entire map */ 523 map->_dm_ex_start = sc->sc_dvmamap->ex_start; 524 map->_dm_ex_end = sc->sc_dvmamap->ex_end; 525 } 526 527 *dmamp = map; 528 return (0); 529 } 530 531 /* 532 * Internal routine to allocate space in the IOMMU map. 533 */ 534 int 535 iommu_dvma_alloc(sc, map, va, len, flags, dvap, sgsizep) 536 struct iommu_softc *sc; 537 bus_dmamap_t map; 538 vaddr_t va; 539 bus_size_t len; 540 int flags; 541 bus_addr_t *dvap; 542 bus_size_t *sgsizep; 543 { 544 bus_size_t sgsize; 545 u_long align, voff, dvaddr; 546 int s, error; 547 int pagesz = PAGE_SIZE; 548 549 /* 550 * Remember page offset, then truncate the buffer address to 551 * a page boundary. 552 */ 553 voff = va & (pagesz - 1); 554 va &= -pagesz; 555 556 if (len > map->_dm_size) 557 return (EINVAL); 558 559 sgsize = (len + voff + pagesz - 1) & -pagesz; 560 align = dvma_cachealign ? dvma_cachealign : map->_dm_align; 561 562 s = splhigh(); 563 error = extent_alloc_subregion1(sc->sc_dvmamap, 564 map->_dm_ex_start, map->_dm_ex_end, 565 sgsize, align, va & (align-1), 566 map->_dm_boundary, 567 (flags & BUS_DMA_NOWAIT) == 0 568 ? EX_WAITOK : EX_NOWAIT, 569 &dvaddr); 570 splx(s); 571 *dvap = (bus_addr_t)dvaddr; 572 *sgsizep = sgsize; 573 return (error); 574 } 575 576 /* 577 * Prepare buffer for DMA transfer. 578 */ 579 int 580 iommu_dmamap_load(t, map, buf, buflen, p, flags) 581 bus_dma_tag_t t; 582 bus_dmamap_t map; 583 void *buf; 584 bus_size_t buflen; 585 struct proc *p; 586 int flags; 587 { 588 struct iommu_softc *sc = t->_cookie; 589 bus_size_t sgsize; 590 bus_addr_t dva; 591 vaddr_t va = (vaddr_t)buf; 592 int pagesz = PAGE_SIZE; 593 pmap_t pmap; 594 int error; 595 596 /* 597 * Make sure that on error condition we return "no valid mappings". 598 */ 599 map->dm_nsegs = 0; 600 601 /* Allocate IOMMU resources */ 602 if ((error = iommu_dvma_alloc(sc, map, va, buflen, flags, 603 &dva, &sgsize)) != 0) 604 return (error); 605 606 cache_flush(buf, buflen); /* XXX - move to bus_dma_sync? */ 607 608 /* 609 * We always use just one segment. 610 */ 611 map->dm_mapsize = buflen; 612 map->dm_nsegs = 1; 613 map->dm_segs[0].ds_addr = dva + (va & (pagesz - 1)); 614 map->dm_segs[0].ds_len = buflen; 615 map->dm_segs[0]._ds_sgsize = sgsize; 616 617 if (p != NULL) 618 pmap = p->p_vmspace->vm_map.pmap; 619 else 620 pmap = pmap_kernel(); 621 622 for (; sgsize != 0; ) { 623 paddr_t pa; 624 /* 625 * Get the physical address for this page. 626 */ 627 (void) pmap_extract(pmap, va, &pa); 628 629 iommu_enter(sc, dva, pa); 630 631 dva += pagesz; 632 va += pagesz; 633 sgsize -= pagesz; 634 } 635 636 return (0); 637 } 638 639 /* 640 * Like _bus_dmamap_load(), but for mbufs. 641 */ 642 int 643 iommu_dmamap_load_mbuf(t, map, m, flags) 644 bus_dma_tag_t t; 645 bus_dmamap_t map; 646 struct mbuf *m; 647 int flags; 648 { 649 650 panic("_bus_dmamap_load_mbuf: not implemented"); 651 } 652 653 /* 654 * Like _bus_dmamap_load(), but for uios. 655 */ 656 int 657 iommu_dmamap_load_uio(t, map, uio, flags) 658 bus_dma_tag_t t; 659 bus_dmamap_t map; 660 struct uio *uio; 661 int flags; 662 { 663 664 panic("_bus_dmamap_load_uio: not implemented"); 665 } 666 667 /* 668 * Like _bus_dmamap_load(), but for raw memory allocated with 669 * bus_dmamem_alloc(). 670 */ 671 int 672 iommu_dmamap_load_raw(t, map, segs, nsegs, size, flags) 673 bus_dma_tag_t t; 674 bus_dmamap_t map; 675 bus_dma_segment_t *segs; 676 int nsegs; 677 bus_size_t size; 678 int flags; 679 { 680 struct iommu_softc *sc = t->_cookie; 681 struct vm_page *m; 682 paddr_t pa; 683 bus_addr_t dva; 684 bus_size_t sgsize; 685 struct pglist *mlist; 686 int pagesz = PAGE_SIZE; 687 int error; 688 689 map->dm_nsegs = 0; 690 691 /* Allocate IOMMU resources */ 692 if ((error = iommu_dvma_alloc(sc, map, segs[0]._ds_va, size, 693 flags, &dva, &sgsize)) != 0) 694 return (error); 695 696 /* 697 * Note DVMA address in case bus_dmamem_map() is called later. 698 * It can then insure cache coherency by choosing a KVA that 699 * is aligned to `ds_addr'. 700 */ 701 segs[0].ds_addr = dva; 702 segs[0].ds_len = size; 703 704 map->dm_segs[0].ds_addr = dva; 705 map->dm_segs[0].ds_len = size; 706 map->dm_segs[0]._ds_sgsize = sgsize; 707 708 /* Map physical pages into IOMMU */ 709 mlist = segs[0]._ds_mlist; 710 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 711 if (sgsize == 0) 712 panic("iommu_dmamap_load_raw: size botch"); 713 pa = VM_PAGE_TO_PHYS(m); 714 iommu_enter(sc, dva, pa); 715 dva += pagesz; 716 sgsize -= pagesz; 717 } 718 719 map->dm_nsegs = 1; 720 map->dm_mapsize = size; 721 722 return (0); 723 } 724 725 /* 726 * Unload an IOMMU DMA map. 727 */ 728 void 729 iommu_dmamap_unload(t, map) 730 bus_dma_tag_t t; 731 bus_dmamap_t map; 732 { 733 struct iommu_softc *sc = t->_cookie; 734 bus_dma_segment_t *segs = map->dm_segs; 735 int nsegs = map->dm_nsegs; 736 bus_addr_t dva; 737 bus_size_t len; 738 int i, s, error; 739 740 for (i = 0; i < nsegs; i++) { 741 dva = segs[i].ds_addr & -PAGE_SIZE; 742 len = segs[i]._ds_sgsize; 743 744 iommu_remove(sc, dva, len); 745 s = splhigh(); 746 error = extent_free(sc->sc_dvmamap, dva, len, EX_NOWAIT); 747 splx(s); 748 if (error != 0) 749 printf("warning: %ld of DVMA space lost\n", (long)len); 750 } 751 752 /* Mark the mappings as invalid. */ 753 map->dm_mapsize = 0; 754 map->dm_nsegs = 0; 755 } 756 757 /* 758 * DMA map synchronization. 759 */ 760 void 761 iommu_dmamap_sync(t, map, offset, len, ops) 762 bus_dma_tag_t t; 763 bus_dmamap_t map; 764 bus_addr_t offset; 765 bus_size_t len; 766 int ops; 767 { 768 769 /* 770 * XXX Should flush CPU write buffers. 771 */ 772 } 773 774 /* 775 * Map DMA-safe memory. 776 */ 777 int 778 iommu_dmamem_map(t, segs, nsegs, size, kvap, flags) 779 bus_dma_tag_t t; 780 bus_dma_segment_t *segs; 781 int nsegs; 782 size_t size; 783 caddr_t *kvap; 784 int flags; 785 { 786 struct vm_page *m; 787 vaddr_t va; 788 bus_addr_t addr; 789 struct pglist *mlist; 790 int cbit; 791 u_long align; 792 int pagesz = PAGE_SIZE; 793 794 if (nsegs != 1) 795 panic("iommu_dmamem_map: nsegs = %d", nsegs); 796 797 cbit = has_iocache ? 0 : PMAP_NC; 798 align = dvma_cachealign ? dvma_cachealign : pagesz; 799 800 size = round_page(size); 801 802 /* 803 * In case the segment has already been loaded by 804 * iommu_dmamap_load_raw(), find a region of kernel virtual 805 * addresses that can accomodate our aligment requirements. 806 */ 807 va = _bus_dma_valloc_skewed(size, 0, align, 808 segs[0].ds_addr & (align - 1)); 809 if (va == 0) 810 return (ENOMEM); 811 812 segs[0]._ds_va = va; 813 *kvap = (caddr_t)va; 814 815 /* 816 * Map the pages allocated in _bus_dmamem_alloc() to the 817 * kernel virtual address space. 818 */ 819 mlist = segs[0]._ds_mlist; 820 for (m = TAILQ_FIRST(mlist); m != NULL; m = TAILQ_NEXT(m,pageq)) { 821 822 if (size == 0) 823 panic("iommu_dmamem_map: size botch"); 824 825 addr = VM_PAGE_TO_PHYS(m); 826 pmap_kenter_pa(va, addr | cbit, VM_PROT_READ | VM_PROT_WRITE); 827 #if 0 828 if (flags & BUS_DMA_COHERENT) 829 /* XXX */; 830 #endif 831 va += pagesz; 832 size -= pagesz; 833 } 834 pmap_update(pmap_kernel()); 835 836 return (0); 837 } 838 839 /* 840 * mmap(2)'ing DMA-safe memory. 841 */ 842 paddr_t 843 iommu_dmamem_mmap(t, segs, nsegs, off, prot, flags) 844 bus_dma_tag_t t; 845 bus_dma_segment_t *segs; 846 int nsegs; 847 off_t off; 848 int prot, flags; 849 { 850 851 panic("_bus_dmamem_mmap: not implemented"); 852 } 853
Indexes created Wed Oct 01 12:09:54 GMT 2025